JPH0719238B2 - Serial bus advance control system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for performing direct memory access using serial transfer, and more particularly to minimizing the memory occupation time and the time required for the entire direct memory access. And the serial bus advance control method.

[Conventional technology]

Main processor and memory
FIG. 3 shows a conventional example in which an input / output device for memory access (hereinafter referred to as DMA) is connected. In FIG. 3, 1 is a main processor, 2 is a memory, 31 and 32 are input / output devices, 4 is a memory bus, and 5 is an arbiter for arbitrating data transfer requests from a plurality of input / output devices.

A DMA sequence by the input / output device 31 in FIG. 3 is shown in FIG. In FIG. 4, REQ is a data transfer request, M
REQ is memory usage request, MACK is memory usage permission, ACK is data transfer permission, ADR is DMA address, DATA is DMA data, D
ACK is a data acknowledge (access complete) signal. Furthermore, a signal with "one" means turning off the signal.

By the way, when connecting the input / output device and the memory bus with a cable, the number of signal lines and the number of buffer elements increase in proportion to the memory bus width. In order to prevent this, serial transfer between the input / output device and the memory bus can be considered. For example, if a memory bus with 24-bit data and 32-bit data is replaced with an 8-bit serial bus that shares address and data, the number of signal lines and the number of buffer elements will be 1 /
7 FIG. 5 is a conventional configuration diagram of a system using a serial bus. In this conventional example, a memory side data conversion device 6 is provided between the memory bus 4 and the serial bus 8, and input / output device side data conversion devices 71 and 72 are provided between the input / output devices 31 and 32 and the serial bus 8, respectively. Is provided. In addition, 1,
2, 5 are the same as in FIG.

Incidentally, as one related to the prior art shown in FIG. 5, for example, Hitachi Microcomputer Data Book / 8 bit / 16
Bit multi-chip P882, HMCS68000 system device connection example (1984) is.

[Problems to be solved by the invention]

The prior art DMA sequence shown in FIG. 5 is as shown in FIG. In other words, the transfer time of DMA address (ADR) and DMA data (DATA) becomes long, and the memory 2
There is a problem that the monopolization time of the system increases and the processing capacity of the system decreases.

By the way, if the serial transfer cycle is 250 nS, the memory usage request from the main processor to the usage permission is 500 nS, the memory access time is 500 nS, and other delays are ignored, D
The MA required time (from data transfer request ON to data transfer permission OFF) and memory occupation time (memory use permission ON period) are required time: 2750nS and occupation time: 2250nS in the case of the configuration shown in FIG.

It is an object of the present invention to provide a serial bus advance control method that minimizes the memory occupation time by the DMA when serial transfer is used for the DMA of the input / output device and further minimizes the time required for the entire DMA.

[Means for solving problems]

The above-mentioned object is to output a memory use request before completion of data reception so that the memory side data conversion device can receive the memory use permission at the time of completion of reception of serial data. Is achieved by receiving the data transfer request from the input / output device, simultaneously outputting the serial transfer request to the memory side data conversion device, and receiving the serial transfer permission from the device.

[Action]

In order for the memory side data converter to access the memory, it is necessary to complete the serial transfer and receive the memory use permission. If the former is earlier than the latter, the data is held in the memory side data conversion device. On the other hand, if the latter is faster than the former, it will occupy extra memory until the serial transfer is completed, and the memory occupancy time by DMA will increase. However, in the present invention, since the memory use request is output before the completion of data reception, both can be made simultaneous, and the data hold time and the memory monopolization time in the same device can be minimized.

Furthermore, since the input / output device side data conversion device outputs the serial transfer request at the same time as the data transfer request is received by the device, the serial transfer permission can be obtained earliest. That is, the data hold time in the device is minimized.

Therefore, the memory occupation time by the DMA and the ownership time of the entire DMA are minimized.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a system configuration diagram to which a serial bus advance control system according to an embodiment of the present invention is applied. In FIG. 1, the main processor 1 and the memory 2 are connected by a memory bus 4. The memory bus 4 and the serial bus 8 are connected by a memory side data conversion device 6, and the input / output device 3
1, 32 are connected to the serial bus 8 via input / output side data converters 71, 72, respectively. The arbiter 5 includes a memory side data conversion device 6 and an input device side data conversion device 71, 72.
Control signals are transmitted and received between and. Further, control signals are directly transmitted and received between the main processor 1 and the data conversion device 6, and between the input / output devices 31 and 32 and the data conversion devices 71 and 72, respectively.

A sequence of DMA write and DMA read performed between the input / output device (IO) 31 and the memory 2 in the system having such a configuration will be described with reference to FIG.

When performing a DMA write, the input / output device (IO) 31 outputs a data transfer request REQ to the data conversion device (CONV) 71. Upon receiving this request REQ, the data conversion device 71 returns a data transfer permission ACK to the input / output device 31, and at the same time sends a serial transfer request SREQ to the data conversion device (CONV) 6 via the arbiter 5. When the data converter 71 receives the serial transfer permission SACK from the data converter 6 via the arbiter 5, the data converter 71 determines that the input / output device 31
DMA address and DMA data ADR + DATA sent from
Are serially transferred to the data converter 6 via the serial bus 8.

On the other hand, the data converter 6 outputs the memory transfer request SACK to the completion of reception of the serial transfer a, and outputs the memory use request MREQ to the memory use enable.
Assuming that the time until MACK is received is b, the memory use request MREQ is output to the main processor 1 ab after the serial transfer permission SACK is output. If a <b,
The memory use request MREQ is output with ab = 0. As a result, the completion of the serial transfer and the reception of the memory use permission MACK become simultaneous, and the write operation to the memory 2 is performed under this condition.

When the memory write is completed, the data acknowledge DACK is output from the memory 2 to the input / output device 31 via the data conversion device 6. As a result, the above request signals and permission signals are turned off.

Also when performing a DMA read, the DMA read address ADR is sent to the memory 2 in the same sequence as the above DMA write sequence, and the read data DATA is read from the memory 2 to the input / output device 31.

According to the present embodiment, under the conditions of the conventional example shown in FIG. 5, the required time is 2250 nS and the occupation time is 500 nS, and the required time is reduced to about 82% and the occupation time to about 22%. It is clear that this value is the minimum because the transfer data is not held in each data conversion device and the memory use permission is obtained only during the period of accessing the memory.

The off timing of the data transfer request (REQ) and the serial transfer request (SREQ) does not have to be the same as in FIG. For example, in the DMA write sequence, SREQ
May be turned off without having DACK at the end of serial transfer.

Also, from the memory use request output MREQ, the memory use enable MACK
If the time until receipt varies, the value that maximizes the throughput of the system from the maximum value to the minimum value may be set to b.

〔The invention's effect〕

According to the present invention, even when serial transfer is performed between the input / output device and the memory bus, the exclusive time of the memory bus by the DMA is minimized, and the time required for the entire DMA is also minimized.

[Brief description of drawings]

FIG. 1 is a system configuration diagram to which a serial bus advance control system according to an embodiment of the present invention is applied, FIG. 2 is a sequence of a serial bus advance control system according to an embodiment of the present invention, and FIG. FIG. 4 is a system configuration diagram, FIG. 4 is a sequence performed by the system of FIG. 3, FIG. 5 is another conventional system configuration diagram, and FIG. 6 is a sequence performed by the system of FIG. 1: main processor, 2: memory, 31 and 32: input / output device,
4: Memory bus, 5: Arbiter, 6: Data converter on memory side, 71 and 72: Data converter on I / O device side, 8: Serial bus, REQ: Data transfer request, ACK: Data transfer enable,
SREQ: Serial transfer request, SACK: Serial transfer enable, MRE
Q: Memory use request, MACK: Memory use permission.

 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Zenichi Yashiro 3-9-11 Midoricho, Musashino City, Tokyo Inside Nippon Telegraph and Telephone Corporation, Communication Network Research Laboratories (72) Inventor Shuichi Isoba 3 Midoricho, Musashino City, Tokyo 9-11, Nippon Telegraph and Telephone Corporation, Communication Network Research Laboratories

Claims (1)

[Claims] 1. An input / output device, a memory for direct memory access by the input / output device, a serial bus for serial data transfer, and an input / output for performing data conversion between the serial bus and the input / output device. The input / output device comprises a device-side data conversion device, a memory-side data conversion device for converting data between the serial bus and the memory, and a main processor that outputs a permission for use of the memory. Outputs a data transfer request for direct memory access to the data converter on the input / output device side, and the data converter on the input / output device side outputs a data transfer permission to the input / output device and simultaneously outputs the data on the memory side. A serial transfer request is output to the conversion device, and the data conversion device on the memory side serializes to the data conversion device on the input / output device side. In addition to outputting the transfer permission, the memory use request is output to the main processor before the completion of the reception of the serial data so that the memory use permission from the main processor can be obtained at the same time when the reception of the serial data is completed. Bus advance control system.