JPH07161996A - Insulated-gate field-effect device and its manufacture - Google Patents

Abstract

PURPOSE:To densify an SiO2 film near its boundary and restructure a network of boundary atoms to reduce boundary level density by treating a very thin SiO film with a plasma that contains nitrogen. CONSTITUTION:An amorphous silicon film.is deposited on a glass substrate 1 by LPCVD using Si2H6. An SiO2 film 3 for gate oxide is deposited on a semiconductor layer 2 by remote plasma CVD. The film thickness is preferably 1 to 10nm; if less than 1nm the semiconductor layer may be damaged, and if more than 10nm nitrogen may not diffuse to the boundary between the semiconductor layer and the oxide film 3. The SiO2 film is treated with N2 plasma for conversion to an SiON film. As a result, the SiO2 film is densified near the boundary and the boundary atoms are restructured, while the introduction of nitrogen with a coordination number of 3 reduces boundary level density.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect semiconductor device and its manufacturing method, and more particularly to an insulated gate field effect semiconductor device which can be manufactured by a low temperature process and its manufacturing method. .

[0002]

2. Description of the Related Art Recently, by using a glass substrate,
In a low temperature process of about 600 ° C, thin film transistors (hereinafter referred to as T
Abbreviated as FT).

When poly-Si or amorphous Si is used for the channel semiconductor layer of the TFT and a SiO ₂ film is used for the gate insulating film, the heat treatment temperature at the time of manufacturing the TFT is about 60.
It is 0 ° C or lower. Therefore, in order to form the SiO ₂ film of the gate insulating film, plasma C which can be formed at a low temperature can be used.
VD method (eg, Jounal of Applied Physics Vol. 60 (9)
p3136 (1986)), remote plasma CVD method (for example, J
ounal of Vacuum Science Technology A5 (4) p2231 (19
87)), APCVD method, LPCVD method, sputtering method
(For example, IEEE Trans.Electron Devices 135 (12) p3104
(1989)) and the like are used to form a gate insulating film. However, since the SiO ₂ film obtained by these methods is not dense, it causes a decrease in the reliability of the TFT.

Further, as a method of densifying these SiO ₂ films, there is a high temperature anneal at about 900 ° C. or a lamp anneal in an N ₂ atmosphere. A quality gate insulating film cannot be obtained.

Further, a technique for obtaining a highly reliable transistor which is resistant to hot carrier injection by nitriding a SiO ₂ film has been conventionally reported (for example, IEEE Trans. Electron.
Devices ED-29 p498 (1982)) also require high temperatures of 900 ° C or higher to perform nitriding.

[0006]

However, if the gate insulating film produced by the above method is produced at a relatively high temperature, or if it is produced at a low temperature of 600 ° C. or less, a dense and high quality product cannot be obtained. , The SiO ₂ film contains a large amount of traps, which adversely affects the TFT characteristics. Further, since these traps cause hot electron injection, there is a problem in reliability of the device. In addition, since the interface state density is high because of low temperature formation, it is difficult to form a good interface. On the other hand, due to thermal distortion, etc., TFT at low temperature
There are strong demands for fabrication.

The present invention has been made in view of such a problem. The density of the interface state is reduced by densifying the SiO ₂ film near the interface and reconfiguring the network of interface atoms, thereby reducing the interface state density. The purpose is to form a SiON layer to form a gate insulating film that is strong against hot electron injection, and obtain a high-quality gate insulating film at a relatively low temperature.

[0008]

According to another aspect of the present invention, there is provided an insulated gate field effect semiconductor device including a poly Si layer formed on an insulating substrate and an S formed on the poly Si layer.
It is characterized by comprising an insulated gate layer formed of an iON layer and a SiO ₂ layer formed on the SiON layer, and a gate electrode formed on the insulated gate layer.

According to another aspect of the present invention, there is provided an insulated gate field effect semiconductor device including poly-Si formed on an insulating substrate.
Layer, a SiON layer formed on the poly-Si layer, and the Si
An insulated gate layer formed of an SiO ₂ layer formed on the ON layer, a gate electrode formed on the insulated gate layer, and a source region and a drain region on the surface of the poly-Si layer are provided to form a TFT. It is characterized by being

An insulated gate field effect semiconductor device according to a third aspect of the present invention is the insulated gate field effect semiconductor device according to the first or second aspect, wherein
The layer thickness is 1 nm or more and 10 nm or less.

A method of manufacturing an insulated gate field effect semiconductor device according to a fourth aspect of the present invention is the method according to the first aspect, the second aspect, or the second aspect.
Alternatively, in the method for manufacturing the insulated gate field effect semiconductor device according to claim 3, a step of forming a poly-Si layer on the insulating substrate, and a step of forming a first SiO ₂ layer on the poly-Si layer, Plasma nitriding the first SiO ₂ layer to form Si
A step of forming an ON layer and a second SiO ₂ layer on the SiON layer.
The method is characterized by including a step of forming a layer and a step of forming a conductive film on the second SiO ₂ layer to form a gate electrode.

[0012]

According to the present invention, after forming an extremely thin (about 1 to 10 nm) insulating film, plasma nitriding treatment is subsequently performed with plasma of a gas containing N (nitrogen), so that the insulating film near the interface becomes dense. And the reconstruction of the interface atoms to reduce the interface state density of tricoordinate N and obtain a good interface, whereby it becomes possible to obtain TFT characteristics with high mobility, low Vth, and S coefficient. . In addition, since the SiON layer near the interface becomes strong against hot electron injection, the TF has excellent reliability.
T can be obtained.

In the present invention, the step of manufacturing the SiO ₂ film of the gate insulating film in the manufacturing process is divided into three steps, and first, an extremely thin (about 1 to 10 nm is most preferable) Si film is formed.
An O ₂ film is formed on the channel semiconductor, and then Si is formed by plasma of a gas containing N atoms such as N ₂ (for example, NH ₃ , N ₂ O, etc.).
Plasma treatment is performed from above O ₂ . Finally, a necessary SiO ₂ film is formed to form a gate insulating film. At this time, the initial Si
If the film thickness of O ₂ is too thick (usually 10 nm or more), the effect of plasma treatment on the SiO ₂ film in the vicinity of the interface is small, and if it is too thin (usually 1 nm or less), plasma damage to the channel semiconductor poses a problem. There is an optimum film thickness range according to the condition of.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a TFT according to an embodiment of the present invention will be described below with reference to the drawings. Although a poly-Si film is used as the channel semiconductor here, other Si-based semiconductors include amorphous Si, single crystal Si, and SiG.
It is also possible to use e or the like. Further, although a TFT will be described in the following embodiments, it is obvious that the TFT can be simply used as a gate insulating film of a capacitor by not forming a source and a drain described later. Further, it is possible to appropriately introduce impurities into the poly-Si film in order to adjust Vth and the like immediately below the gate insulating film.

First, as shown in FIG. 1 (a), about 600
An amorphous Si film is formed at a substrate temperature of about 450 ° C. by a LPCVD method using Si ₂ H ₆ gas on a glass substrate 1 having a high strain point temperature that can withstand a heat treatment at a temperature of ° C. The amorphous Si film is annealed at 600 ° C. for about 20 hours in an N ₂ atmosphere to obtain a poly Si film by solid phase growth, and is etched into an island in a desired shape to form the semiconductor layer 2.

Next, as shown in FIG. 1B, a SiO ₂ film 3 to be a gate insulating film is formed on the semiconductor layer 2 by a remote plasma CVD method to a film thickness of about 1 to 10 nm, in this embodiment 5 nm. Form a film. The film formation conditions by the remote plasma CVD method are a substrate temperature of 300 ° C. and a reaction pressure of 0.2 To.
rr, SiH ₄ flow rate 1 sccm, O ₂ flow rate 50 sccm,
The RF power was 200 W. The method of forming the SiO ₂ film 3 at this time is not limited to the remote plasma CVD method, and if the low temperature film formation is possible, the plasma CVD method, the ECRCVD method,
An LPCVD method, an APCVD method or the like may be used. Also, SiO
_{If the} film thickness of the _two films 3 is 10 nm or more, the effect of the plasma treatment described later is small, so 10 nm or less is desirable. Although the range of the film thickness varies depending on the plasma processing apparatus and the processing conditions, if the thickness is less than 1 nm, the semiconductor layer 2 will be damaged, and if it is more than 10 nm, the interface of the N (nitrogen) (semiconductor layer 2) will be damaged. And the plasma-treated SiO ₂ film 3) is not diffused, so that the effect of the plasma treatment is reduced. Therefore, the film thickness of the SiO ₂ film 3 is preferably 1 nm or more and 10 nm or less.

Next, as shown in FIG. 1C, a plasma treatment (N _{2 in} this case) with N ₂ plasma is continued for 10 minutes.
Although a gas is used, the gas is not particularly limited as long as it is a gas containing N such as N ₂ O or NH ₃ ) and SiO ₂
The film 3 is a SiON film. Here, it is not necessary to change the entire SiO ₂ film 3 into a SiON film. The conditions of the plasma treatment at this time are as follows: substrate temperature 300 ° C., reaction pressure 0.
5 Torr, N ₂ flow rate 100 sccm, power density 0.
It was performed at 1 W / cm ² . The plasma processing temperature is 6
It may be 00 ° C or lower. Further, although the plasma treatment is performed by the parallel plate plasma CVD apparatus here, it may be performed by a remote plasma CVD apparatus or an ECRCVD apparatus.

Next, as shown in FIG. 1D, SiO ₂
The film 3 ′ is formed to have a film thickness of about 90 to 100 nm, and in the present embodiment, 95.
A gate insulating film composed of a SiO ₂ film 3 and a SiO ₂ film 3 ′, which is formed by a remote plasma CVD apparatus and has a thickness of nm, is plasma-processed.

Next, as shown in FIG. 1E, a polysilicon Si film having a film thickness of about 250 nm is formed on the glass substrate 1 and patterned into a desired shape to form a gate electrode 4. In a self-aligned manner, the impurity element (phosphorus for Nch, boron for Pch) is added at 1 × 10 ¹⁵ ion /
Ions are implanted at a pressure of about cm ² and 40 keV and activated to form the source and drain of a TFT (not shown). Then, at the same time as this step, the resistance of the gate electrode 4 is reduced by impurity ion implantation, and then the film thickness 500 is obtained.
An interlayer insulating film 5 made of a SiO ₂ film having a thickness of about nm is formed.

Finally, as shown in FIG. 1F, a contact hole is formed in the interlayer insulating film 5 on the source and drain, and then an aluminum lead electrode 6 is formed to complete the TFT.

The TFT characteristics of the gate insulating film thus manufactured in three steps are as shown in the table below.

[0022]

[Table 1]

Here, as a comparative example, TFT characteristics produced by forming a SiO ₂ film by a remote plasma CVD method without plasma treatment are also shown. Here, the equivalent thickness of the gate insulating film of the TFT used as the comparative example and the gate insulating film of the TFT manufactured by applying the plasma treatment are the same. As is clear from the table, the mobility, Vth, and S coefficient are higher in mobility and lower in Vt than the TFT characteristics in which the gate insulating film is composed of the SiO ₂ film without plasma treatment.
h, a low S coefficient, indicating an improvement in the interface structure.

In FIG. 2, the electric field strength applied to the gate is 8 MV / c.
m, TDDB characteristics at an atmospheric temperature of 150 ° C. As is clear from this figure, the TDDB characteristics of the gate insulating film that has been subjected to the plasma treatment are superior to those of the characteristics that are not subjected to the plasma treatment, and it is possible to obtain a highly reliable insulating film in which electron injection does not easily occur. Has become. Therefore, it is understood that the TFT subjected to the plasma treatment is excellent not only in characteristics but also in reliability.

[0025]

According to the present invention, N is applied from the ultrathin SiO ₂ layer.
By treating with plasma of gas containing
The io ₂ layer was densified and the interface atoms were reconstructed,
By introducing the coordinated N to reduce the interface state density, TFT characteristics such as mobility, Vth, and S coefficient can be improved.

Further, since the SiON layer is formed on the interface layer, it becomes strong against hot electron injection, and a highly reliable TFT can be obtained.

[Brief description of drawings]

FIG. 1 is a gate insulating film and TF according to an embodiment of the present invention.
FIG. 6 is a process cross-sectional view showing the method of manufacturing T.

FIG. 2 is a graph showing TDDB characteristics of gate insulating films manufactured according to Examples and Comparative Examples of the present invention.

[Explanation of symbols]

1 glass substrate 2 semiconductor layer 3 plasma-treated SiO ₂ film 3'SiO ₂ film 4 gate electrode 5 interlayer insulating film 6 extraction electrode

Claims (4)

[Claims] 1. A poly-Si layer formed on an insulating substrate,
An insulated gate layer comprising a SiON layer formed on the poly-Si layer and a SiO ₂ layer formed on the SiON layer;
An insulated gate field effect semiconductor device, comprising: a gate electrode formed on the insulated gate layer. 2. A poly-Si layer formed on an insulating substrate,
An insulated gate layer comprising a SiON layer formed on the poly-Si layer and a SiO ₂ layer formed on the SiON layer;
A gate electrode formed on the insulated gate layer; and a source region and a drain region on the surface of the poly-Si layer.
An insulated gate field effect semiconductor device having T. 3. The thickness of the SiON layer is 1 nm or more 10
It is below 1 nm, Claim 1 or Claim 2 characterized by the above-mentioned.
Insulated gate type field effect semiconductor device according to. Forming a wherein the poly Si layer on an insulating substrate, forming a first SiO ₂ layer on the poly-Si layer, and the SiON layer of the first SiO ₂ layer to plasma nitriding And a step of forming a _second SiO ₂ layer on the SiON layer, and a step of forming a conductive film on the second SiO ₂ layer to form a gate electrode. A method of manufacturing an insulated gate field effect semiconductor device according to claim 1, claim 2, or claim 3.