JPH07169876A - Semiconductor device and mounting carrier thereof - Google Patents
Semiconductor device and mounting carrier thereofInfo
- Publication number
- JPH07169876A JPH07169876A JP6074697A JP7469794A JPH07169876A JP H07169876 A JPH07169876 A JP H07169876A JP 6074697 A JP6074697 A JP 6074697A JP 7469794 A JP7469794 A JP 7469794A JP H07169876 A JPH07169876 A JP H07169876A
- Authority
- JP
- Japan
- Prior art keywords
- mounting
- semiconductor device
- circuit pattern
- terminal
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及び半導体装
置用実装キャリアに関し、更に詳細には外部回路と接続
される実装端子が装着された半導体装置、及び一端部が
半導体装置本体のランド部に接続されると共に、他端部
が外部回路に接続される実装端子が端子基板に固着され
た半導体装置用実装キャリアに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device mounting carrier, and more particularly to a semiconductor device having mounting terminals connected to an external circuit, and one end of which is a land portion of the semiconductor device body. The present invention relates to a mounting carrier for a semiconductor device, to which a mounting terminal that is connected and whose other end is connected to an external circuit is fixed to a terminal board.
【０００２】[0002]
【従来の技術】先ず、従来の実装端子付半導体装置につ
いて図１３及び図１４を使用して説明する。図１１は、
従来から使用されている、実装端子が装着された実装端
子付半導体装置（例えばピングリッドアレイ型半導体装
置）１００の断面図である。図１１において、樹脂基板
１０２の下面に固着された半導体チップ１０４は、基板
１０２の下面に形成された回路パターン１０６の一端部
とワイヤで接続されている。かかる回路パターン１０６
は半導体チップ１０４の周囲に多数配設されている。2. Description of the Related Art First, a conventional semiconductor device with mounting terminals will be described with reference to FIGS. FIG. 11 shows
FIG. 11 is a cross-sectional view of a semiconductor device with mounting terminals (for example, a pin grid array type semiconductor device) 100, which is conventionally used and has mounting terminals attached thereto. In FIG. 11, the semiconductor chip 104 fixed to the lower surface of the resin substrate 102 is connected to one end of the circuit pattern 106 formed on the lower surface of the substrate 102 by a wire. Such circuit pattern 106
Are arranged around the semiconductor chip 104.
【０００３】これら半導体チップ１０４、半導体チップ
１０４と回路パターン１０６の接続部分１０８等は合成
樹脂で封止され、樹脂封止部１０８を形成する。一方、
回路パターン１０６の他端部には、中心部に透孔１１２
が透設されたランド部１１２が設けられている。この透
孔１１２の各々は、内壁面が金属めっきが施され、且つ
透孔１１２に挿着されたピン状の実装端子１１０は、は
んだ付けで固定されている。この様に、樹脂基板１０２
に透設された透孔１１２に固定された実装端子１１０
は、回路基板（不図示）に接続することによって、半導
体装置１００の表面実装を行うことができる。The semiconductor chip 104, the connecting portion 108 between the semiconductor chip 104 and the circuit pattern 106, and the like are sealed with a synthetic resin to form a resin sealing portion 108. on the other hand,
The other end of the circuit pattern 106 has a through hole 112 at the center.
The land portion 112 is provided so as to be transparent. An inner wall surface of each of the through holes 112 is metal-plated, and the pin-shaped mounting terminals 110 inserted into the through holes 112 are fixed by soldering. In this way, the resin substrate 102
Mounting terminal 110 fixed to a through hole 112 that is transparently provided in
Can be surface-mounted on the semiconductor device 100 by connecting to a circuit board (not shown).
【０００４】[0004]
【発明が解決しようとする課題】かかる図１３に示す実
装端子１１０が設けられた実装端子付半導体装置１００
によれば、半導体装置１００の表面実装を容易に行うこ
とができる。しかしながら、この従来の半導体装置１０
０、特にピングリッドアレイ型半導体装置においては、
ピン状の実装端子１１０を樹脂基板１０２に立設する場
合、樹脂基板１０２に透設された透孔１１２に実装端子
１１０を挿通することが、立設された実装端子１１０の
強度等の観点から必要である。更に、この透孔１１２
は、ランド部１１４の中央に透設されるため、ランド部
１１４の直径Ｚは透孔１１２の直径より大径となる。こ
のため、従来の半導体装置１００においては、例えば図
１４に示すように、２個の回路パターン１０６ａと１０
６ｂの間（距離Ｙ）に、他の回路パターン１０６を配設
する場合、回路パターン１０６の配設可能範囲Ｘは、Ｘ
＝Ｙ−Ｚとなる。従って、ランド部１１４の直径Ｚが大
きくなるほど、回路パターン１０６の配設可能範囲Ｘが
狭くなるため、配設可能範囲Ｘに配設し得る回路パター
ン１０６の本数が減少する。A semiconductor device with a mounting terminal 100 having the mounting terminal 110 shown in FIG. 13 is provided.
According to this, the surface mounting of the semiconductor device 100 can be easily performed. However, this conventional semiconductor device 10
0, especially in the pin grid array type semiconductor device,
When the pin-shaped mounting terminal 110 is erected on the resin substrate 102, it is necessary to insert the mounting terminal 110 into the through hole 112 pierced through the resin substrate 102 from the viewpoint of the strength of the erected mounting terminal 110 and the like. is necessary. Further, this through hole 112
Is transparently provided in the center of the land portion 114, so that the diameter Z of the land portion 114 is larger than the diameter of the through hole 112. Therefore, in the conventional semiconductor device 100, for example, as shown in FIG. 14, two circuit patterns 106a and 10a are provided.
When another circuit pattern 106 is arranged between 6b (distance Y), the disposition range X of the circuit pattern 106 is X.
= Y-Z. Therefore, the larger the diameter Z of the land portion 114, the narrower the disposition range X of the circuit pattern 106 becomes, and the number of circuit patterns 106 that can be arranged in the disposition range X decreases.
【０００５】一方、実装端子１１０を立設するための透
孔１１２は、ランド部１１４の中央に配設しなければな
らず、しかも実装端子１１０は、ある程度の太さが必要
であるため、実装端子１１０を挿通する透孔１１２は、
ランド部１１４の直径Ｚを小さくすることは困難であ
る。このため、実装端子付半導体装置１００において、
回路パターン１０６の更なる高密度化を図ることが困難
であり、昨今の回路パターンの高密度化の要請に応える
ことが困難となっている。そこで、本発明の目的は、実
装端子の固定用の透孔を不要とし、回路パターンの高密
度化を図り得る半導体装置を提供することにある。On the other hand, the through hole 112 for standingly mounting the mounting terminal 110 must be arranged at the center of the land portion 114, and the mounting terminal 110 needs to have a certain thickness, so that the mounting terminal 110 is mounted. The through hole 112 through which the terminal 110 is inserted is
It is difficult to reduce the diameter Z of the land portion 114. Therefore, in the semiconductor device 100 with mounting terminals,
It is difficult to further increase the density of the circuit pattern 106, and it is difficult to meet the recent demand for higher density of the circuit pattern. Therefore, an object of the present invention is to provide a semiconductor device that does not require a through hole for fixing a mounting terminal and can increase the density of a circuit pattern.
【０００６】[0006]
【課題を解決するための手段】かかる本発明の目的を達
成すべく検討した結果、半導体チップが搭載され且つ回
路パターンが形成された半導体装置本体に、別体に形成
された実装端子が立設された実装キャリアを装着するこ
とによって、半導体装置本体に実装端子固定用の透孔を
不用にできることを見出し、本発明に到達した。すなわ
ち、本発明は、板状の装置基板の一面側に搭載された半
導体チップに一端部が接続されていると共に、他端部が
外部回路と接続するためのランド部に形成された回路パ
ターンを具備し、且つ前記半導体チップ及び回路パター
ンの一端部が樹脂封止されて成る半導体装置本体に、板
状の端子基板に透設された透孔に挿通されて固着された
実装端子の端部の各々が、接点として端子基板の両面か
ら突出する実装キャリアが装着されている半導体装置で
あって、該半導体装置本体の表面に形成されたランド部
と実装キャリアに設けられた実装端子の一端部とが電気
的に接続されていることを特徴とする半導体装置にあ
る。As a result of studies to achieve the object of the present invention, as a result, a separately formed mounting terminal is erected on a semiconductor device body on which a semiconductor chip is mounted and a circuit pattern is formed. The present invention has been completed by finding that the mounting holes for fixing the mounting terminals can be eliminated in the semiconductor device main body by mounting the mounted mounting carrier. That is, according to the present invention, one end portion is connected to a semiconductor chip mounted on one surface side of a plate-shaped device substrate, and the other end portion has a circuit pattern formed on a land portion for connecting to an external circuit. In the semiconductor device main body, which is provided with the semiconductor chip and one end of the circuit pattern is resin-sealed, the end of the mounting terminal that is fixed by being inserted into the through hole that is transparently provided in the plate-shaped terminal board. Each is a semiconductor device in which mounting carriers protruding from both sides of a terminal board are mounted as contacts, and a land portion formed on the surface of the semiconductor device body and one end portion of a mounting terminal provided on the mounting carrier. Is electrically connected to a semiconductor device.
【０００７】かかる構成を有する本発明において、装置
基板の半導体チップ搭載面に形成された、回路パターン
の他端部にランド部が設けられて成る半導体装置本体、
装置基板の半導体チップ搭載面に対して反対側面に形成
された回路パターンの他端部にランド部が設けられ、且
つ半導体チップ搭載面に形成された回路パターンとラン
ド部形成面の回路パターンとがスルーホールによって電
気的に連結されて成る半導体装置本体、或いは装置基板
の半導体チップ搭載面に、内部回路パターンが形成され
た多層回路基板が装着され、且つ前記多層回路基板の露
出面に形成された回路パターンの他端部にランド部が設
けられていると共に、内部回路パターンとランド部形成
面の回路パターンとがスルーホールによって電気的に連
結されて成る半導体装置本体に適用できる。就中、装置
基板が樹脂製である半導体装置本体、或いは金属製の装
置基板に、樹脂製の多層回路基板が装着されて成る半導
体装置本体であって、実装端子としてピン状の実装端子
が固着された実装キャリアを使用することによって、ピ
ングリットアレイ型半導体装置が容易に得られる。In the present invention having such a structure, a semiconductor device main body having a land portion provided at the other end of the circuit pattern formed on the semiconductor chip mounting surface of the device substrate,
A land portion is provided at the other end of the circuit pattern formed on the side opposite to the semiconductor chip mounting surface of the device substrate, and the circuit pattern formed on the semiconductor chip mounting surface and the circuit pattern on the land portion forming surface are A multilayer circuit board having an internal circuit pattern is mounted on a semiconductor chip mounting surface of a semiconductor device body or a device substrate electrically connected by through holes, and is formed on an exposed surface of the multilayer circuit board. The present invention can be applied to a semiconductor device main body in which a land portion is provided at the other end of the circuit pattern and the internal circuit pattern and the circuit pattern on the land portion forming surface are electrically connected by a through hole. Especially, a semiconductor device body whose device board is made of resin, or a semiconductor device body in which a resin multilayer circuit board is mounted on a metal device board, and pin-shaped mounting terminals are fixed as mounting terminals. By using the mounted carrier, a pin grid array type semiconductor device can be easily obtained.
【０００８】また、本発明は、板状の装置基板の一面側
に搭載された半導体チップに一端部が接続されていると
共に、他端部が外部回路と接続するためのランド部に形
成された回路パターンを具備し、且つ前記半導体チップ
及び回路パターンの一端部が樹脂封止されて成る半導体
装置本体に装着される実装キャリアであって、該実装キ
ャリアには、実装端子の端部の各々が接点として端子基
板の両面から突出するように、前記実装端子が板状の端
子基板に透設された透孔に挿通されて固着され、且つ前
記実装キャリアが半導体装置本体の表面に形成されたラ
ンド部に装着されたとき、前記装置基板のランド部と実
装キャリアの実装端子の一端部とが電気的に接続される
ことを特徴とする半導体装置用実装キャリアでもある。
かかる構成の本発明において、実装端子としてピン状の
実装端子が固着された実装キャリアを使用することによ
って、ピングリットアレイ型半導体装置を容易に製造で
きる。Further, according to the present invention, one end is connected to the semiconductor chip mounted on the one surface side of the plate-shaped device substrate, and the other end is formed in the land for connecting to an external circuit. A mounting carrier which is equipped with a circuit pattern and which is mounted on a semiconductor device main body in which one end of the semiconductor chip and the circuit pattern is resin-sealed, wherein each end of the mounting terminal is mounted on the mounting carrier. The mounting terminal is inserted into and fixed to a through hole formed in a plate-shaped terminal board so as to project from both sides of the terminal board as a contact, and the mounting carrier is formed on the surface of the semiconductor device body. The mounting carrier for a semiconductor device is also characterized in that, when mounted on a portion, the land portion of the device substrate and one end portion of the mounting terminal of the mounting carrier are electrically connected.
In the present invention having such a configuration, by using the mounting carrier to which the pin-shaped mounting terminal is fixed as the mounting terminal, the pin grid array type semiconductor device can be easily manufactured.
【０００９】[0009]
【作用】本発明によれば、半導体装置本体に、実装端子
が設けられた実装キャリアを装着して半導体装置を形成
するとき、装置基板のランド部と実装キャリアの実装端
子の一端部とを電気的に接続することができる。このた
め、装置基部に形成された回路パターンのランド部に、
実装端子の固定に用いる大径の透孔を透設することなく
実装端子を電気的に接続することができ、ランド部の直
径を可及的に小さくできる結果、回路パターンの配設可
能範囲を広くとることができるため、配設し得る回路パ
ターンの本数を増加できる。According to the present invention, when a mounting carrier provided with mounting terminals is mounted on a semiconductor device body to form a semiconductor device, the land portion of the device substrate and one end portion of the mounting terminal of the mounting carrier are electrically connected. Can be connected to each other. Therefore, in the land portion of the circuit pattern formed on the device base,
The mounting terminals can be electrically connected without providing a large-diameter through hole used for fixing the mounting terminals, and the diameter of the land can be made as small as possible. Since it can be wide, the number of circuit patterns that can be arranged can be increased.
【００１０】[0010]
【実施例】以下、本発明の好適な実施例について添付図
面と共に詳述する。なお、本実施例では、実装端子付半
導体装置としてピングリッドアレイ型半導体装置を例に
挙げて説明する。図１は、本発明に係る実装端子付半導
体装置１０の断面図である。図１において、絶縁性を有
する合成樹脂（例えばガラスエポキシ樹脂）で板状に形
成された装置基板１２の下面に、半導体チップ１４が固
定されている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. In this embodiment, a pin grid array type semiconductor device will be described as an example of the semiconductor device with mounting terminals. FIG. 1 is a sectional view of a semiconductor device 10 with mounting terminals according to the present invention. In FIG. 1, a semiconductor chip 14 is fixed to the lower surface of a device substrate 12 formed in a plate shape with a synthetic resin having an insulating property (for example, glass epoxy resin).
【００１１】また、この装置基板１２の下面には、例え
ば銅箔等をエッチングすることにより形成された回路パ
ターン１６が、多数本形成されている。かかる回路パタ
ーン１６は、半導体チップ１４の周囲に配設されてお
り、各回路パターン１６の内端部、すなわち半導体チッ
プ１４側の回路パターン端部の各々は、ボンディングワ
イヤ１８を介して半導体チップ１４と電気的に接続され
ている。一方、各回路パターン１６の外端部は、後述す
る様に、実装端子との接点となる円形のランド部２０に
形成されている。更に、装置基板１２の下面から突設さ
れている樹脂封止部２２は、半導体チップ１４、回路パ
ターン１６の内端部等を内包している。この様に、本実
施例においては、装置基板１２、半導体チップ１４、及
び回路パターン１６等で半導体装置本体２４が構成され
る。On the lower surface of the device substrate 12, a large number of circuit patterns 16 formed by etching copper foil, for example, are formed. The circuit pattern 16 is arranged around the semiconductor chip 14, and the inner end of each circuit pattern 16, that is, each end of the circuit pattern on the side of the semiconductor chip 14 is connected to the semiconductor chip 14 via the bonding wire 18. Is electrically connected to. On the other hand, the outer end portion of each circuit pattern 16 is formed in a circular land portion 20 that serves as a contact point with a mounting terminal, as will be described later. Furthermore, the resin sealing portion 22 protruding from the lower surface of the device substrate 12 includes the semiconductor chip 14, the inner end portion of the circuit pattern 16, and the like. As described above, in this embodiment, the device substrate 12, the semiconductor chip 14, the circuit pattern 16, and the like form the semiconductor device body 24.
【００１２】かかる半導体装置本体２４には、絶縁性を
有する合成樹脂（例えばガラスエポキシ樹脂）で板状に
形成された端子基板２６が装着されている。端子基板２
６は、装置基板１２と外形が略同一形状、輪郭寸法が略
同一サイズに形成され、端子基板２６の中央には中央孔
２８が透設されている。中央孔２８は、樹脂封止部２２
が貫通可能なサイズである。また、端子基板２６には各
ランド部２０に対応して上下方向の透孔３０が多数透設
されている。かかる透孔３０の各々には、ピン状に形成
された金属製の実装端子３２が端子基板２６の上面から
下面方向へ挿通され、実装端子３２の上端部３４は、第
１の接点としてバンプ状に形成され、端子基板２６上面
から突出している。この実装端子３２の上端部３４の平
面形状は円形に形成され、その直径はランド部２０の直
径以下である。他方、実装端子３２の下端部３６は、第
２の接点として端子基板２６の下面から突出すると共
に、樹脂封止部２２の下面より下方に位置している。な
お、実装端子３２の下端部３６は、取り付けられる回路
基板（不図示）に装着可能なサイズに形成されている。
この様に、本実施例では、端子基板２６と実装端子３２
とによって実装キャリア３８が構成される。A terminal board 26, which is formed in a plate shape from a synthetic resin having an insulating property (eg, glass epoxy resin), is mounted on the semiconductor device body 24. Terminal board 2
6, the external shape and the outline size of the device substrate 12 are substantially the same, and a central hole 28 is formed at the center of the terminal substrate 26. The central hole 28 is formed by the resin sealing portion 22.
Is a size that can penetrate. Further, the terminal board 26 is provided with a large number of through holes 30 in the vertical direction corresponding to the respective land portions 20. A pin-shaped metal mounting terminal 32 is inserted into each of the through holes 30 from the upper surface to the lower surface of the terminal substrate 26, and the upper end portion 34 of the mounting terminal 32 serves as a bump-shaped contact. And is projected from the upper surface of the terminal board 26. The upper end portion 34 of the mounting terminal 32 is formed in a circular shape in plan view, and the diameter thereof is equal to or smaller than the diameter of the land portion 20. On the other hand, the lower end portion 36 of the mounting terminal 32 projects from the lower surface of the terminal substrate 26 as the second contact and is located below the lower surface of the resin sealing portion 22. The lower end portion 36 of the mounting terminal 32 is formed in a size that can be mounted on a circuit board (not shown) to be mounted.
Thus, in the present embodiment, the terminal board 26 and the mounting terminals 32 are
The mounting carrier 38 is constituted by
【００１３】本実施例においては、かかる半導体装置本
体２４を構成している装置基板１２の下面と、実装キャ
リア３８を構成している端子基板２６の上面とを対向し
て配置し、各回路パターン１６の各ランド部２０に対
し、各実装端子３２の上端部３４の各々を電気的に接続
し（図１図示の状態）、後述する適宜な手段により半導
体装置２４と実装キャリア３８とを連結することによっ
て、実装端子付半導体装置１０が完成する。この実装端
子付半導体装置１０は、実装端子３２の下端部３６を、
取り付けられる回路基板（不図示）に装着することによ
り平面実装される。In this embodiment, the lower surface of the device substrate 12 constituting the semiconductor device main body 24 and the upper surface of the terminal substrate 26 constituting the mounting carrier 38 are arranged so as to face each other, and each circuit pattern is formed. The upper ends 34 of the respective mounting terminals 32 are electrically connected to the respective 16 land portions 20 (state shown in FIG. 1), and the semiconductor device 24 and the mounting carrier 38 are connected by appropriate means described later. As a result, the semiconductor device 10 with mounting terminals is completed. In this semiconductor device 10 with mounting terminals, the lower end portion 36 of the mounting terminal 32 is
It is planarly mounted by mounting it on a circuit board (not shown) to be mounted.
【００１４】次に、図２〜図５を用いて実装端子３２の
端子基板２６に対する固定方法について説明する。図２
に示す例は、端子基板２６の透孔３０に対する金属製の
スリーブ４０を嵌着し、そのスリーブ４０に実装端子３
２を挿通してある。スリーブ４０と実装端子３２との間
は、はんだ４２によって固着されている。図２の場合、
はんだ４２によってスリーブ４０と実装端子３２を固着
するため、両者４０、３２の表面は、はんだの濡れ性が
良好となるようめっき処理が施されている。図３に示す
例は、実装端子３２の中間部分に端子基板２６の透孔３
０よりも大径の大径部４４を形成し、この大径部４４を
透孔３０内に圧入して固定した例である。Next, a method of fixing the mounting terminal 32 to the terminal board 26 will be described with reference to FIGS. Figure 2
In the example shown in FIG. 3, a metal sleeve 40 is fitted into the through hole 30 of the terminal board 26, and the mounting terminal 3 is attached to the sleeve 40.
2 is inserted. The sleeve 40 and the mounting terminal 32 are fixed by solder 42. In the case of FIG.
Since the sleeve 40 and the mounting terminal 32 are fixed to each other by the solder 42, the surfaces of the both 40 and 32 are plated so that the wettability of the solder is good. In the example shown in FIG. 3, the through hole 3 of the terminal board 26 is provided in the middle portion of the mounting terminal 32.
This is an example in which a large-diameter portion 44 having a diameter larger than 0 is formed and the large-diameter portion 44 is press-fitted and fixed in the through hole 30.
【００１５】図４に示す例は、端子基板２６の透孔３０
にスリーブ４０を嵌着し、そのスリーブ４０に円柱状の
実装端子３２を挿通している。実装端子３２の上端はス
リーブ４０内に在る。第１の接点は、スリーブ４０の上
端面と実装端子３２の上端面とを連結するためのはんだ
４２ａがバンプ状に形成され兼任している。なお、スリ
ーブ４０と実装端子３２との連結をより確実にするた
め、スリーブ４０の下端面と実装端子３２の中間部分を
はんだ４２ｂで固着している。この例でもスリーブ４０
と実装端子３２は、はんだの濡れ性が良好となるようめ
っき処理が施されている。図５に示す例は、実装端子３
２がピン状に形成されておらず、実装端子３２の第１の
接点である上端部３４と第２の接点である下端部３６
は、端子基板２６の上面と下面からバンプ状に突設され
ている。この実装端子３２は、銅めっき処理が施されて
おり、更に実装端子３２の外表面は、はんだ４２ａ、４
２ｂによって被覆されている。In the example shown in FIG. 4, the through hole 30 of the terminal board 26 is provided.
The sleeve 40 is fitted into the sleeve 40, and the cylindrical mounting terminal 32 is inserted into the sleeve 40. The upper end of the mounting terminal 32 is in the sleeve 40. A solder 42a for connecting the upper end surface of the sleeve 40 and the upper end surface of the mounting terminal 32 is formed in a bump shape to serve also as the first contact. In order to secure the connection between the sleeve 40 and the mounting terminal 32, the lower end surface of the sleeve 40 and the intermediate portion of the mounting terminal 32 are fixed with solder 42b. Also in this example, the sleeve 40
The mounting terminal 32 is plated so that the solder wettability is good. The example shown in FIG.
2 is not formed in a pin shape, and the mounting terminal 32 has a first contact point as an upper end portion 34 and a second contact point as a lower end portion 36.
Are provided in a bump shape from the upper surface and the lower surface of the terminal board 26. The mounting terminal 32 is copper-plated, and the outer surface of the mounting terminal 32 has solder 42 a, 4
It is covered by 2b.
【００１６】かかる半導体装置２４と実装キャリア３８
との連結方法について、図６〜図８を使用して説明す
る。図６に示す例は、実装端子３２の上端部３４と装置
基板１２のランド部２０をはんだ４２で接続することに
より半導体装置２４と実装キャリア３８を電気的に接続
するものである。また、図７に示す例は、実装端子３２
の上端部３４と装置基板１２のランド部２０とを機械的
に接触させ、電気的に両者３４、２０を接続し、且つ装
置基板１２と端子基板２６とを接着剤４４で連結した例
である。The semiconductor device 24 and the mounting carrier 38
A method of connecting with and will be described with reference to FIGS. In the example shown in FIG. 6, the semiconductor device 24 and the mounting carrier 38 are electrically connected by connecting the upper end 34 of the mounting terminal 32 and the land 20 of the device substrate 12 with solder 42. In addition, the example shown in FIG.
Is an example in which the upper end 34 of the device and the land 20 of the device substrate 12 are mechanically contacted to electrically connect the two 34, 20 and the device substrate 12 and the terminal substrate 26 are connected by an adhesive 44. .
【００１７】更に、図８に示す例は、装置基板１２と端
子基板２６との間に異方導電性フィルム４６を介在さ
せ、実装端子３２の上端部３４と装置基板１２のランド
部２０とを圧着させることによって、実装端子３４とラ
ンド部２０との電気的接続を図ると同時に装置基板１２
と端子基板２６との連結を行うものである。Further, in the example shown in FIG. 8, an anisotropic conductive film 46 is interposed between the device substrate 12 and the terminal substrate 26, and the upper end portion 34 of the mounting terminal 32 and the land portion 20 of the device substrate 12 are connected to each other. By crimping, electrical connection between the mounting terminal 34 and the land portion 20 is achieved, and at the same time, the device substrate 12
And the terminal board 26 are connected.
【００１８】実装端子３２の端子基板２６に対する固定
方法について、更に別の例を図９及び図１０を使用して
説明する。図９に示す例は、図２に示す例の変形例であ
る。端子基板２６の透孔３０内壁面及び開口部周縁部に
は、金属めっき（例えば銅）が施され、めっき層５０が
形成されている。かかる透孔３０に挿通された実装端子
３２は、はんだ４２を介して固着されている。なお、図
９の場合も、はんだ４２で実装端子３２を固着するた
め、実装端子３２の表面は、はんだの濡れ性が良好とな
るようめっき処理が施されている。Another method for fixing the mounting terminal 32 to the terminal board 26 will be described with reference to FIGS. 9 and 10. The example shown in FIG. 9 is a modification of the example shown in FIG. Metal plating (for example, copper) is applied to the inner wall surface of the through hole 30 and the peripheral edge of the opening of the terminal board 26 to form a plating layer 50. The mounting terminal 32 inserted into the through hole 30 is fixed via the solder 42. In the case of FIG. 9 as well, since the mounting terminals 32 are fixed by the solder 42, the surfaces of the mounting terminals 32 are plated so that the solder wettability is good.
【００１９】また、図１０に示す例は、図４に示す例の
変形例である。図９の例と同様、端子基板２６の透孔３
０内壁面及び開口部周縁部には金属めっき（例えば銅）
が施され、めっき層５０が形成されている。かかる透孔
３０に挿通された円柱状の実装端子３２は上端が透孔３
０内に在るため、はんだ４２ａによってバンプ状に形成
された第１の接点が、めっき層５０の上端面と実装端子
３２の上端面とを連結する。なお、めっき層５０と実装
端子３２との連結をより確実にするため、めっき層５０
の下端面と実装端子３２の中間部分をはんだ４２ｂで固
着している。この例でも実装端子３２は、はんだの濡れ
性が良好となるようめっき処理が施されている。The example shown in FIG. 10 is a modification of the example shown in FIG. Similar to the example of FIG. 9, the through holes 3 of the terminal board 26
Metal plating (for example, copper) on the inner wall surface and the periphery of the opening
And the plated layer 50 is formed. The cylindrical mounting terminal 32 inserted into the through hole 30 has the through hole 3 at the upper end.
Since it is in 0, the first contact formed in a bump shape by the solder 42a connects the upper end surface of the plating layer 50 and the upper end surface of the mounting terminal 32. In order to secure the connection between the plating layer 50 and the mounting terminal 32, the plating layer 50
The lower end surface of the and the intermediate portion of the mounting terminal 32 are fixed by solder 42b. Also in this example, the mounting terminal 32 is plated so that the solder wettability is good.
【００２０】これまで述べてきた半導体装置１０は、半
導体装置本体２４が、装置基板１２の半導体チップ搭載
面に、回路パターン１６を形成するランド部２０が形成
されているものであるが、昨今の回路パターンの高密度
化の要請に応えるためには、図１１又は図１２に示す半
導体装置１０が好ましい。図１１に示す半導体装置１０
は、その半導体装置本体２４が、装置基板１２の半導体
チップ搭載面に対して反対側面に形成された回路パター
ン１６ｂの端部にランド部２０が設けられ、且つ半導体
チップ搭載面に形成された回路パターン１６ａとランド
部形成面の回路パターン１６ｂとがスルーホール１５に
よって電気的に連結されているものである。かかる半導
体装置本体２４のスルーホール１５は、装置基板１２に
透設された小孔にスルーホールめっきを施すことによっ
て得ることができる。このスルーホール１５は、回路パ
ターン１６ａと回路パターン１６ｂとを連結するもので
あるため、従来の半導体装置において実装端子１１０を
固定する透孔１１２（図１３）に比較して、著しく小径
とすることができる。このため、ランド部２０の中心部
にスルーホール１５を配設しても、回路パターン１６の
高密度化を妨げるほどランド部２０の直径を拡大させる
ことがない。また、装置基板１２の半導体チップ搭載面
に対して反対面の全面にランド部２０を形成できるた
め、半導体装置の多ピン化の要請にも応えることができ
る。この様な、図１１に示す半導体装置本体２４のラン
ド部２０の各々に対し、実装キャリア３８の実装端子３
２の実装端子上端部３４の固定方法は、先に述べた固定
方法と同様の方法を採用できる。In the semiconductor device 10 described above, the semiconductor device main body 24 has the land portion 20 for forming the circuit pattern 16 formed on the semiconductor chip mounting surface of the device substrate 12, but these days. In order to meet the demand for higher density circuit patterns, the semiconductor device 10 shown in FIG. 11 or 12 is preferable. Semiconductor device 10 shown in FIG.
In the semiconductor device body 24, the land portion 20 is provided at the end of the circuit pattern 16b formed on the side opposite to the semiconductor chip mounting surface of the device substrate 12, and the circuit formed on the semiconductor chip mounting surface. The pattern 16a and the circuit pattern 16b on the land portion forming surface are electrically connected by the through hole 15. The through hole 15 of the semiconductor device main body 24 can be obtained by performing through hole plating on the small hole provided through the device substrate 12. Since the through hole 15 connects the circuit pattern 16a and the circuit pattern 16b, the through hole 15 should be remarkably smaller in diameter than the through hole 112 (FIG. 13) for fixing the mounting terminal 110 in the conventional semiconductor device. You can Therefore, even if the through hole 15 is provided in the central portion of the land portion 20, the diameter of the land portion 20 is not enlarged so much as to prevent the circuit pattern 16 from being highly densified. Further, since the land portion 20 can be formed on the entire surface of the device substrate 12 opposite to the semiconductor chip mounting surface, it is possible to meet the demand for increasing the number of pins of the semiconductor device. The mounting terminal 3 of the mounting carrier 38 is attached to each of the lands 20 of the semiconductor device main body 24 shown in FIG.
The second mounting terminal upper end portion 34 can be fixed by the same method as the above-described fixing method.
【００２１】また、図１２に示す半導体装置は、その半
導体装置本体２４が、銅又はアルミ等の金属から成る装
置基板１７の半導体チップ搭載面に、内部回路パターン
１６ｃが形成された樹脂製の多層回路基板２５が装着さ
れ、且つ多層回路基板２５の露出面に形成された回路パ
ターン１６ｂの他端部にランド部２０が設けられている
と共に、内部回路パターン１６ｃとランド部形成面の回
路パターン１６ｂとがスルーホール１５によって電気的
に連結されているものである。かかる半導体装置本体２
４のスルーホール１５は、多層回路基板２５に透設され
た小孔にスルーホールめっきを施すことによって得るこ
とができる。このスルーホール１５は、内部回路パター
ン１６ｃと回路パターン１６ｂとを連結するものである
ため、従来の半導体装置において実装端子１１０を固定
する透孔１１２（図１３）に比較して、著しく小径とす
ることができる。このため、ランド部２０の中心部にス
ルーホール１５を配設しても、回路パターン１６の高密
度化を妨げるほどランド部２０の直径を拡大させること
がない。なお、図１２に示す半導体装置本体２４のラン
ド部２０の各々に対し、実装キャリア３８の実装端子３
２の実装端子上端部３４の固定方法は、先に述べた固定
方法と同様の方法を採用できる。In the semiconductor device shown in FIG. 12, the semiconductor device main body 24 has a resin multilayer structure in which the internal circuit pattern 16c is formed on the semiconductor chip mounting surface of the device substrate 17 made of metal such as copper or aluminum. The circuit board 25 is mounted, and the land portion 20 is provided at the other end of the circuit pattern 16b formed on the exposed surface of the multilayer circuit board 25, and the internal circuit pattern 16c and the circuit pattern 16b on the land portion forming surface are formed. And are electrically connected by a through hole 15. Such a semiconductor device body 2
The through holes 15 of No. 4 can be obtained by performing through hole plating on the small holes formed through the multilayer circuit board 25. Since the through hole 15 connects the internal circuit pattern 16c and the circuit pattern 16b, it has a remarkably smaller diameter than the through hole 112 (FIG. 13) for fixing the mounting terminal 110 in the conventional semiconductor device. be able to. Therefore, even if the through hole 15 is provided in the central portion of the land portion 20, the diameter of the land portion 20 is not enlarged so much as to prevent the circuit pattern 16 from being highly densified. The mounting terminal 3 of the mounting carrier 38 is attached to each of the lands 20 of the semiconductor device body 24 shown in FIG.
The second mounting terminal upper end portion 34 can be fixed by the same method as the above-mentioned fixing method.
【００２２】[0022]
【発明の効果】本発明に係る半導体装置では、装置基板
の一方の面と、実装キャリアの端子基板の一方の面とを
対向して配置し、各回路パターンの各ランド部に対し、
各実装端子を電気的に接続すると、回路パターンのラン
ド部に実装端子の固定用に使用される大径の透孔を設け
てなくても各ランド部と各実装端子を電気的に接続可能
となる。従って、ランド部に実装端子固定用の透孔を透
設する必要がないため、ランド部の大きさを可及的に小
さくでき、ランド部同士の間に形成可能な回路パターン
を増加することができる結果、回路パターンの高密度化
を図ることができる。In the semiconductor device according to the present invention, one surface of the device substrate and one surface of the terminal board of the mounting carrier are arranged so as to face each other, and each land portion of each circuit pattern is
When each mounting terminal is electrically connected, each land can be electrically connected to each mounting terminal without providing a large-diameter through hole used for fixing the mounting terminal in the land of the circuit pattern. Become. Therefore, since it is not necessary to form through holes for mounting terminals in the lands, it is possible to reduce the size of the lands as much as possible and increase the number of circuit patterns that can be formed between the lands. As a result, it is possible to increase the density of the circuit pattern.
【図１】本発明に係る一実施例を示す半導体装置の断面
図である。FIG. 1 is a sectional view of a semiconductor device showing an embodiment according to the present invention.
【図２】実装端子の実装基板に対する固定方法について
説明するための部分断面図である。FIG. 2 is a partial cross-sectional view for explaining a method of fixing a mounting terminal to a mounting board.
【図３】実装端子の実装基板に対する固定方法について
の他の例を説明するための部分断面図である。FIG. 3 is a partial cross-sectional view for explaining another example of the method of fixing the mounting terminal to the mounting board.
【図４】実装端子の実装基板に対する固定方法について
の他の例を説明するための部分断面図である。FIG. 4 is a partial cross-sectional view for explaining another example of a method of fixing a mounting terminal to a mounting board.
【図５】実装端子の実装基板に対する固定方法について
の他の例を説明するための部分断面図である。FIG. 5 is a partial cross-sectional view for explaining another example of the method of fixing the mounting terminal to the mounting board.
【図６】半導体装置と実装キャリアとの連結方法につい
て説明するための部分断面図である。FIG. 6 is a partial cross-sectional view for explaining a method of connecting a semiconductor device and a mounting carrier.
【図７】半導体装置と実装キャリアとの連結方法につい
ての他の例を説明するための部分断面図である。FIG. 7 is a partial cross-sectional view for explaining another example of the method of connecting the semiconductor device and the mounting carrier.
【図８】半導体装置と実装キャリアとの連結方法につい
ての他の例を説明するための部分断面図である。FIG. 8 is a partial cross-sectional view for explaining another example of the method of connecting the semiconductor device and the mounting carrier.
【図９】実装端子の実装基板との固定方法についての他
の例を説明するための部分断面図である。FIG. 9 is a partial cross-sectional view for explaining another example of the method of fixing the mounting terminal to the mounting board.
【図１０】実装端子の実装基板との固定方法についての
他の例を説明するための部分断面図である。FIG. 10 is a partial cross-sectional view for explaining another example of the method of fixing the mounting terminal to the mounting board.
【図１１】本発明に係る他の実施例を示す半導体装置の
断面図である。FIG. 11 is a sectional view of a semiconductor device showing another embodiment of the present invention.
【図１２】本発明に係る他の実施例を示す半導体装置の
断面図である。FIG. 12 is a sectional view of a semiconductor device showing another embodiment of the present invention.
【図１３】従来の半導体装置を示した断面図である。FIG. 13 is a sectional view showing a conventional semiconductor device.
【図１４】従来の半導体装置における回路パターンとラ
ンド部との関係について説明するための部分底面図であ
る。FIG. 14 is a partial bottom view for explaining the relationship between the circuit pattern and the land portion in the conventional semiconductor device.
１０ 実装端子付半導体装置 １２ 装置基板 １４ 半導体チップ １６ 回路パターン ２０ ランド部 ２４ 半導体装置本体 ２６ 端子基板 ３０ 透孔 ３２ 実装端子 ３４ 実装端子上端部 ３６ 実装端子下端部 ３８ 実装キャリア 10 Semiconductor Device with Mounting Terminal 12 Device Board 14 Semiconductor Chip 16 Circuit Pattern 20 Land Part 24 Semiconductor Device Main Body 26 Terminal Board 30 Through Hole 32 Mounting Terminal 34 Mounting Terminal Upper End 36 Mounting Terminal Lower End 38 Mounting Carrier
───────────────────────────────────────────────────── フロントページの続き (72)発明者 宮坂 俊次 長野県長野市大字栗田字舎利田711番地 新光電気工業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shunji Miyasaka 711, Rita, Kurita, Nagano City, Nagano Shinko Electric Industry Co., Ltd.
Claims (9)
導体チップに一端部が接続されていると共に、他端部が
外部回路と接続するためのランド部に形成された回路パ
ターンを具備し、且つ前記半導体チップ及び回路パター
ンの一端部が樹脂封止されて成る半導体装置本体に、 板状の端子基板に透設された透孔に挿通されて固着され
た実装端子の端部の各々が、接点として端子基板の両面
から突出する実装キャリアが装着されている半導体装置
であって、 該半導体装置本体の表面に形成されたランド部と実装キ
ャリアに設けられた実装端子の一端部とが電気的に接続
されていることを特徴とする半導体装置。1. A circuit pattern having one end connected to a semiconductor chip mounted on one surface of a plate-shaped device substrate and the other end formed on a land for connecting to an external circuit. Further, each of the end portions of the mounting terminals inserted into and fixed to the through holes formed in the plate-shaped terminal board in the semiconductor device body formed by resin-sealing one end portions of the semiconductor chip and the circuit pattern. Is a semiconductor device in which mounting carriers protruding from both sides of a terminal board are mounted as contacts, and a land portion formed on the surface of the semiconductor device body and one end portion of a mounting terminal provided on the mounting carrier are A semiconductor device, which is electrically connected.
ップ搭載面に形成された、回路パターンの他端部にラン
ド部が設けられて成る請求項１記載の半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor device main body is provided with a land portion on the other end of the circuit pattern formed on the semiconductor chip mounting surface of the device substrate.
ップ搭載面に対して反対側面に形成された回路パターン
の他端部にランド部が設けられ、且つ半導体チップ搭載
面に形成された回路パターンとランド部形成面の回路パ
ターンとがスルーホールによって電気的に連結されて成
る請求項１記載の半導体装置。3. A circuit pattern formed on a semiconductor chip mounting surface of a semiconductor device main body, wherein a land portion is provided at the other end of a circuit pattern formed on a side surface of the device substrate opposite to the semiconductor chip mounting surface. 2. The semiconductor device according to claim 1, wherein the circuit pattern on the land forming surface is electrically connected by a through hole.
ップ搭載面に、内部回路パターンが形成された多層回路
基板が装着され、且つ前記多層回路基板の表面に形成さ
れた回路パターンの他端部にランド部が設けられている
と共に、内部回路パターンとランド部形成面の回路パタ
ーンとがスルーホールによって電気的に連結されて成る
請求項１記載の半導体装置。4. A semiconductor device main body, wherein a multi-layer circuit board having an internal circuit pattern formed thereon is mounted on a semiconductor chip mounting surface of a device substrate, and the other end of the circuit pattern formed on the surface of the multi-layer circuit board. 2. The semiconductor device according to claim 1, wherein the land portion is provided on the inner surface, and the internal circuit pattern and the circuit pattern on the land portion forming surface are electrically connected by a through hole.
脂製である請求項１〜３のいずれか一項記載の半導体装
置。5. The semiconductor device according to claim 1, wherein the device substrate forming the semiconductor device main body is made of resin.
に、樹脂製の多層回路基板が装着されて成る請求項４記
載の半導体装置。6. The semiconductor device according to claim 4, wherein the semiconductor device main body is formed by mounting a resin multilayer circuit board on a metal device board.
するピングリットアレイ型半導体装置である請求項１〜
６のいずれか一項記載の半導体装置。7. The semiconductor device is a pingrit array type semiconductor device using a pin-shaped mounting terminal.
7. The semiconductor device according to claim 6.
導体チップに一端部が接続されていると共に、他端部が
外部回路と接続するためのランド部に形成された回路パ
ターンを具備し、且つ前記半導体チップ及び回路パター
ンの一端部が樹脂封止されて成る半導体装置本体に装着
される実装キャリアであって、 該実装キャリアには、実装端子の端部の各々が接点とし
て端子基板の両面から突出するように、前記実装端子が
板状の端子基板に透設された透孔に挿通されて固着さ
れ、 且つ前記実装キャリアが半導体装置本体の表面に形成さ
れたランド部に装着されたとき、前記装置基板のランド
部と実装キャリアの実装端子の一端部とが電気的に接続
されることを特徴とする半導体装置用実装キャリア。8. A circuit pattern having one end connected to a semiconductor chip mounted on one surface of a plate-shaped device substrate and the other end formed on a land for connecting to an external circuit. A mounting carrier to be mounted on a semiconductor device main body in which one ends of the semiconductor chip and the circuit pattern are resin-sealed, wherein each of the mounting terminal ends serves as a terminal board. The mounting terminals are inserted into and fixed to the through holes formed through the plate-shaped terminal board so as to project from both sides of the mounting terminal, and the mounting carrier is mounted on the land portion formed on the surface of the semiconductor device body. In this case, the mounting carrier for a semiconductor device is characterized in that the land portion of the device substrate and one end portion of the mounting terminal of the mounting carrier are electrically connected.
項８記載の半導体装置用実装キャリア。9. The mounting carrier for a semiconductor device according to claim 8, wherein the mounting terminal is a pin-shaped mounting terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6074697A JPH07169876A (en) | 1993-04-13 | 1994-04-13 | Semiconductor device and mounting carrier thereof |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8609693 | 1993-04-13 | ||
| JP5-227715 | 1993-09-14 | ||
| JP22771593 | 1993-09-14 | ||
| JP5-86096 | 1993-09-14 | ||
| JP6074697A JPH07169876A (en) | 1993-04-13 | 1994-04-13 | Semiconductor device and mounting carrier thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07169876A true JPH07169876A (en) | 1995-07-04 |
Family
ID=27301586
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6074697A Pending JPH07169876A (en) | 1993-04-13 | 1994-04-13 | Semiconductor device and mounting carrier thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07169876A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277525A (en) * | 2007-04-27 | 2008-11-13 | Shinko Electric Ind Co Ltd | Substrate with pin as well as wiring substrate and semiconductor device |
| JP2008277526A (en) * | 2007-04-27 | 2008-11-13 | Shinko Electric Ind Co Ltd | Substrate with pin, manufacturing method therefor, and semiconductor product |
-
1994
- 1994-04-13 JP JP6074697A patent/JPH07169876A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008277525A (en) * | 2007-04-27 | 2008-11-13 | Shinko Electric Ind Co Ltd | Substrate with pin as well as wiring substrate and semiconductor device |
| JP2008277526A (en) * | 2007-04-27 | 2008-11-13 | Shinko Electric Ind Co Ltd | Substrate with pin, manufacturing method therefor, and semiconductor product |
| US8188589B2 (en) | 2007-04-27 | 2012-05-29 | Shinko Electric Industries Co., Ltd. | Substrate with pin, manufacturing method thereof, and semiconductor product |
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