JPH07146825A - Memory system - Google Patents

Abstract

PURPOSE:To provide a memory system capable of increasing operating speed when no error exists in data. CONSTITUTION:This system is constituted in such a way that an error detection circuit 6 which detects the error by using effective data D31-DO and redundant bits C11-C8 required for the detection of the error in the redundant bits C11-CO, an acknowledge control circuit 17 which sends out an acknowledge signal to a CPU 5 corresponding to the presence/absence of the error in the data D31-DO detected by the error detection circuit 6, and a selector 8 which outputs data to the CPU 5 corresponding to the presence/absence of the error in the data D31-DO detected by the error detection circuit 6, and when no error is detected in the effective data, the effective data is selected as it is, and speeding up can be attained by outputting the data to the CPU 5 at an ordinary operating timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system, and more particularly to a memory system for reducing error detection time.

[0002]

2. Description of the Related Art In a memory system connected to a CPU, an ECC is used to ensure the reliability of the data.
An error detection and correction circuit (hereinafter referred to as "ECC circuit") using (Error Correcting Code, error correction code) is mounted to perform data error detection and correction.

FIG. 3 is a block diagram showing an example of the configuration of a conventional ECC circuit, and FIG. 4 shows the bit configuration of the memory 1 shown in FIG.

Reference numeral 1 is a memory, 5 is a CPU, and the memory 1
A syndrome generation circuit 2, a data correction circuit 3, a 2-bit error detection circuit 4, and an acknowledge control circuit 7 which form an ECC circuit are provided between the CPU and the CPU 5.

The operation of the ECC circuit will be described below with reference to this drawing.

From the 32-bit data D31 to D0 output from the memory 1 and the 8-bit redundant bits C7 to C0, the syndrome generating circuit 2 generates the syndromes S7 to S0 according to the generating equation of the following equation 1.

[0007]

[Equation 1] Here, the syndromes S7 to S0 are the data D31 to D
When 0 has an error, it indicates information of where in the data D31 to D0 the error occurred.

The data correction circuit 3 uses the data D31 to D3.
0 and the above-mentioned syndromes S7 to S0, the following formula 2
CPU generates the data D31a to D0a according to the generation formula of
Output to 5.

At this time, the data D31a to D0a become corrected data when a 1-bit error occurs in the data D31 to D0.

[0010]

[Equation 2] At the same time, the 2-bit error detection circuit 4 checks the syndromes S7 to S0, and as a result, the data D31 to D0 are detected.
When a 2-bit error is detected in the data D31, a 2-bit error detection signal is sent to the CPU 5 to output the data D31.
a-D0a informs that it is invalid.

The acknowledge control circuit 7 considers the time when the syndrome generation circuit 2 generates the syndromes S7 to S0 and the time when the data correction circuit 3 generates the data D31a to D0a, and acknowledges it at a preset delay time. The signal is sent to the CPU 5.

In this way, when a 1-bit error occurs, it is corrected, and when a 2-bit error occurs, it is processed as an error.

[0013]

[Problems to be Solved by the Invention] However, the conventional ECC
In the case of a circuit, since the logic for detecting an error and the logic for correcting an error are the same, the operation speed of the memory system depends on the delay time of the ECC circuit regardless of the presence or absence of an error.

Therefore, it is difficult to increase the speed of the memory system due to the delay time of the ECC circuit.

The present invention has been made to solve the above problems, and an object thereof is to make a data error in response to a demand for speeding up of a memory system accompanying the speeding up of numerical control devices in recent years. An object of the present invention is to provide a memory system that can reduce the operation speed when there is no such problem.

[0016]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and a memory system for detecting an error and correcting an error by adding a plurality of redundant bits to effective data. In, in the case where an error is detected in the data by the error detecting means for detecting an error by using the data and at least one redundant bit necessary for detecting an error in the redundant bit, A data correction means for correcting the data by using a bit necessary to correct an error among the data and the redundant bit; and an acknowledge to the CPU according to the presence or absence of an error in the data detected by the error detection means. The means for changing the timing of transmitting a signal and the data detected by the error detection means And having a data selection means for selecting data to be output to the CPU, and in response to the presence or absence of errors reported.

[0017]

According to the memory system of the present invention having the above configuration, when the error detecting means detects an error in the valid data, the data correcting means corrects the valid data. The data correction means selects the corrected data and outputs it to the CPU. At this time, the means for changing the timing delays the timing for the time required for the data correction and sends an acknowledge signal to the CPU.

When the error detecting means does not detect an error in the valid data, the data selecting means selects the valid data as it is and outputs it to the CPU. At this time, the means for changing the timing sends an acknowledge signal to the CPU at normal operation timing.

As described above, according to the present invention, when an error is not detected in valid data, it is not necessary to delay the transmission timing of the acknowledge signal from the means for changing the timing, so that the speed can be increased. .

[0020]

FIG. 1 shows an embodiment of the present invention.
FIG. 2 shows the bit configuration of the memory in the embodiment. Embodiments will be described below with reference to this drawing. The same elements as those in the conventional example are designated by the same reference numerals.

In FIG. 1, 6 is valid data D31 to D31.
This is an error detection circuit which is an error detection means for detecting an error by using D0 and redundant bits C11 to C8 necessary for detecting an error among the redundant bits C11 to C0. 1
7 is data D31 to D31 detected by the error detection circuit 6.
This is an acknowledge control circuit that changes the timing of sending an acknowledge signal to the CPU 5 depending on the presence or absence of an error in D0. Reference numeral 8 is a selector which is a data selection means for selecting data to be output to the CPU 5 according to the presence / absence of an error in the data D31 to D0 detected by the error detection circuit 6.

Further, D31 to D0 in FIG. 2 represent valid data, and C11 to C0 represent the valid data D31.
Redundant bits for error detection or error correction of D0. In addition, C11 to C8 of the redundant bits
Is used for error detection, and C7 to C0 are used for error correction.

First, the operation when there is no error in the data will be described. The description of the same operation as the conventional example is omitted.

In the error detection circuit 6, the data D31
~ D0 and redundant bits C11 to C8 are checked for the presence or absence of an error by the logical calculation shown in the following Expression 3.

[0025]

[Equation 3] When there is no error in the data D31 to D0, the error detection circuit 6 sends the error detection signal in the error undetected state.

When no error is detected, the selector 8 converts the data D31 to D0 output from the memory 1 into the data D.
31b to D0b are output to the CPU 5 as they are. This is because inside the selector 8, the signal lines of the data D31 to D0 and the data D31b are changed by the switching operation.
This is performed by connecting signal lines to D0b.

When the error detection signal is in the error undetected state, the acknowledge control circuit 17 outputs an acknowledge signal to the CPU 5 at the timing of normal operation.

As described above, when there is no error in the data, it is not necessary to use the outputs from the syndrome generation circuit 2 and the data correction circuit 3, so that a memory system that does not depend on the delay time can be constructed.

Next, the operation when there is an error in the data will be described.

Data D31 to D output from the memory 1
When 0, C11 to C8, the error detection circuit 6 detects an error as a result of the logical calculation by the equation 3, the error detection signal is sent to the selector 8 and the acknowledge control circuit 17 in the error detection state. When the error detection signal enters the error detection state, the selector 8 outputs the data D31a to D0a output from the data correction circuit 3 to the CPU 5 as D31b to D0b.

This is done by connecting the signal lines of the data D31a-D0a and the data D31b-D0b inside the selector 8 by the switching operation.

When the error detection signal is in the error detection state, the acknowledge control circuit 17 detects the time required for the syndrome generation circuit 2 to generate the syndromes S7 to S0, and the data correction circuit 3 sets the data D31a to D0a.
In consideration of the time required to generate, the output of the preset delay time acknowledge signal is delayed.

Here, the time required for the error detection circuit 6 to detect an error is the time required for the syndrome generation circuit 2 to generate the syndromes S7 to S0 and the time required for the data correction circuit 3 to be D31a to D0a. It is clear from the number of formulas as well as the number of data bits that it is shorter than the time required to generate. Therefore, if there is an error in the data, the delay time will be the same as the conventional one.

As described above, when there is an error in the data D31 to D0, the data is corrected.

The equation 1 used in the above embodiment shows an example of the syndrome generation formula, and the present invention is not limited to the syndrome generation formula. Similarly in Formula 3, an example of the error detection formula is shown, and the present invention is not limited to the error detection formula. It is also clear that the bit configuration of the memory 1 does not limit the scope of the present invention.

[0036]

According to the present invention, since error detection and error correction can be performed by separate logics, error detection can be performed with a simpler logic, and at the same time, by controlling the timing of sending an acknowledge, an error can be detected in data. If not present, the operation of the memory system depends on the delay time of the error detecting means having a short delay time, and when the memory system is constructed, the speedup is facilitated.

If the data has an error, the data is corrected, so that the reliability of the memory system is ensured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory system according to the present invention.

FIG. 2 is a diagram showing a bit configuration of a memory according to an embodiment of the present invention.

FIG. 3 is a block diagram of an error detection / correction circuit in the related art.

FIG. 4 is a diagram showing a bit configuration of a memory according to a conventional technique.

[Explanation of symbols]

 1 memory 2 syndrome generation circuit 3 data correction circuit 4 2-bit error detection circuit 5 CPU 6 error detection circuit 7, 17 acknowledge control circuit 8 selector

Claims (1)

[Claims] 1. A memory system for detecting an error and correcting an error by adding a plurality of redundant bits to valid data, wherein at least one bit of redundancy is required for detecting an error of the data and the redundant bit. Error detection means for detecting an error using a bit, and when an error is detected in the data by the error detection means, the data and the redundant bit are used to correct the error. Data correcting means for correcting the data, means for changing the timing of sending an acknowledge signal to the CPU according to the presence or absence of an error in the data detected by the error detecting means, and the data detected by the error detecting means. Data selection to select the data to output to the CPU depending on the presence or absence of an error in Memory system, comprising: the stage, a.