JPH07131496A - Amplitude phase modulator - Google Patents

Abstract

PURPOSE:To decrease the amount of data on a simulation result and to reduce the capacity of a memory by selecting and outputting one of plural signals which are equal in frequency and different in phase or amplitude corresponding to respective signals in a signal train. CONSTITUTION:This modulator has a signal regenerating device 21 which previously stores plural signal trains representing a 1st locus on a phase plane and selects and outputs one of the signal trains corresponding to an inputted modulated signal and a phase transformation device 22 which converts the signal train outputted by the signal regenerating device 21 into a signal train representing a 2nd locus on the phase plane corresponding to a specific phase control signal. Further, the modulator is equipped with a selector 23 which selects and outputs one of plural signals that are equal in frequency and different in phase or amplitude corresponding to the respective signals in the signal train transformed by the phase transformation device 22. Then the necessary signal train can be generated by rotation on the phase plane and transformation into a signal which is symmetrical with one axis, so the amount of data which should be stored can be decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude / phase modulator, and more particularly to an amplitude / phase modulator suitable for a transmitter for transmitting digital signals.

[0002]

2. Description of the Related Art Although mobile phones are becoming popular,
In such a wireless device, downsizing and low power consumption are very important factors. Under such circumstances, there is a demand for downsizing and low power consumption of the modulation / demodulation circuit.

FIG. 14 is a block diagram showing the structure of a conventional analog quadrature modulator.

The quadrature modulator shown in FIG. 1 removes sampling noise contained in the outputs of the D / A converters 1 and 2 and the respective D / A converters, which convert the modulation signals given by two digital series into analog modulation signals. Low-pass filters 3 and 4, and a synthesizer 5 that generates a local signal
, A π / 2 phase shifter 6 that shifts the frequency of the local signal output from the synthesizer 5 by π / 2, and a low-pass filter 3
Mixer 7 for amplitude-modulating the output of π / 2 phase shifter 6 with the output of
, A mixer 8 that amplitude-modulates the output of the synthesizer 5 with the output of the low-pass filter 4, and the output of each mixer is combined,
Basically, it is composed of a combiner 9 that outputs an amplitude-phase modulated wave. An amplitude modulator can be used for the mixers 7 and 8.

Since this type of quadrature modulator processes analog signals after the D / A converters 1 and 2, various errors and distortions are generated. Normally, a sufficiently large bias current is required for a signal to reduce distortion, which causes a problem of large current consumption. This problem is also common when the mixer is used as an amplitude modulator. Further, in the quadrature modulator, in order to perform highly accurate modulation, correction means such as a correction circuit and a correction signal generation circuit are required for error correction.
There is a problem that the circuit scale becomes large.

On the other hand, as a high-accuracy digital quadrature modulator, a method of digitally constructing a signal has been proposed, as seen in the proceedings B-239 of the 1991 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers. This system requires high-speed processing of multi-bit digital signals in order to improve accuracy, requires a large circuit scale, and consumes a large amount of power, and is not suitable for portable wireless terminals and the like.

Therefore, the present inventor has proposed an amplitude-phase modulator which has low power consumption and a small number of adjustment points by applying delta-sigma modulation (Japanese Patent Application No. 5-20072).

FIG. 15 is a block diagram showing the structure of the amplitude / phase modulator.

As shown in the figure, the modulated signals I and Q are
By the vector delta-sigma modulator 10, a, b, c,
It is converted into a signal string represented by the four symbols of d and is input to the selector 11 as a selection signal.

A reference signal having a frequency four times as high as the desired output frequency is also input to the selector 11, and the frequency dividing circuit of the selector 11 generates four signals each having a phase difference of 90 °.

For example, when the selection signal a is input to the selector 11, the selector 11 outputs cosωt. Similarly,
When the selection signals b, c, d are input to the selector 11, the selector 11 outputs sin ωt, −cos ωt, −sin ωt.

The vector delta-sigma modulator 10 operates with a clock having a frequency sufficiently higher than the frequencies of the modulation signals I and Q, and the output of the selector 11 is cos ωt,
The signals sin ωt, −cos ωt, and −sin ωt are
Each has a square pulse envelope.

This modulator uses cosω as in the pulse density modulation method in which the amplitude is controlled by the density of square pulses.
The amplitude and phase at a desired frequency are modulated by the mixing ratio of pulses of each phase of t, sin ωt, −cos ωt, and −sin ωt. FIG. 16 is a block diagram showing the configuration of the vector delta sigma modulator 10 shown in FIG.

The encoder 12 shown in the figure has a when the coordinates represented by the two scalar inputs x and y are in the first quadrant on the coordinate plane shown in FIG. 17, and is a second quadrant. b, c in the third quadrant, and d in the fourth quadrant.

The output of the encoder 12 is output as an output signal (selection signal) of the vector delta-sigma modulation 10 while being input to the vector regenerator 13. The vector regenerator 13 outputs coordinates according to the selection signal. The input / output relationship of the vector regenerator 13 can be expressed as shown in FIG. The output signal (coordinate signal) of the vector regenerator 13 is
The modulated signals I and Q are input to the linear converter 14.

Here, the input / output relationship of the linear converter 14 is

[Equation 1] Can be expressed by a determinant.

By the way, in the amplitude phase modulation, a digital signal is often transmitted. In particular, when handling a limited number of input signals such as the QPSK modulation method, it is conceivable that the result of simulating delta sigma modulation with a computer or the like is stored in a memory in advance and called according to the modulation input.

That is, in the QPSK modulation, as shown in FIG. 19, a mapping device 16 is arranged in the preceding stage of the vector delta sigma modulator 10 shown in FIGS. 15 to 16, and the vector delta sigma modulator 10 and the mapping device are arranged. The signal conversion device 15 is constituted by 16 and. And
The transmission data input by the mapping device 16 of the signal conversion device 15 is converted into coordinates on the phase plane, and modulated signals I and Q to the vector delta sigma modulator 10 are generated. The vector delta-sigma modulator 10 converts the input modulation signals I and Q into selection signals for the selector 10. Here, both the vector delta-sigma modulator 10 and the mapping device 16 which compose the signal conversion device 15 are means for performing signal conversion in discrete time. The transmission data is also a digital signal string of several bits which constitutes the selection signal. Therefore, it is conceivable to replace the signal conversion device 15 including the vector delta-sigma modulator 10 and the mapping device 16 with signal conversion means using a memory as described above.

FIG. 20 shows an example in which the signal converting means shown in FIG. 19 is realized by using a memory. As shown in the figure, the signal conversion device 17 corresponds to the signal conversion device 15 shown in FIG. 19 and includes an address generation device 18 and a memory 19. Then, the address generator 18 converts the input transmission data into a predetermined memory address for the memory 19. The memory 19 outputs the output data of the designated memory address. The output corresponds to the output of the vector delta sigma modulator 10 (see FIG. 19) corresponding to the transmission data.

However, in order to obtain an output signal that is less affected by quantization noise, it is necessary to set the sampling frequency high. Therefore, when the above-mentioned memory is used, the data amount of the simulation result to be stored becomes large, which causes a problem that a large memory capacity is required.

For example, assume that the modulator generates a QPSK signal whose signal points are ,, as shown in FIG. a, b, c, d are signal sequences output by the vector delta sigma modulator 10, and positions (r, θ) on the coordinates of a, b, c, d are the pulses output by the selector 11. It represents the amplitude and phase.

It is assumed that the corresponding code is currently output on the phase plane. Since the next code is either or, the phase change can be expressed as shown in FIG.

Now, considering the case of outputting the following, for example, along the arrow line heading from to in FIG.
The phase changes. Vector delta-sigma modulator 10
Represents this by the ratio of the number of signal sequences a, b, c, d. The ratio of the numbers of the signal trains a, b, c, d means that if a point on the phase plane is represented by this, a is 80
The number is 50, b is 50, c is 20, and d is 50. Then, this ratio is changed in a form along the arrow line from to, for example, 50 a and 8 b.
When the number is 0, c is 50, and d is 20, points on the phase plane are represented. Saving the result of the above-mentioned simulation in the memory means, for example, that the vector delta sigma modulator 1
This means that a series of signal sequences output by 0 are stored in a memory.

In the above example, the case where the following is output was considered, but actually, as shown in FIG. 4, next, next, next as shown in FIG. Next to ..., but not shown, next to ..., Next to ..., and so on. Moreover, in wireless communication, the modulated signal is often band-limited in order to narrow the occupied frequency band. When the band is limited, the loci between the codes on the phase plane are affected by the codes before and after that.
Therefore, for example, the change (trajectory) of the phase from to also differs depending on the sign before the. For example, the signs before and of and the phase changes (trajectories) from to are different.

From the above description, it is understood that the result of simulating the delta sigma modulation results in an extremely huge amount of data. Therefore, when the simulation result is stored in the memory and is called according to the modulation input, a memory with a large memory capacity is required.

[0026]

As described above, the amplitude-phase modulator based on the delta-sigma modulation proposed by the present inventor can reduce power consumption and reduce the number of adjustment points. When the result of the simulation is stored in the memory and called in accordance with the modulation input, the amount of data of the simulation result to be stored becomes large, which causes a problem that a memory with a large memory capacity is required.

The present invention has been made in order to solve such a problem, and a result obtained by simulating delta sigma modulation in advance is stored in a memory and is called according to a modulation input. It is an object of the present invention to provide an amplitude phase modulator which can be realized in a memory having a small memory capacity in a phase modulator by reducing the data amount of the simulation result to be stored.

[0028]

In order to solve such a problem, the present invention stores a plurality of signal sequences representing the first locus on the phase plane in advance, and stores the plurality of signals according to the input modulation signal. A signal reproducing means for selecting and outputting one of the signal rows, and a signal row outputted by the signal reproducing means in response to a predetermined phase control signal, representing a second locus on the phase plane. Phase conversion means for converting into a signal sequence to
And a selecting means for selecting and outputting one of a plurality of signals having the same frequency and different phases or amplitudes according to each signal of the signal sequence converted by the phase converting means.

Further, according to the present invention, a plurality of signal trains representing the first locus on the phase plane are stored in advance, and one signal train is selected from the plurality of signal trains according to the input modulation signal. Signal reproducing means for outputting, phase control signal generating means for generating a phase control signal corresponding to the phase on the phase plane of the currently output converted signal sequence, and phase control signal generated by this phase control signal generating means Phase conversion means for converting the signal sequence output by the signal reproduction means into a conversion signal sequence expressing the second locus on the phase plane, and a conversion signal sequence converted by the phase conversion means. And selecting means for selecting and outputting one of a plurality of signals having the same frequency but different phases or amplitudes in accordance with each signal.

[0030]

According to the present invention, the same signal sequence output from the signal reproducing means is required to be converted by the phase converting means such as rotation on the phase plane or conversion into a signal line-symmetric with respect to a certain axis. Since it is possible to generate various signal sequences, it is possible to reduce the amount of data to be stored.
If the data becomes small, the amplitude / phase modulator can be realized by an integrated circuit having a small memory capacity, that is, a small chip area. In addition, a differential encoding method is often used in the phase modulation method, but since the phase conversion device can be in charge of the differential encoding process, the differential encoder can be omitted.

[0031]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an amplitude / phase modulator according to an embodiment of the present invention. In the figure,
Reference numeral 20 is a vector delta-sigma modulator, which includes a signal reproducing device 21 and a phase converting device 22. The vector delta sigma modulator 20 has a different configuration from the vector delta sigma modulator 10 shown in FIG. 15, but the selection signal output for the modulation signals I and Q is the vector delta sigma modulator shown in FIG. The same as 10. Also, 2
Reference numeral 3 denotes a selector, which has the same configuration as the selector 11 shown in FIG.

Next, the amplitude phase modulator of this embodiment is shown in FIG.
Description will be made in association with the amplitude phase modulator shown in FIG. Figure 2
FIG. 3 is a diagram showing a configuration of an amplitude / phase modulator of this embodiment.

The configuration comprising the phase conversion device 22, the signal reproduction device 24, and the phase signal generation device 27 shown in FIG.
0 corresponds to the signal converter 17 shown in FIG. The signal reproduction device 24 includes an address generation device 25 and a memory 26. Then, the transmission data is input to the address generation device 25 and the phase signal generation device 27 of the signal reproduction device 24. The address generator 25 converts the transmission data into a memory address signal according to the data. The address generator 25 converts the transmission data into a phase control signal according to the data. Here, in the amplitude / phase modulator device shown in FIG. 19, the memory 19 holds in advance different output data for each transmission data, and the address generation device 18 generates different addresses for different transmission data. ing. On the other hand, in the amplitude / phase modulator shown in FIG. 2, all output data that become equal when the memory 26 rotates on the phase plane are regarded as the same data, and these same data are held as one output data. is doing. The address generation device 25 generates an address according to the input transmission data, but generates an address corresponding to the output data that becomes the same when rotated on the phase plane, as the same address. The phase signal generator 27 is
The phase control signal corresponding to the phase on the phase plane of the signal train currently input to the selector 23 is generated. That is, in the case of output data that becomes the same when rotated on the phase plane, the same output data is input from the memory 26 to the phase conversion device 22, but in the case of output data that rotates on the phase plane, it corresponds to each phase. Since different phase control signals are input from the phase signal generation device 27 to the phase conversion device 22, as a result, the selector 23 has the same signal sequence as the signal sequence input from the signal conversion device 17 of FIG. 20 to the selector 11. Is entered.

This embodiment will be described more specifically assuming that the amplitude-phase modulator configured as shown in FIG. 2 generates a QPSK signal whose signal points are, as shown in FIG. . Here, a, b, c, d are signal sequences output by the phase converter 22, and the position (r, θ) on the coordinates of a, b, c, d is the pulse output by the selector 23. Represents the amplitude and phase of.

It is assumed that the corresponding code is currently output on the phase plane. Since the next code is either or, the phase change can be expressed as shown in FIG.

Next, it is assumed that the corresponding code is output on the phase plane. Since the next code is either or, the change in phase at this time can be expressed as shown in FIG. Here, comparing FIG. 4 with FIG. 5, it can be seen that when FIG. 4 is rotated counterclockwise by 90 °, it coincides with FIG. 4.

In the memory 26, the vector delta sigma conversion results from the signal point on the phase plane to the next signal point are recorded in advance.

The phase converter 22 is, as shown in FIG.
The input signals a, b, c, d input from the memory 26 are converted into any of the signals a, b, c, d according to the phase control signal output from the phase signal generator 27.
In this embodiment, the phase control signal is P1 when the amplitude / phase modulator is currently outputting a code corresponding to the phase plane, and is P1 when the amplitude / phase modulator is outputting a code corresponding to the current phase plane. Is P2, P3 when the corresponding code is currently output on the phase plane, and P4 when the corresponding code is currently output on the phase plane.

Here, when the transmission data is input to the signal regenerator 24 so as to move from to, ie, to the adjacent code in the counterclockwise direction on the phase plane, the signal regenerator 24 moves on the phase plane. A corresponding to the trajectory from to,
b, c, d signal sequences are output. The signals of the signal train are input to the phase converter 22.

Since the current phase control signal is P1, the phase conversion device 22 outputs the signal string output from the signal reproduction device 24 to the selector 23 as it is.

When the reproduction of the code string from the signal point to the signal point is completed, the phase control signal is changed to P2.

Next, when the transmission data is input to the signal reproducing device 24 so as to move to, ie, to the adjacent code in the counterclockwise direction on the phase plane, the signal reproducing device 2
4 outputs the signal sequence of a, b, c, d corresponding to the locus from to on the phase plane similar to the case described above. The signals of the signal train are input to the phase converter 22.

Since the phase control signal input from the phase signal generation device 27 to the phase conversion device 22 is P2, the phase conversion device 22 causes the signal sequence output from the signal reproduction device 24 to be a for b, Convert b to c, c to d, and d to a. As a result, the output of the selector 23 follows the trajectory from to.

As described above, the amplitude phase modulator of this embodiment is
Only the vector delta sigma conversion result from the signal point to the next signal point ,,, needs to be recorded in advance, starting from the signal point ,, the next signal point,
Since it is not necessary to record the vector delta-sigma conversion results up to and, it is possible to significantly reduce the memory capacity.

Further, the amplitude / phase modulator of the present invention is particularly advantageous in the case of the differential encoding system. That is, in the differential encoding system QPSK modulation system, the code moves to the adjacent code in the counterclockwise direction on the phase plane, the code moves to the adjacent code in the clockwise direction on the phase plane, the code moves to the diagonal direction, or Since it does not move corresponds to each code, a differential encoding device is required for use in the conventional analog modulator. On the other hand, in the amplitude phase modulator of the present invention, if the signal before differential encoding is input to the signal reproducing device 24 as described above, the effect of the differential encoding is taken by the phase converter 22. You can

If the input / output relationship of the phase converter 22 is defined as shown in FIG. 7, for example, the phase control signal is P5.
By doing so, the output of the signal sequence from the signal reproducing device 24 to the can be converted into the signal sequence from the signal point to. In this way, the trajectories having a mirror image relationship can also be composed of common data.

FIG. 8 is a diagram for explaining the second embodiment of the present invention.

Here, the signal point arrangement of the 8-phase PSK modulator is shown. The structure of the amplitude / phase modulator is the same as that shown in FIG.
It is necessary to store the signal for K. Phase converter 22
Stores the code string from the signal point to each signal point and the code string from the signal point to each signal point. When the starting signal point number is an odd number, the signal point data is used, and when the starting signal point number is an even number, the signal point data is used.

Therefore, like the first embodiment, in the second embodiment as well, if the input / output relationship of the phase converter 22 is as shown in FIG. 7, data conversion in a mirror image relationship is possible. For example, the signal sequence from the signal point to the signal point is changed to the phase control signal P
The signal sequence from the signal point to the signal point is obtained by the conversion by 5, and the signal sequence from the signal point to the signal point is obtained by converting the signal sequence from the signal point to the signal point by the phase control signal P8. Therefore, the data that needs to be stored in the signal reproducing device 24 is the data starting from the signal point to the signal point to and the data starting from the signal point to the signal point to.

The 8-point PSK signal point arrangement is π / 4 shift Q.
Same as PSK, but for π / 4 shift QPSK,
The data from the odd signal points to the odd signal points and the data from the even signal points to the even signal points in FIG. 8 are unnecessary.

FIG. 9 is a diagram for explaining the third embodiment of the present invention.

The figure shows the signal point arrangement of the 16QAM modulator. The amplitude phase modulator of this embodiment is applied to this signal point arrangement. The structure of the amplitude phase modulator of this embodiment is the same as that of FIG.
It is necessary to store the signal for 16QAM. In this case, the modulated signal can be configured by the signal points, the signal points, the data from the signal points to each signal point, and the conversion defined in FIG.

FIG. 10 is a diagram for explaining the fourth embodiment of the present invention.

The figure shows the signal point arrangement of the QPSK modulator. The amplitude phase modulator of this embodiment is applied to this signal point arrangement. In this case, the selector 23 selects and outputs one of five signals having phases different by 90 ° and a signal having an amplitude of 0. The input / output relationship of the phase converter 22 is as shown in FIG.

FIG. 12 is a diagram for explaining the fifth embodiment of the present invention.

The figure shows the signal and signal point arrangement of the modulator for π / 4 shift QPSK. The amplitude phase modulator of this embodiment is applied to this signal point arrangement. The input / output relationship of the phase converter 22 in this case is as shown in FIG. The signal reproducing device 24 stores data from signal point to signal point and data from signal point to signal point. The code string in the counterclockwise direction from each signal point is
It is obtained by the phase control signals P1 to P8. The code strings in the clockwise direction from each signal point are the phase control signals P9 to P16.
Obtained by

[0058]

As described above, according to the amplitude / phase modulator of the present invention, the memory capacity required for the vector delta-sigma modulator constituted by the memory can be reduced, so that the integrated circuit with a small chip area can be obtained. Can realize a vector delta-sigma modulation circuit, and can provide an amplitude-phase modulator at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an amplitude phase modulator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of the amplitude / phase modulator of FIG. 1 more specifically.

FIG. 3 is a signal point arrangement diagram of the amplitude phase modulator according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of phase transition.

FIG. 5 is an explanatory diagram of phase transition.

FIG. 6 is a diagram showing an input / output relationship of the phase conversion device in the amplitude phase modulator according to the embodiment of the present invention.

FIG. 7 is a diagram showing another input / output relationship of the phase conversion device in the amplitude phase modulator according to the embodiment of the present invention.

FIG. 8 is a signal point arrangement diagram of the amplitude phase modulator according to the second embodiment of the present invention.

FIG. 9 is a signal point arrangement diagram of the amplitude phase modulator according to the third embodiment of the present invention.

FIG. 10 is a signal point arrangement diagram of the amplitude phase modulator according to the fourth embodiment of the present invention.

FIG. 11 is a diagram showing an input / output relationship of a phase converter in the amplitude phase modulator according to the fourth embodiment of the present invention.

FIG. 12 is a signal point arrangement diagram of the amplitude phase modulator according to the fifth embodiment of the present invention.

FIG. 13 is a diagram showing the input / output relationship of the phase converter in the amplitude / phase modulator according to the fifth embodiment of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional analog quadrature modulator.

FIG. 15 is a block diagram showing a configuration of a conventional amplitude / phase modulator.

16 is a block diagram showing the configuration of the vector delta sigma modulator shown in FIG.

17 is a diagram showing an output of the encoder shown in FIG.

FIG. 18 is a diagram showing an input / output relationship of the vector regenerator shown in FIG.

FIG. 19 is a block diagram more specifically showing a configuration of the amplitude phase modulator shown in FIG.

20 is a diagram showing an example in which the signal conversion device of the amplitude / phase modulator shown in FIG. 19 is configured by a memory.

[Explanation of symbols]

20 ... Vector delta-sigma modulator, 21, 24 ... Signal reproduction device, 22 ... Phase conversion device, 23 ... Selector, 25 ...
Address generator, 26 ... Memory, 27 ... Phase signal generator.

Claims (2)

[Claims] 1. A signal reproduction in which a plurality of signal sequences expressing a first locus on a phase plane are stored in advance, and one of the plurality of signal sequences is selected and output according to an input modulation signal. Means, phase conversion means for converting the signal sequence output by the signal reproduction means into a signal sequence expressing a second locus on the phase plane, according to a predetermined phase control signal, and the phase conversion means. An amplitude / phase modulator comprising: a selecting unit that selects and outputs one of a plurality of signals having the same frequency and different phases or amplitudes according to each signal of the signal sequence converted by the above. 2. A signal reproduction for preliminarily storing a plurality of signal sequences expressing a first locus on a phase plane, and selecting and outputting one of the plurality of signal sequences according to an input modulation signal. Means, a phase control signal generation means for generating a phase control signal corresponding to the phase on the phase plane of the currently output conversion signal sequence, and a phase control signal generated by the phase control signal generation means, Phase conversion means for converting the signal sequence output by the signal reproduction means into a conversion signal sequence expressing the second locus on the phase plane, and each signal of the conversion signal sequence converted by the phase conversion means. An amplitude / phase modulator according to claim 1, further comprising: selecting means for selecting and outputting one of a plurality of signals having the same frequency but different phases or amplitudes.