JPH07130858A - Semiconductor integrated circuit and its manufacturing method - Google Patents

Abstract

PURPOSE:To install an additional transistor which is used for correcting a circuit under the reinforcing wiring of power supply and ground and to correct the circuit relatively simply by changing the type of a diffusion layer or laying out a gate electrode in advance. CONSTITUTION:An N well for forming a PNP-type transistor and a P-well for forming an NPN-type transistor are formed on the same substrate. Diffusion layers CP and Cn are originally located at a power supply reinforcement region but gate electrodes A1 and A2 are wired over the P-well and N-well on it, this enabling a gate to be formed, Further, a power supply wiring Vj which is a first-layer wiring and a ground wiring G1 are laid out on it and a power supply wiring V2 which is a second-layer wiring for reinforcing power supply and a ground wiring G2 are wired on it. With this configuration, additional transistors for correcting a circuit can be installed to correct the circuit relatively easily.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a mounting technique for a semiconductor integrated circuit having a cell-based mask layout area such as a standard cell used in an ASIC.

[0002]

2. Description of the Related Art With the recent large-scale integration and high speed of LSIs, there is an increasing demand for semiconductor integrated circuits such as gate arrays and ASICs that provide circuits in accordance with user requirements. Also in semiconductor integrated circuits having these cell-based mask layout portions, wiring methods for mounting power supply wirings and ground wirings have been studied due to the problem of current consumption, and the problems have become remarkable.

FIGS. 6 and 7 show a conventional cell-based mass.
An example of playout is shown. FIG. 6 shows an LSI having multilayer wiring.
The whole shape of one chip of P-well
Or a cell region obtained by diffusing an N-well,
Power supply wiring V of the first layer₁And ground wiring G₁And the second
Power supply wiring V of the layer₂And ground wiring G ₂And with
The cell area is composed of circuits such as transistors.
An area for forming the body. The first layer and the second layer
Each wiring in is electrically connected by through holes.
Power supply wiring and ground wiring in each cell area.
Various gates and the like can be formed by using.

FIG. 7 (a) shows an enlarged view of the intersection area of the power supply wiring and the ground wiring in FIG. Figure 7 (b)
7A shows a cross-sectional view of the semiconductor integrated circuit cut along the line XX ′ in FIG. As shown in the cross-sectional view, the power supply wiring has two layers, that is, a power supply and a ground.
This is because in order to prevent the so-called electromigration phenomenon in which the movement of ions occurs when the amount of current in the power supply wiring increases and the current concentrates at one location, which causes disconnection of the power supply wiring or the ground wiring, The purpose is to reinforce a plurality of points by the second layer metal wiring to disperse the current. In an LSI having a relatively large amount of current such as a bipolar integrated circuit, consideration of such power supply wiring is essential.

Conventionally, it is difficult to arrange a normal standard cell in this region, that is, in a region below the reinforcing wiring of the power supply and the ground by the reinforcing second layer metal wiring (hereinafter referred to as a power supply reinforcing area). Therefore, it is only used as an empty region, a substrate contact for fixing the substrate potential or the well potential, or a well contact region. Therefore, the dummy N-type diffusion layer C _n ′ is provided in the N-well cell region, and the dummy P-type diffusion layer C _p ′ is provided in the P-well cell region.

[0006]

However, under the present circumstances where the circuit scale becomes large and the verification of the operation becomes very difficult, as in today's LSI, a problem in the circuit operation is found after the layout is completed. There is an increasing number of cases where it is necessary to modify a part of the circuit, or when a defect is discovered after actually making a prototype of an integrated circuit and a circuit must be added. It is a problem that cannot be avoided at the stage. The contents of the corrections / additions are often to add a gate for signal logic inversion or timing adjustment, and therefore, it is necessary to add a new transistor.

If these defects are only those for connecting and converting the already arranged cells, it is possible to correct them relatively easily because only the revision of the metal wiring is necessary, but if a new cell has to be added, the high density is required. There is a problem that it is necessary to re-lay out and re-trial-produce the pattern accumulated on the substrate, which is very time-consuming. Even if the area for correction is provided in one place on the substrate, if the position where the additional circuit for those transistors should be inserted and the cell position of the circuit for the addition are separated, the wiring becomes longer and the wiring becomes longer. It is meaningless because it is troublesome to draw around.

Therefore, an object of the first invention and the second invention is to provide a semiconductor integrated circuit having a layout which can be corrected relatively easily when a design is changed.
A third aspect of the present invention provides a semiconductor integrated circuit manufacturing process in which the addition of gates or the like can be relatively easily corrected even in the final designing process by using the semiconductor integrated circuit of the first or second aspect. Especially.

[0009]

The semiconductor integrated circuit for the above-mentioned purpose has an additional structure for use in circuit modification under the power supply and ground reinforcing wirings by the metal wiring of the second layer in the cell-based layout area. To be able to install a transistor,
This is achieved by changing the type of diffusion layer to be provided and arranging the gate electrode in advance. This gate electrode is usually not connected to any circuit.

Explaining the above matters in detail, the first invention is, in a semiconductor integrated circuit having a multilayer structure having a cell base layout region, a first wiring layer (L ₁ ) having a power supply wiring and a ground wiring, was extended in a direction crossing the extending direction of the first wiring layer (L _1), the second wiring layer having a power supply wiring and ground wiring (L _2), the first wiring layer (L ₁₎ and a second provided in a different layer from the wiring layer (L _2), and, the first wiring layer (L ₁₎ and the semiconductor integrated provided at a position corresponding to the second wiring layer (L ₂₎ of the crossing areas (R) The redundant cells (C _n , C _p ) for modifying the circuit
It is achieved by a semiconductor integrated circuit including and.

A second aspect of the present invention is the first wiring layer (L ₁ )
Alternatively, in the second wiring layer (L ₂ ), the semiconductor integrated circuit according to the first aspect of the present invention has a wiring region having a width allowing one or a plurality of wirings in a region between the power supply wiring and the ground wiring.

A third invention is a semiconductor integrated circuit manufacturing method for manufacturing using a semiconductor integrated circuit having a multilayer structure having a cell base layout region, which is the first invention or the second invention.
A layout process (step S303) for designing a pattern based on the semiconductor integrated circuit of the invention described above to create an evaluation semiconductor integrated circuit; and a layout process (step S30).
3) In the operation evaluation step (step S304) for verifying the operation of the evaluation semiconductor integrated circuit designed, and in the operation evaluation step (step S304), it is determined that the circuit modification of the specific portion of the evaluation semiconductor integrated circuit is necessary. If
The redundant cell (C
_This is achieved by a semiconductor integrated circuit manufacturing method including a re-layout step (step S305) of correcting a circuit at a specific location including _n , C _p ).

[0013]

According to the first aspect of the invention, in a semiconductor integrated circuit having a multilayer structure having a cell base layout region, the first-layer wiring and the second-layer power supply wiring and the ground wiring are present in different layers from each other, and the pattern Are crossed, and the redundant cell for correcting the semiconductor integrated circuit is provided at a position (for example, the lower periphery) corresponding to the crossing area of the two, and if additional correction is necessary, A gate can be formed using this redundant cell, and a new element can be added to the semiconductor integrated circuit.

Further, according to the second invention, the area between the power supply wiring and the ground wiring of the first layer wiring or the second layer wiring is a wiring area having a width allowing one or a plurality of wirings. Since it has, by forming the pattern by using the area between these at the time of routing the wiring at the time of additional correction,
You can make additional corrections.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor integrated circuit having a multilayer structure having a cell base layout region, the layout step is a circuit diagram based on the semiconductor integrated circuit of the first aspect or the second aspect. A layout design based on the above is performed to create an evaluation semiconductor integrated circuit, and in the operation evaluation process that follows, the operation of the evaluation semiconductor integrated circuit designed by the layout process is verified to ensure that the originally planned operation is performed. Evaluate whether or not.
When it is determined by the operation evaluation process that the semiconductor integrated circuit for evaluation is not operating properly, and as a result, it is determined that the circuit at the specific location needs to be corrected, the redundancy provided at the position corresponding to the specific location by the relayout process. It is possible to effectively modify the wiring including the cells and modify the circuit at a specific location.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the semiconductor integrated circuit of the present invention will be described with reference to the drawings. (I) First Embodiment In the first embodiment of the present invention, a diffusion layer and a gate electrode for forming a transistor are placed inside the power supply reinforcing cell instead of the conventional substrate and well contact. is there.

The structure of the first embodiment is shown in FIG. Figure 1
The semiconductor integrated circuit of this embodiment shown in (a) is a PNP type transistor.
N-well and NPN type tiger for forming a transistor
On the same substrate as the P-well to form the transistor
Has been formed. The diffusion layer (C_p, C_n) Is a book
The gate electrode is located on the power supply reinforcement area
A ₁And A₂Is wired across the P-well and N-well.
Therefore, the gate can be formed.
Furthermore, on the upper part thereof, the power supply wiring V which is the wiring of the first layer₁
And ground wiring G₁Is placed on the
Power supply wiring V which is the second layer wiring for strong use₂And ground
Line G₂Is wired. The gate electrode A₃Is traditional
Circuit wiring and the gate of the cell region.

FIG. 1 (b) shows the first actual product shown in FIG. 1 (a).
FIG. 2 is a cross-sectional view of the semiconductor integrated circuit of the example, which is the same as the one shown in FIG.
A cross section of the substrate taken along the dotted line X-X 'is shown.
It As shown in the cross-sectional view, the substrate has a multilayer structure.
Power supply wiring V for power supply reinforcement on the top layer₂And ground
Line G₂By arranging the
It is dispersed. In addition, N-W
And a P-type diffusion layer C for modifying the circuit is further formed thereon.
_pAre shown to be diffused. And this
Is the diffusion layer not arranged in the conventional semiconductor integrated circuit?
Gate electrode A ₁And A₂Is wired. This
The gate electrode is located in the lower layer and determines the state of the diffusion layer
Since it is a thing, it should be installed from the initial design stage.
If so, it will be difficult to correct later.

As shown in FIG. 1, the upper half of the figure is an N-way
P type diffusion layer C for circuit modification on the rule layer _pIs provided
And the gate electrode is arranged thereon. for that reason,
Power supply wiring by providing contact holes in each part of the P-type diffusion layer
Alternatively, by connecting to the ground wiring, the PNP type
A transistor can be formed. Also, P-well
In the region (lower half of FIG. 1A), the N-type diffusion layer C for circuit correction is used.
_nAre provided, and contact holes are made in the same way.
NP by connecting the power supply wiring or the ground wiring with
It is also possible to form an N-type transistor.

At the time of initial design of a semiconductor integrated circuit, a gate or the like made of a transistor or the like is arranged in the cell region. Unless a design error or a circuit change is made, the power supply reinforcement region as shown in FIG. Has no circuitry. However, when a test of a circuit is completed after the trial manufacture of an integrated circuit is completed, some kind of operation inconvenience usually occurs, and the circuit must be modified in order to cope with it.

Therefore, if there is a structure in which a diffusion layer and a gate electrode that can be actually used are provided as in this embodiment, the structure is used for an additional circuit, which causes unnecessary movement of the existing circuit. Circuit can be added without

For example, when it becomes necessary to provide a NAND gate near the power supply reinforcement area in FIG. 1A, the power supply can be easily performed by providing a contact hole in the power supply wiring and the ground wiring of the first layer. The transistor made of the P-type diffusion layer C _p for circuit correction and the N-type diffusion layer C for circuit correction
NAND by connecting with the transistor made in _n
A gate can be formed. By wiring the gate formed in this way to a necessary location in the vicinity, it becomes possible to easily add a circuit without moving the wiring and gates that have already been wired.

FIG. 2 shows an example of wiring when the NAND gate is added as described above. The figure shows a freehand addition of gates. A transistor is provided in an originally unused power supply reinforcing region.

According to the first embodiment, a region which has not been used as a power supply reinforcing region in the related art can be effectively used as a correction wiring region, and a gate electrode has already been arranged. Transistors can be easily added simply by adding lead wires, and a new gate can be created by configuring transistors of multiple cells. (Ii) Second Example The second example of the present invention corresponds to the second aspect of the present invention, in which not only the power supply wiring, the ground wiring, and the gate electrode are provided in the power supply reinforcing area, but also added as much as the area allows. This is to leave a space for wiring.

FIG. 3 shows the configuration of the semiconductor integrated circuit of the second embodiment. The difference from the first embodiment is that the space between both electrodes of the second layer is wide and a space for a plurality of additional wirings is provided. As in the first embodiment, N on the substrate
-Wells (upper half of Figure 3) and P-wells (lower half of Figure 3) are provided. The N-well is further provided with a circuit-modifying P-type diffusion layer C _p for providing a PNP-type transistor, and the P-well is provided with a circuit-modifying N-type diffusion layer C _n for the NPN-type transistor. There is. The gate electrodes A ₁ and A ₂ are laid across the upper and lower diffusion layers in the figure,
Although a tap for drawing out is provided, it is normally unwired. The gate electrode A ₃ is a part of the original wiring on the standard cell. In the upper layer, the power supply wiring V ₁ which is the wiring of the first layer is provided on the N-well and the ground wiring G.
₁ is laid on the upper portion of the P-well, and further, the power supply wiring V ₂ and the ground wiring G ₂ of the second layer for power supply reinforcement are laid on the power supply reinforcement area at right angles to the wiring of the first layer. ing.

Now, in the semiconductor integrated circuit of the second embodiment, when circuit modification / addition of elements is required, a contact hole is provided for the power supply wiring or the ground wiring of the first layer for the same purpose as in the first embodiment. To make a transistor. At that time, it is conceivable to effectively use the space between the power supply wiring and the ground wiring of the first layer provided in this embodiment.

That is, since this space has the width of a plurality of wiring lines (of course, only one line is enough), the wiring can be routed by the additional gate through this space. An example of forming the additional gate in this way is shown in FIG. This is also an example in which a NAND gate is added.

According to the second embodiment, it is easy to make additional corrections in the middle stage of circuit design. In addition, since a space that is not normally used is provided between the power lines, it is easy to draw the lines. This embodiment is an LSI with a particularly high packaging density,
Even if it is difficult to extend the additional wiring on the standard cell side because the standard cell area is filled with wiring, additional correction can be performed relatively easily. (Iii) Third Example A third example is a semiconductor integrated circuit manufacturing method using the semiconductor integrated circuit of the present invention.

In the conventional LSI manufacturing method using standard cells such as ASIC and gate array, when a number of logic simulations are completed and the logic design and logic verification are completed, it is determined that the circuit has been decided and automatic layout by CAD or the like. Enter the process. Then, through layout verification, a mass production process such as mask manufacturing is performed.

However, as described above, the circuit scale becomes large and the design time is shortened, so that a layout or circuit inconvenience may be discovered after the automatic layout design by CAD is completed. . Most of such corrections can be realized by simple gates such as logic adjustment and slight timing adjustment.

Therefore, as in the present invention, if a semiconductor integrated circuit that can easily form an additional gate even when the standard cell is fully used is used as a basis, it is possible to make an urgent correction at the final stage of this design. Relatively easy to respond.

The process of the third embodiment will be described with reference to FIG. First, as the design of a semiconductor integrated circuit, functional design based on basic specifications is performed, and the number of input / output terminals, types of control terminals,
Basic specifications such as an allowable operating timing range and input / output conditions are designed in the functional design process (step S301).

Then, based on the determined input / output conditions,
Logic design is performed by combining gates provided in standard cells or the like so as to satisfy the condition, and mainly timing verification is performed (step S302). Many of these processes are automated by computer,
Specifically, design rule check, logic simulation, timing verification, test design, etc. are performed.
Normally, it is desirable that thorough circuit verification be performed in this step.

Then, the layout design process determines how the standard cells of the selected substrate are connected to actually arrange the circuit created in the logic verification design process (step S302) (step S303). .

Next, the operation evaluation step evaluates whether or not the desired operation is performed in the finally placed mounting state (step S304). When a timing problem or the like that could not be considered in the simulation is found due to the influence of the pattern routing or the like (step S304: N
O), layout is performed in the relayout process. Most of the corrections in this case are simple, and there are many local corrections. Often, the corrections are mainly performed manually without needing to read out a CAD file having an enormous capacity and make corrections. In this case, the circuit modifying cells of the present invention, which are evenly arranged over the entire standard cell region, can be effectively used. For example, when it is desired to insert a NAND gate at one point on a circuit, the gate can be constructed by combining a transistor having a P-type diffusion layer and a transistor having an N-type diffusion layer as shown in FIG. Furthermore, the wiring up to the correction point can be performed by using the gap between the power supply wiring and the ground wiring of the layer related to the power supply according to the second invention.

If the operation evaluation is finally good after the correction as described above (step S304), the mask manufacturing process is started (step S306). According to the third embodiment, the gate can be assembled relatively easily by using the correction circuit cell existing in the vicinity of any standard cell, and the wiring to the corresponding correction point also passes through the normal wiring area. Correction work can be done more easily than doing it. Other Modifications The present invention is not limited to the above embodiments, but various modifications are possible.

For example, in each of the above embodiments, the circuit correction P
Although two gate electrodes are arranged across the type diffusion layer C _p and the circuit correction N-type diffusion layer C _n , the gate electrodes on the P-type diffusion layer and the N-type diffusion layer are separated and four gate electrodes are provided. It may be a gate. Furthermore, a larger number of gate electrodes may be arranged depending on the width of the cell for power supply reinforcement.

[0038]

As described above, according to the first aspect of the present invention, since the previously unused area is used for additional correction, the layout correction and trial development period can be reduced without lowering the integration density in the semiconductor integrated circuit. Can be shortened.

Further, according to the second aspect of the invention, since the area for routing the circuit correction pattern is prepared in the power supply wiring, the wiring in the standard cell area should be changed even in the high-density mounted semiconductor integrated circuit. It is possible to easily make additional corrections without adding.

According to the third invention, the first invention or the second invention
By using the semiconductor integrated circuit of the invention described above, a re-layout process is provided after the layout process, so that the circuit modification at the final stage can be performed relatively easily.

[Brief description of drawings]

FIG. 1 is a mounting view showing a semiconductor integrated circuit according to a first embodiment.

FIG. 2 is a mounting diagram showing a wiring example of a semiconductor integrated circuit according to a first embodiment.

FIG. 3 is a mounting view showing a semiconductor integrated circuit according to a second embodiment.

FIG. 4 is a mounting diagram showing a wiring example of a semiconductor integrated circuit according to a second example.

FIG. 5 is a flowchart illustrating a method for manufacturing a semiconductor integrated circuit according to a third embodiment.

FIG. 6 is an explanatory diagram showing an overall shape of a conventional semiconductor integrated circuit.

FIG. 7 is a mounting diagram showing a conventional semiconductor integrated circuit.

[Explanation of symbols]

_{A 1, A 2, A 3} ... gate electrode B ... substrate C _p ... circuit modified P-type diffusion layer C _n ... circuit modification N-type diffusion layer C p _'... P-type diffusion layer C n _dummy' ... dummy N-type diffusion layer G ₁ ... First layer ground wiring G ₂ ... Second layer ground wiring H _t ... Through hole H _c ... Contact hole L ₁ ... First wiring layer L ₂ ... Second wiring layer R ... Crossing area V ₁ ... 1st layer power supply wiring V ₂ ... 2nd layer power supply wiring

Claims (3)

[Claims] 1. A multi-layered semiconductor integrated circuit having a cell base layout region, comprising: a first wiring layer (L ₁ ) having a power supply wiring (V ₁ ) and a ground wiring (G ₁ ); Power supply wiring (V ₂ ) and ground wiring (G ₂ ) extending in a direction intersecting the extending direction of L ₁ ).
And a second wiring layer (L ₂ ) having the same, and provided in a layer different from the first wiring layer (L ₁ ) and the second wiring layer (L ₂ ), and the first wiring layer (L ₁ )
And the redundant cell (C _n , C _p ) provided in a position corresponding to the intersection region (R) of the second wiring layer (L ₂ ) for correcting the semiconductor integrated circuit. A characteristic semiconductor integrated circuit. 2. In the first wiring layer (L ₁ ) or the second wiring layer (L ₂ ), power supply wiring (V ₁ , V ₂ ) and ground wiring (G ₁ ,
_2. The semiconductor integrated circuit according to claim 1, further comprising a wiring region having a width allowing one or a plurality of wirings in a region between G ₂ ). 3. A semiconductor integrated circuit manufacturing method for manufacturing using a semiconductor integrated circuit having a multilayer structure having a cell base layout region, wherein pattern design is performed based on the semiconductor integrated circuit according to claim 1 or 2. Layout step of creating a semiconductor integrated circuit for use (step S303), an operation evaluation step (step S304) of verifying the operation of the evaluation semiconductor integrated circuit designed by the layout step (step S303), and the operation evaluation step When it is determined in (step S304) that the circuit modification of the specific part of the evaluation semiconductor integrated circuit is necessary, the redundant cells (C _n , C _p ) provided at the position corresponding to the specific part are included. In addition, a relayout process (step S30) for correcting the circuit at the specific portion
5) A method for manufacturing a semiconductor integrated circuit, comprising: