JPH0713860A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate the waste of the storage capacity of a RAM and shorten program execution time by previously transferring constant data, stored in a ROM, to a RAM. CONSTITUTION:The ROM 12 has a 1st bank and a 2nd bank given in the same storage area. When the 2nd bank is decided, the areas of low-order addresses are different between the ROM 12 and RAM 13, so there is no conflict of data. When the RAM 13 is accessed, the contents of a data access bank register R2 are set to the 2nd bank. When constant data stored in the ROM 12 are accessed, the contents of the data access bank register R2 are held as the 2nd bank as they are and need not be rewritten. Therefore, the waste of the storage capacity of the RAM 13 resulting from the previous transfer of the constant data stored in the ROM 12 to the RAM 13 is eliminated. Consequently, a program stored in the ROM 12 is made short to shorten the execution time of the program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a microprocessor unit.

[0002]

2. Description of the Related Art FIG. 5 shows an M including a ROM and a RAM.
The memory map of PU is shown. When & H is attached to the head and a hexadecimal number is written, the address areas of the internal ROM and internal RAM are & HFF8000 to & HFFFFFF and & H000100 to & H001000, respectively.
Programs and constant data are stored in the internal ROM, while the internal RAM is used as a work area for accessing data.

In order to reduce the number of bits of the address designation section in the instruction word and shorten the instruction word length, the entire memory space is
It is divided into banks that are distinguished by the upper 8 bits. The instruction word read bank in the program is held in the instruction word access bank register R1 and the data access bank is held in the data access bank register R2. In the data access bank register R2, & H00 must be written to access the data in the internal RAM, and & HFF must be written to access the constant data in the internal ROM. Therefore, the internal R of the access target
It is necessary to rewrite the contents of the data access bank register R2 according to the AM and the internal ROM, which causes a long program and a long program execution time.

In order to solve this problem, conventionally, in an initialization routine executed immediately after power-on,
All constant data in the internal ROM has been transferred to the internal RAM, and the constant data has been read from the internal RAM.

[0005]

However, extra time is required to transfer the constant data in the internal ROM to the internal RAM, and the available capacity of the internal RAM is reduced. In view of such problems, the object of the present invention is to
Since the constant data stored in the OM is transferred to the RAM in advance, it is possible to eliminate waste of the storage capacity of the RAM.
An object of the present invention is to provide an information processing device that can shorten the program stored in the OM and can shorten the program execution time.

[0006]

An information processing apparatus according to the present invention will be described with reference to the reference numerals of corresponding constituent elements in the embodiments. According to the present invention, for example, as shown in FIGS. 1 to 3, the banks are distinguished by the upper address, the ROM 12 selected by the first select signal CS1 in which the program and the constant data are stored is assigned to the first bank, and the second select signal is assigned. R selected by CS2 to access data
AM13 is assigned to the second bank, and in an information processing device having a register R1 holding an instruction word access bank and a register R2 holding a data access bank in the CPU 11, the bank is determined based on the upper address. However, the bank decoding circuit 16 that generates the first select signal CS1 when it is determined to be the first bank or the second bank and generates the second select signal CS2 when it is determined to be the second bank And a lower address area excluding the higher address from all addresses is a ROM
12 and RAM 13 are different.

With the above configuration, the ROM 12 is provided with the first bank and the second bank in the same storage area. When it is determined that the bank is the second bank, both the first select signal CS1 and the second select signal CS2 are active, but the lower address areas are the ROM 12 and the RAM.
Since it is different from 13, the data collision does not occur because only one of the ROM 12 and the RAM 13 is accessed.

When accessing the RAM 13, first, the contents of the data access bank register R2 are set to the second bank. When the constant data stored in the ROM 12 is accessed, the contents of the data access bank register R2 had to be set to the first bank as a pre-processing in the past, but in the present invention, the contents of the data access bank register R2 are changed to the second bank. There is no need to rewrite the bank as it is.

Therefore, the RAM 1 is obtained by transferring the constant data stored in the ROM 12 to the RAM 13 in advance.
Waste of the storage capacity of 3 can be omitted, the program stored in the ROM 12 can be shortened, and
The program execution time can be shortened. In the first aspect of the present invention, for example, as shown in FIG. 3A, each bit of the first bank has the same value, and each bit of the second bank has a value obtained by inverting the same value. The decoding circuit 16 includes an AND gate 21A or a NOR gate 22 to which an upper address is supplied, as shown in FIG.
The output of A determines that the bank is the first bank or the second bank.

In this case, the structure is particularly simple. In the second aspect of the present invention, in addition to the above configuration, for example, as shown in FIG. 4, the address discrimination circuit 33 to discriminates that the bank is the second bank and the lower address is outside the lower address area of the RAM 13. 35, an address conversion circuit 32 for converting the lower address to a lower address of the ROM 12 outside the lower address area of the RAM 13, and when the determination is made, the output of the address conversion circuit 32 is selected and the determination is made. When the above is not performed, the selector 31 which selects the lower address is used, and the output selected by the selector 31 is used for designating the lower address of the ROM 12 and the RAM 13.

In the case of this configuration, an RO having two banks
The lower addresses in both banks of M12 can be different. A third aspect of the present invention is a microprocessor unit in which the information processing apparatus having the above configuration is integrated into a single chip. The effect of the present invention is remarkable when applied to a microprocessor unit having a relatively small storage capacity, which has the ROM 12 and the RAM 13 built-in.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a schematic configuration of the one-chip MPU 10. The MPU 10 includes a CPU 11, ROM 12, RA
An M13, a peripheral circuit 14, an I / O port 15, a bank decode circuit 16, an address bus 17 and a data bus 18 are provided, and the address bus 1 is provided between the constituent elements 11 to 16.
7 and the data bus 1 is connected between the constituent elements 11 to 15.
8 are connected.

The peripheral circuit 14 includes, for example, a timer, a serial / parallel conversion circuit, a parallel / serial conversion circuit, an A / D converter and the like. Address bus 17 is 2
It has 4 bits, and its memory space is divided into banks represented by the upper 8 bits. The bank for reading the instruction word and the bank for accessing the data are respectively the CPU 11
It is designated by the instruction word access bank register R1 and the data access bank register R2. The upper 8 bits of the program counter in the CPU 11 are determined by the content of the instruction word access bank register R1, while the upper 8 bits of the data access address are determined by the content of the data access bank register R2 and the lower 16 bits are the instruction word. Determined by the addressing section inside. With such a configuration, it is possible to specify an address in a large-capacity memory space with a short instruction word length.

The bank decoding circuit 16 activates the select signals CS1 to CS4 in accordance with the values of the upper 8 bits A23 to A16 (upper address) of the address,
ROM 12, RAM 13, peripheral circuit 14 and I respectively
One of the / O ports 15 is enabled, and data can be exchanged with the CPU 11 via the data bus 18. In the activated ROM 12 or RAM 13, the storage address is designated by the lower 16 bits of the address.

The ROM 12 has two first and second address areas for the same storage area. For example, FIG.
As shown in (A), the first address area is & HFF800.
0 to & HFFFFFF, the second address area is & H008
000- & H00FFFF. This second address area is the address area & H00010 of the RAM 13.
0 && H000FFF, the same bank & H00.

In order to give two address areas to the same storage area of the ROM 12, the bank decoding circuit 16
As a component thereof, is generally provided with a select signal CS1 & CS2 generating circuit 20 as shown in FIG. 1 (A) to create the select signal CS1. Both the first bank determination circuit 21 and the second bank determination circuit 22 are supplied with the upper 8 bits A23 to A16 of the address, and the first bank determination circuit 21 only determines that this address is the first bank. Outputs a high level, and the second bank determination circuit 2
2 indicates that this address is the second as the select signal CS2.
High level is output only when it is determined to be a bank.
The outputs of the first bank determination circuit 21 and the second bank determination circuit 22 are supplied to the OR gate 23, and the logical sum of them is output as the select signal CS1.

In the case of FIG. 3A, since the first bank is the bank & HFF and the second bank is the bank & H00, the select signal CS1 & CS2 generating circuit 20 is shown in FIG.
A circuit 20A as shown in (B) can be used. That is, the AND gate 2 is used as the first bank determination circuit 21.
1A and the NOR gate 22A can be used as the second bank determination circuit 22, which simplifies the configuration.

Next, the operation of the first embodiment constructed as described above will be explained. When the content of the data access bank register R2 is & HFF, only CS1 of the select signals CS1 to CS4 becomes high level, and when the content of the data access bank register R2 is & H00, the select signal C
Both S1 and CS2 go high. But ROM
Since the lower 16 bits (lower address) of the addresses of 12 and RAM 13 are different from each other, only one of them can be accessed and data collision does not occur.

The reset signal RST is supplied to the CPU 11 by the reset operation immediately after the power is turned on or thereafter,
The content of the instruction word access bank register R1 is set to & HFF, and the program stored in the ROM 12 is stored in the CPU 11
Executed by. When accessing the RAM 13, the CPU 11 first sets the data access bank register R2.
The content of is & H00. In the case of accessing the constant data stored in the ROM 12, the CPU 11 conventionally needs to set the content of the data access bank register R2 to & HFF as a preprocessing, but in the first embodiment, the first data assigned to the ROM 12 is used. 2 address area & H0080
Since it is possible to access 00 to & H00FFFF, the contents of the data access bank register R2 are set to & H0
There is no need to rewrite as 0.

Therefore, the RAM 1 is obtained by transferring the constant data stored in the ROM 12 to the RAM 13 in advance.
It is possible to eliminate the waste of the storage capacity of 3, and to shorten the program stored in the ROM 12 as compared with the conventional one.
Moreover, the program execution time can be shortened. [Second Embodiment] In the first embodiment, as shown in FIG. 3A, the ROM 12 includes a bank & HFF and a bank & H00.
Although the lower 16 bits of are the same, the lower 16 bits can have different values as shown in FIG.

In this case, the address of the bank & HFF & H
8000 && HFFFF and bank & H00 address &
One ROM in correspondence with H1000 to & H8FFF
12 are assigned. ROM 12 is associated with bank & HFF and bank & H00, and RAM 13 is associated with bank & H
Since it is the same as the first embodiment in that it corresponds to 00, the select signal CS1 & CS2 generation circuit 20A shown in FIG. 1B can be used.

However, the lower address of the ROM 12 & H8
000- & HFFFF and lower address & H1000- &
Since the H8FFF and the H8FFF correspond to each other, the address discrimination / conversion circuit 30 as shown in FIG.
Prepare for 11. For the addresses A23 to A00 output from the CPU 11, the addresses generated by decoding the address part of the instruction word in the CPU 11 are A15 'to
Notated as A00 '. Addresses A15'-A12 'are
It is commonly supplied to one input terminal of the selector 31, the address conversion circuit 32, and the OR gate 33. On the other hand, the upper address A held in the data access bank register R2
23 to A16 are supplied to the NOR gate 34. The output of the address conversion circuit 32 is supplied to the other input end of the selector 31. The outputs of the OR gate 33 and the NOR gate 34 are both supplied to the AND gate 35, and the output thereof is supplied to the control input terminal of the selector 31. Address conversion circuit 3
2 shifts up & H1 to & H9 to & H8 to & HF.

The other points are the same as those of the first embodiment. In the above configuration, when the value of the upper address A23 to A16 is 0 and the value of the address A15 'to A12' is not 0, that is, the lower address is in & H1000 to & HFFFF in the bank & H00 (second bank) (outside the address area of the RAM13). ), The output of the AND gate 35 becomes high level, the output of the address conversion circuit 32 is selected by the selector 31, and the selector 31 selects & H1.
Addresses A15 to A12 obtained by converting the values in & H9 to & H8 to & HF are output. Meanwhile, the bank is & H
00, the select signal C in FIG.
S1 and CS2 go high. Therefore, the RAM 13 and the ROM 12 can be data-accessed without changing the bank & H00.

According to the second embodiment, the lower addresses of both banks of the ROM 12 having two banks can be made different, but the configuration becomes complicated as compared with the first embodiment. In addition, the present invention includes various modifications. For example, in FIG. 2, the second address area of the ROM 12 is connected to the outside of the MPU 10 and is not shown in the RAM.
The same bank may be used.

[0025]

As described above, in the information processing apparatus according to the present invention, the contents of the data access bank register can be set to the second bank regardless of whether the data is accessed from the RAM or the ROM. It is possible to eliminate the waste of the storage capacity of the RAM due to the transfer of the stored constant data to the RAM in advance, it is possible to further shorten the program stored in the ROM, and it is possible to shorten the program execution time. It has an excellent effect.

According to the first aspect of the present invention, there is an effect that the structure is particularly simple. According to the second aspect of the present invention, it is possible to make different lower addresses in both banks of a ROM having two banks. According to the third aspect of the present invention, since the storage capacities of the ROM and the RAM are relatively small, the above effect of the present invention is remarkable.

[Brief description of drawings]

FIG. 1 is a select signal C constituting a bank decode circuit.
It is a S1 & CS2 generation circuit diagram.

FIG. 2 is a block diagram showing a schematic configuration of a microprocessor unit.

FIG. 3 is a memory map inside a microprocessor unit.

FIG. 4 is an address discrimination / translation circuit diagram.

FIG. 5 is a memory map of a conventional microprocessor unit.

[Explanation of symbols]

 10 MPU 11 CPU 12 ROM 13 RAM 16 Bank Decode Circuit 20, 20A Select Signal CS1 & CS2 Generation Circuit 21 First Bank Determination Circuit 22 Second Bank Determination Circuit 30 Address Discrimination / Conversion Circuit 31 Selector 32 Address Conversion Circuit

Claims (4)

[Claims] 1. A bank is distinguished by an upper address, a program and constant data are stored, and a first select signal (C
The ROM (12) selected in S1) is assigned to the first bank, the RAM (13) selected by the second select signal (CS2) and accessed for data is assigned to the second bank, and the instruction word access bank Register holding (R
1) and a register (R
2) and an information processing device having a CPU (11), the bank is determined based on the higher-order address, and when it is determined that the bank is the first bank or the second bank, the first select signal is output. A bank decode circuit (16) for generating the second select signal when it is determined to be the second bank, and the lower address area excluding the upper address from all addresses is the ROM and the RAM. An information processing device, characterized in that it is different for and. 2. Each bit of the first bank has the same value, each bit of the second bank has a value obtained by inverting the same value, and the bank decoding circuit (16) includes 2. The information processing apparatus according to claim 1, wherein it is determined to be the first bank or the second bank based on the output of the AND gate (21A) or the NOR gate (22A) supplied with. 3. The address discrimination circuit according to claim 1, wherein the bank is the second bank, and the lower address is outside the lower address area of the RAM (13). 35), an address conversion circuit (32) for converting the lower address to a lower address of the ROM (12) outside the lower address area of the RAM, and the address when the determination is made. A selector (31) for selecting the output of the conversion circuit and selecting the lower address when the determination is not made, and outputting the output selected by the selector to the lower address of the ROM and the RAM. An information processing device characterized by being used for specifying. 4. A microprocessor unit comprising the information processing apparatus according to claim 1 integrated into one chip.