JPH07122781A - Manufacture of led array - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing an excel lent LED array provided with an insulating film of few pinholes. CONSTITUTION:An alumina film 14 is formed on an N-type semiconductor substrate 10, and a first operating 15 is provided to the alumina film 14. Zinc is selectively diffused into the N-type semiconductor substrate 10 provided with the first opening 15 to form a P-type diffusion region 12, and a second insulating film 19 as a second layer is formed on the N-type semiconductor substrate 10 provided with the first opening 15. At this point, the second insulating film 19 is selectively etched to form a second opening 21 corresponding to the first opening 15. Then, a wiring layer 20 is formed on the second insulating film 19 provided with the second opening 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an LED array.

[0002]

2. Description of the Related Art When manufacturing an LED array, a light emitting diode (LE) is formed between a semiconductor substrate of the first conductivity type and the substrate.
It is necessary to form a large number of second conductivity type impurity diffusion regions forming a pn junction for D) in an array. In that case, an insulating film having an array of openings is used as a diffusion preventing film having a function of exposing the portion of the substrate where the p-type impurity diffusion region is formed and covering the other portion, and the impurity diffusion is performed. As a conventional example of a method for manufacturing an LED array including such an impurity diffusion step, there are those disclosed in Documents I and II (Document I: Japanese Patent Laid-Open No. 56-30776).
"Manufacturing Method of Light-Emitting Element Array", Reference II: "Development of Zn Selective Diffusion Technology Using Plasma CVD SiO _X N _Y Film", Oki Electric Research & Development, No. 128, Vol. 52, N
o. 4, October 1985, PP 104-110).

FIG. 7 shows a conventional L disclosed in Document I.
One LE in the sample in the process of forming the ED array
A portion D (this portion is referred to as an array element portion) is shown.

In the LED array manufacturing method disclosed in Document I, Zn is used as a P-type impurity when selectively forming a large number of P-type diffusion regions 32 on the N-type semiconductor substrate 30, and diffusion is prevented at that time. An alumina (Al ₂ O ₃ ) film 34 having an opening is used as a film, and a SiO ₂ film 36 is used as a mask for low-concentration diffusion. The alumina film 34 has a property of slowing down the zinc diffusion rate when the P-type diffusion region 32 is formed by zinc diffusion. Therefore, the alumina film 34 has a function of suppressing lateral diffusion of the P-type diffusion region. Further, since the alumina film 34 can make the bottom surface of the P-type diffusion region 32 flat,
It has been reported that ED arrays can be densely packed. In addition, the SiO ₂ film 36 which is a mask for low-concentration diffusion
Are generally removed in a later step in the LED array forming process (see Reference III: “Solid-state Light-Emitting Devices and Their Applications”, Industry Bulletin, 1971, P80).

FIG. 8 shows an example of the LED array element portion in the process of forming the conventional LED array disclosed in Document II.

In the method of manufacturing an LED array disclosed in Document II, silicon having an opening 43 as a diffusion preventing film for P type impurities when a large number of P type diffusion regions 42 are selectively formed in an N type semiconductor substrate 40. A laminated film of a nitride film 44 and a SiON film 46 having an opening 45 is used. The P-type diffusion region 42 is formed by diffusing zinc as in the case of FIG. 7. In addition, the manufacturing method from the conventional LED array element portion of FIG. 7 and FIG.
Since it is disclosed in Document III, detailed description is omitted here.

In each of the above-mentioned documents I to II,
Although illustration is omitted, the alumina film 3 which is a diffusion preventing film
4 and the SiON film 46 are used as they are as an interlayer insulating film, and one end of the film 34 or 46 is p-type.
A wiring layer connected to the type diffusion region 32 (42) is formed.

[0008]

However, the LED array manufacturing methods disclosed in the above-mentioned Documents I and II have the following problems.

According to the method of Document I, the insulating film (Al ₂ O ₃ film) 34 formed on the N-type semiconductor substrate 30 is only one layer (the SiO ₂ film 36 is formed in the later step as described above). Removed). Therefore, when there is a pinhole in the alumina film 34 of the conventional LED array element portion, the wiring layer (not shown) formed in the alumina film 34 and the N-type semiconductor substrate 30 are connected via the pinhole. It is electrically connected and causes a short circuit. Therefore, even when a signal is applied between the electrodes formed on the upper surface and the lower surface of the substrate 30, dots that do not emit light are generated in the elements of the LED array. Further, when the P-type diffusion region 32 is formed on the lower surface of the pinhole, light is emitted also from the pinhole portion, and there is a problem that a regular amount of emitted light cannot be obtained. As described above, there is a problem that it is difficult to uniformly form a pinhole-free film on the N-type semiconductor substrate 30 with only one layer of the alumina film 34.

In the method of Document II (an example in which two layers of a silicon nitride film (SiN film) 44 and a SiON film 46 are used as an insulating film), the number of insulating films is two, so that the problem of pinholes is reduced. It is thought that it can be done, but I think that the cause of pinholes is still inherent. The factors are as follows. SiO used as the upper layer
The internal stress of the N film 46 is larger than that of the silicon nitride film (SiN film) or the alumina film (Al ₂ O ₃ film), and therefore cracks are likely to occur. Further, pinholes are generated due to flakes or the like when the insulating film is formed (see FIG. 6A). Therefore, as shown in FIG.
It is considered that the pinhole defect 50a is likely to occur also in the resist pattern 48 formed as a mask for forming the openings 45 and 43 in the film 46 and the SiN film 44. Therefore, the openings 45, 43 are formed in the SiON film 46 and the SiN film 44.
In the etching for forming the pinhole 50b
And the pinhole 50c is generated in the SiN film 44 which is the lower layer through the pinhole 50.
For this reason, the wiring layer of the Al thin film and the N-type semiconductor substrate 40 are short-circuited as in the method of the above-mentioned document I, and a light emission defect occurs in the element portion of the LED array.

This application has been made in view of the above-mentioned problems, and an object of each invention of this application is to provide a method capable of manufacturing an excellent LED array having an insulating film with few pinholes. It is in.

[0012]

In order to achieve this object, according to the first invention of this application, an N-type semiconductor substrate,
A plurality of P-type diffusion regions provided on the N-type semiconductor substrate,
An LED including an insulating film having an opening exposing the P-type diffusion region, and a wiring layer having one end connected to a part of the P-type diffusion region and extending over the insulating film. In manufacturing the array, (a) an alumina film (Al ₂ O) is formed as a first layer portion of the insulating film on an N-type semiconductor substrate.
₃ film), (b) forming a first opening in the alumina film, and (c) selectively diffusing zinc (Zn) into the N-type semiconductor substrate in which the opening has been formed. And (d) forming a second insulating film as a second layer portion of the insulating film on the N-type semiconductor substrate on which the first opening has been formed, and selectively etching the second insulating film. Forming a second opening corresponding to the first opening in the second insulating film (provided that the second insulating film and its etching means selectively apply the second insulating film to the alumina film). And (e) a step of forming the wiring layer on the second insulating film in which the second opening has been formed, and a method of manufacturing the LED array.

In carrying out the first invention, the etching means for the second insulating film is dry etching, and the second insulating film is one kind selected from a silicon nitride film (SiN film), a silicon oxide film and a SiON film. A film or a laminated film is preferable.

Further, in implementing the present invention, a diffusion protection film is formed on the entire surface of the N-type semiconductor substrate on which the first opening has been formed, and the zinc is selectively diffused with the diffusion protection film formed. Is preferred.

In order to achieve this object, according to the second invention of this application, an N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, and the P-type diffusion region are provided. An LED array is manufactured that includes an insulating film having an opening that exposes a region, and a wiring layer that has one end connected to a part of the P-type diffusion region and that extends over the insulating film. (I) forming an alumina film (Al ₂ O ₃ film) as a first layer portion of the insulating film on the N-type semiconductor substrate, and (ii) forming a first opening in the alumina film. (Iii) a step of forming a PSG film on the N-type semiconductor substrate on which the first opening has been formed, and (iv) the PSG film.
With the film formed, zinc (Z
n) selectively diffusing, and (V) forming a second alumina film as a second layer portion of the insulating film on the PSG film of the sample in which the diffusion of zinc has been completed, v
i) selectively etching the second alumina film with hot phosphoric acid to form a second opening corresponding to the first opening in the second insulating film, and (vii) the second opening. A step of selectively etching the PSG film portion exposed by forming the opening using buffer hydrofluoric acid to form a third opening in the PSG film; and (viii) a sample in which the third opening has been formed. And forming the wiring layer on the second alumina film.

[0016]

According to the configuration of the first invention of this application described above,
The Zn diffusion preventing film at the time of forming the P type diffusion region and the insulating film serving as an interlayer insulating film between the subsequent wiring layer and the N type semiconductor substrate are composed of a laminated film of an alumina film and a predetermined second insulating film. It The alumina film plays a role of suppressing lateral diffusion of Zn. In addition, since the second insulating film is a material that is selectively etched compared to the alumina film, the alumina film is substantially removed when the second insulating film is etched to form the second opening in the second insulating film. It can be said that it is not etched. This means that even if a pinhole exists in the second insulating film, the alumina film is not substantially etched through this pinhole. That is, it can be said that when the opening is formed in the second insulating film, the pinhole is not continuously formed from the second insulating film to the alumina film due to the pinhole in the second insulating film. Further, it can be said that even if pinholes are formed in the alumina film and the second insulating film at the time of forming each film, the probability that the pinholes in both films overlap with each other is very low. From these facts, according to the method of the first invention, an insulating film with few pinholes can be obtained as a result.

Further, in the structure using the diffusion protection film, it is possible to prevent, for example, phosphorus or arsenic from coming out from the compound semiconductor generally used as the N-type semiconductor substrate.

According to the structure of the second invention, since the PSG film is not etched by the etchant (hot phosphoric acid) that etches the second alumina film, the lower alumina film is etched by the second alumina film. At the time of, it is protected by the PSG film. Therefore, even if a pinhole is formed in the second alumina film, the pinhole is not connected to the lower alumina film through this pinhole. Therefore, like the first invention, an insulating film with few pinholes can be obtained. Further, the alumina film is a SiN film, a Si
Since the film stress is smaller than that of the ON film and the SiO ₂ film, it can be said that the second invention is less likely to cause a defect due to the film stress than the first invention.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an LED array according to the present invention will be described below with reference to the drawings. It should be noted that the drawings merely schematically show the shapes, sizes, and arrangements of the respective constituent components to the extent that the present invention can be understood. Prior to the method of manufacturing the LED array, the structure of the LED array of the present invention will be briefly described.

FIG. 1A is a plan view schematically showing the structure of the LED array of the present invention, and FIG.
It shows a cross-sectional view when cut along the line A.

First, the LED array of the first embodiment of the present invention will be described with reference to FIGS. 1 (A) and 1 (B). In addition, here, one element of the LED array is LE
It is called a D array element section. The LED array element portion of the present invention includes an N-type semiconductor substrate 10 (for example, an N-type GaAsP substrate) and a plurality of P-type diffusion regions 12 on the N-type GaAsP substrate 10. Furthermore, the N-type GaAsP substrate 10
As the alumina (Al ₂ O ₃ ) film 14 having the first opening 15 on which the P-type diffusion region 12 is exposed and the second insulating film,
The PSG film 16 having the third opening 27 and the silicon nitride film (SiN film) 18 having the second opening 21 are laminated. Here, the alumina film 14 and the PSG film 1
6 and the silicon nitride film 18 are collectively referred to as an insulating film 23.

Further, the alumina film 1 is formed from the P-type diffusion region 12
4, a lead portion 20a is provided on the surface of the substrate 10 along the end portions of the PSG film 16 and the silicon nitride film 18. The lead portion 20a has one end face fixed to the P-type diffusion region 12 and the other end face bonded to the bonding pad 20.
It is electrically coupled to b. Then, the drawer portion 20a
And the bonding pad 20b form the wiring layer 20.

On the other hand, on the back surface of the substrate 10, an AuGeNi film 22 and an Au film 24 which will be N-type electrodes are laminated. The AuGeNi film 22 and the Au film 24 are collectively referred to as a lower wiring layer 25.

Next, L of a modification of the first embodiment of the present invention.
The structure of the ED array is shown in FIG.

The structure of a modification of the first embodiment of the present invention is as follows:
The insulating film 19 provided on the N-type GaAsP substrate 10 is used as the alumina film 14 and the second insulating film, and the silicon nitride film 19 is formed.
It has a two-layer structure in which and are laminated. The other structure is similar to that of the first embodiment, and thus the description thereof is omitted.

Next, a method of manufacturing the LED array of the first embodiment of the present invention will be described with reference to FIGS. 3A, 3B and 3C, 4A, 4B and 4C. And FIG.
The description will be made with reference to (A) and (B).

N-type GaAsP as N-type semiconductor substrate 10
A substrate (hereinafter referred to as a substrate) is used. This board 10
Prior to forming the film, the substrate 10 is first washed with an arbitrary suitable cleaning liquid to remove stains on the surface of the substrate 10, and then the substrate 10 is dried.

An alumina (Al ₂ O ₃ ) film 14 is formed on the substrate 10 by using, for example, a sputtering method (FIG. 3A). At this time, the film thickness of the alumina (Al ₂ O ₃ ) film 14 is, eg, 2000 A ° to 3000 A ° (the symbol of A ° represents Angstrom).

Next, a first opening 15 for forming a diffusion region of zinc is formed in the alumina (Al ₂ O ₃ ) film 14 by using the photolithography method (FIG. 3B). As an etching condition for forming the opening in the alumina film 14, hot phosphoric acid is used as an etching solution, and an etching process is performed for 2 minutes in a temperature range of 80 ° C. to 85 ° C.

Next, PS is formed on the alumina (Al ₂ O ₃ ) film 14 having the first opening 15 by using, for example, the CVD method.
The G film 16 is formed. The film thickness of the PSG film 16 is 100
A ° to 200 A °. The PSG film 16 is preferably formed so that the refractive index of the film thickness is about 1.4. Then, zinc (Zn) is selectively diffused in the substrate 10 in which the first opening 15 is formed to form the P-type diffusion region 12 (C in FIG. 3). The PSG film 16 plays a role of preventing evaporation of gallium (Ga) and arsenic (As) atoms when zinc is diffused. When zinc is diffused, either an open tube method or a sealed tube method may be used as the diffusion furnace, and the diffusion conditions are preferably a heating temperature of 700 ° C. in the sealed tube method. The temperature is set in the range of up to 800 ° C. and the treatment is performed for 6 hours. At this time, since the alumina film 14 is formed on the substrate 10, the P
Lateral diffusion of the shape diffusion region 12 can be suppressed.

Next, the structure of FIG. 3C is washed and dried by any suitable method, and then the substrate 10 on which the first opening 15 is formed is formed by using, for example, the plasma CVD method.
A second insulating film (for example, a silicon nitride film (SiN film)) 18 is formed thereon as a second layer portion of the insulating film 23 (FIG. 4).
(A)).

The film thickness of the silicon nitride film (SiN film) 18 is about 1000 A °.

Next, a second opening 21 is formed in the silicon nitride film 18 at a portion corresponding to the first opening 15 by photolithography (FIG. 4B). A dry etching method is used for etching the silicon nitride film 18 at this time.

The silicon nitride film 18 is the alumina film 1
4 and the PSG film 16 are made of a material having a higher etching rate, the alumina film 14 and the PSG film 16 are not etched even if the silicon nitride film 18 is etched. When dry etching is used, a SiON film may be used instead of the SiN film 18 as the second insulating film. However, when the SiON film is used, the internal stress of the film is large, so that the substrate may be warped, so that it is necessary to pay sufficient attention to the film forming conditions.

Further, it is desirable that the length L ₂ of the second opening 21 of the silicon nitride film be larger than the length L ₁ of the first opening 15 of the alumina film described above. The reason for this will be described later. Further, for example, an arbitrary suitable resist pattern (not shown) is formed on the silicon nitride film 18 as an etching mask and etching is performed. At this time, plasma etching is used as an etching method for the silicon nitride film 18. The plasma etching conditions at this time are
It is as follows.

Etching gas: carbon tetrafluoride (CF ₄ ) gas + oxygen (O ₂ ) gas RF frequency: 13.56 MHz Power: 250 W Etching time: about 2 minutes The silicon nitride film 18 is selectively etched under the above etching conditions. Although removed, the PSG film 16 and the alumina film 14 remain as they are without being removed.

Next, as an example of the second invention of the present invention, a second alumina film is used instead of the silicon nitride film.
Since the second alumina film has a smaller internal stress of the film than the silicon nitride film, the warp of the substrate 10 can be suppressed. Also in the case of the second alumina film, the length L ₂ of the second opening 21 is
Length L of the first opening 15 of the alumina film 14 in the first layer portion
_It should be larger than ₁ . Further, the second alumina film is etched by a wet etching method, for example, the second alumina film on the PSG film 16 is almost selectively etched by hot phosphoric acid. At this time, since the PSG film 16 remains without being etched, the alumina film 14 as the first layer portion is not etched.

FIGS. 6A and 6B are schematic views for explaining the occurrence of pinholes formed in the insulating film. 6B is a schematic diagram of the first embodiment, and FIG. 6A is a schematic diagram of a conventional example for comparison with the present invention. As described above, in the conventional example, when the pinholes 50a, 50b and 50c are formed in the resist pattern 48, the SiON film 46 and the SiN film 44, the silicon nitride film 4 is formed when the openings 43 and 45 are formed.
4 and the SiON film 46 are almost equal in etching rate, the SiON film 46 is etched through the pin holes of the resist pattern 48, and further the silicon nitride film 44 on the lower surface is etched. Resist pattern 4
8 of the pinhole 50a and the SiON film 46 of the pinhole 5
When 0b overlaps, it is considered that the pinhole penetrates the silicon nitride film 44 and reaches the substrate 10. On the other hand, in the embodiment of the present invention, even if the resist pattern 48, the silicon nitride film 19 and the alumina film 14 have pinholes 51a, 51b and 51c, the silicon nitride film 19 has an etching rate higher than that of the alumina film 14. Since it is large, the alumina film 14 is not etched. Therefore, even if the resist pattern 48 and the pinholes 51a and 51b in the silicon nitride film 19 overlap each other, the probability that the pinhole penetrates the alumina film 14 and reaches the substrate 10 is reduced.

Next, after the resist pattern is removed by any suitable method, the second opening 2 is formed by using, for example, buffered hydrofluoric acid using the silicon nitride film 18 as a mask.
The PSG film 16 formed under 1 is removed. At this time, the third opening 27 is formed in the PSG film 16.

Next, a preliminary film for wiring layer (not shown) is formed on the entire surface of the sample by using, for example, the EB vapor deposition method, and then the lead portion 2 from the P-type diffusion region is formed by the photolithography method.
0a is formed ((C) of FIG. 4). This drawer 20
a is an Al film and the film thickness is 1.5 μm to 2.5 μm. The lead portion 20a and the bonding pad (not shown) formed on the silicon nitride film are coupled to each other to form a wiring layer (see FIG. 1A).

A wet etching method is used for etching the lead portion 20a. At this time, the alumina film 14 is etched similarly to the lead portion 20a, but the PSG film 16 and the silicon nitride film 18 are not etched.

The second opening 2 of the silicon nitride film 18
The length L ₂ of ₁ is larger than the length l ₁ of the first opening 15 of the alumina film 14. Therefore, the drawer 2
It is possible to reduce the formation of voids due to over-etching of the portion of the alumina film 14 that is in close contact with 0a.

Next, after the back surface of the substrate 10 is polished by any suitable method, the AuGeNi film 22 for the N-type electrode is formed by using, for example, the EB evaporation method ((A) of FIG. 5). The film thickness of the AuGeNi film 22 for N-type electrode is 1000 A °.
˜2000 A °.

Further, an Au film 24 is formed on the AuGeNi film 22 by the EB vapor deposition method (FIG. 5B).
The AuGeNi film 22 and the Au film 24 are collectively referred to as a lower wiring layer 25. The main structural portion of the LED array of the present invention is formed through the series of steps described above.

Next, a manufacturing method of a modified example of the first embodiment of the present invention will be described with reference to FIG.

After the step (C) of FIG. 3 of the first embodiment described above, the PSG film 16 is completely removed using any suitable method. After that, the LED array is formed in the same process as that of FIG. Therefore, detailed description is omitted. Thus, the insulating film 23 may have a two-layer structure of the alumina film 14 and the silicon nitride film 19.

As can be understood from the above description, in the present invention, since the number of pinholes generated in the insulating film 23 can be reduced by using different materials and changing the etching rate, the wiring layer 20 can be reduced. Thus, short-circuit defects of the substrate 10 are reduced and the product yield is improved.
According to the experimental results of the present inventors, the conventional yield is 70%.
% To 80%, the yield of the present invention is 10
A result close to 0% is obtained. Therefore, it was found that the LED array formed according to the embodiment of the present invention can provide a high-quality LED array with high yield.

Further, according to the present invention, since the alumina film is provided as the first layer portion on the N-type semiconductor substrate, the conventional excellent property, that is, the lateral diffusion of the P-type diffusion region can be suppressed. There is also an advantage that it can be inherited as it is.

Further, according to the present invention, since the alumina film or the silicon nitride film having a small internal stress is laminated on the N-type semiconductor substrate, the warp of the substrate can be reduced as compared with the conventional SiON film or SiO ₂ film. There is also.

[0050]

As is apparent from the above description, according to the LED array manufacturing method of the first and second inventions of this application, an insulating film that can be used as both a diffusion preventing film and an interlayer insulating film is provided. An insulating film having the characteristic of suppressing the lateral diffusion of Zn contained in the alumina film and having fewer pinholes than in the past can be obtained. Therefore, since the lateral diffusion of Zn can be prevented, an LED array in which each LED has a high light emission intensity and a high density can be obtained, and since the pinholes are smaller than before, short circuit between the substrate and the wiring layer due to the pinholes and Can prevent short circuit between rods. In addition, since the number of pinholes is small and the light emission loss can be reduced, the light emission efficiency is improved.

[0051] In the configuration of the second invention, the alumina film, since the SiN film, SiON film or the film stress is small compared to the SiO ₂ film, SiN film as the second insulating film, when using a SiON film or SiO ₂ film Wafer warpage is less likely to occur than in. Therefore, it is expected that the characteristic deterioration of the LED array due to the warp of the wafer can be reduced.

[Brief description of drawings]

FIG. 1A is a plan view of an LED array of a first embodiment of the present invention, and FIG. 1B is a sectional view taken along the line AA.

[0052]

FIG. 2 is a structural cross-sectional view of an LED array used for explaining a modification of the first embodiment of the present invention.

[0053]

3 (A) to (C) are manufacturing process diagrams provided for explaining a manufacturing method of a first embodiment of the present invention.

[0054]

4 (A) to 4 (C) are manufacturing process diagrams provided for explaining the manufacturing method of the first embodiment of the present invention following FIG.

[0055]

5 (A) and 5 (B) are manufacturing process diagrams provided for explaining the manufacturing method of the first embodiment of the present invention, following FIG.

[0056]

FIG. 6 (A) is a schematic view for explaining the generation of pinholes formed in a conventional insulating film, and FIG. 6 (B) shows the generation of pinholes according to the first embodiment of the present invention. It is a schematic diagram for explaining.

[0057]

FIG. 7 is a cross-sectional view for explaining the structure of a conventional LED array element section.

[0058]

FIG. 8 is a cross-sectional view illustrating a structure of a conventional LED array element portion.

[0059]

[Explanation of symbols]

 10: N-type GaAsP substrate 12: P-type diffusion region 14: Alumina film 15: First opening 16: PSG film 18, 19: Second insulating film 20a: Lead-out part from P-type diffusion region 20b: Wire bonding pad 20 : Wiring layer 21: Second opening 22: AuGeNi film 23: Insulating film 24: Au film 25: Lower wiring layer 27: Third opening

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masumi Yanaka 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. An N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, an insulating film having an opening exposing the P-type diffusion region, and the P-type diffusion region. In manufacturing an LED array comprising a wiring layer, one end of which is connected to one end, extending over the insulating film, (a) a first layer of the insulating film on an N-type semiconductor substrate A step of forming an alumina film (Al ₂ O ₃ film) as a portion, (b) a step of forming a first opening in the alumina film, and (c) zinc on the N-type semiconductor substrate in which the opening has been formed. (D) selectively diffusing (Zn), and (d) forming a second insulating film as a second layer portion of the insulating film on the N-type semiconductor substrate on which the first opening has been formed, A second opening corresponding to the first opening is formed in the second insulating film by selectively etching the insulating film. (Wherein the second insulating film and its etching means are materials and means for selectively etching the second insulating film with respect to the alumina film), (e) the second opening. And a step of forming the wiring layer on the formed second insulating film. 2. The LED array manufacturing method according to claim 1, wherein the etching means for the second insulating film is dry etching, and the second insulating film is a silicon nitride film (SiN film), a silicon oxide film, and a SiON film. A method for manufacturing an LED array, which comprises one kind of film selected from the films or a laminated film. 3. The method of manufacturing an LED array according to claim 1, wherein a diffusion protective film is formed on the entire surface of the N-type semiconductor substrate on which the first opening has been formed, and the diffusion protective film is formed. A method for manufacturing an LED array, which comprises performing the selective diffusion of zinc. 4. An N-type semiconductor substrate, a plurality of P-type diffusion regions provided in the N-type semiconductor substrate, an insulating film having an opening exposing the P-type diffusion region, and the P-type diffusion region. In manufacturing an LED array comprising a wiring layer, one end of which is connected to one end, extending over the insulating film, (i) a first layer of the insulating film on an N-type semiconductor substrate. A step of forming an alumina film (Al ₂ O ₃ film) as a portion, (ii) a step of forming a first opening in the alumina film, and (iii) the N-type semiconductor substrate on which the first opening has been formed A step of forming a PSG film thereon, (iv) a step of selectively diffusing zinc (Zn) into the N-type semiconductor substrate in a state where the PSG film is formed, (v) termination of diffusion of the zinc Second alumina film as the second layer portion of the insulating film on the PSG film of the prepared sample And (vi) selectively etching the second alumina film with hot phosphoric acid to form a second opening corresponding to the first opening in the second insulating film. , (Vii) PSG exposed by forming the second opening
A step of selectively etching the film portion with buffer hydrofluoric acid to form a third opening in the PSG film; and (viii) the wiring layer on the second alumina film of the sample in which the third opening has been formed. And a step of forming the LED array.