JPH07128400A - Self-inspection equipment for semiconductor device - Google Patents

Abstract

PURPOSE:To provide a self-inspection equipment for semiconductor device in which the inspection data is reduced while preventing the area of semiconductor device from increasing. CONSTITUTION:The self-inspection equipment comprises an internal logic circuit 1 and an inspection circuit 7 wherein the inspection circuit 7 comprises a timing adjusting circuit 3 and an inspection data generating circuit 4. The inspection circuit 7 receives an output value from the internal logic circuit 1 and generates an inspection data for the internal logic circuit 1 based on the received output value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device self-inspection apparatus.

[0002]

2. Description of the Related Art In recent semiconductor devices, the scale and density have been increased, and the inspection amount for inspecting the semiconductor devices has become enormous, which requires a considerable amount of time and a lot of cost. As a means for solving this problem, there is an LSI self-inspection system disclosed in Japanese Patent Laid-Open No. 60-68624, which discloses a device as shown in FIG.

In FIG. 6, reference numeral 60 is a pseudo-random number generation circuit for generating an inspection pattern by using a binary counter or a linear feedback shift register (LFSR), 61 is an inspected circuit, and 62 is a response sequence from the inspected circuit 61. This is a judgment circuit that judges whether the received signal is normal or abnormal. The determination circuit 62 includes a compression circuit 63 for compressing the response sequence from the circuit under test 61, a reference value generator 64 for generating a reference value calculated in advance, and a result and reference value compressed by the compression circuit 63. Comparator 65 for comparing and judging normality / abnormality
It consists of

In the circuit of this configuration, a test pattern for testing is generated by the pseudo random number generation circuit 60, input to the circuit under test 61, and judged by the judgment circuit 62, so that a large amount of data can be generated at high speed. It is generated by the pseudo random number generation circuit 60 and self-inspected.

[0005]

However, in the conventional LSI self-inspection method described above, although a large amount of data can be generated at high speed by the pseudo-random number generation circuit 60 to perform self-inspection, an inspection pattern is generated. Since it is necessary to incorporate both the pseudo random number generation circuit 60 and the judgment circuit for compressing / deciding the inspection result, the overhead of the entire inspection circuit becomes large and the area of the semiconductor device increases, There is a drawback that the amount of data is large and the inspection takes time.

Therefore, an object of the present invention is to provide a semiconductor device self-inspection apparatus capable of preventing an increase in the area of the semiconductor device and reducing the inspection time by reducing the inspection data. .

[0007]

In order to achieve the above object, the present invention is a self-inspecting apparatus for self-inspecting a semiconductor device, which is an inspected circuit to be inspected and an output of the inspected circuit. And an inspection circuit that generates inspection data to be input to the circuit to be inspected based on the output of the circuit to be inspected.

Further, the present invention according to claim 2 provides the inspection circuit according to claim 1, wherein the inspection circuit generates pseudo-random inspection data for inspecting the circuit to be inspected. And a timing adjusting circuit for outputting the output from the circuit to be inspected to the inspection data generating unit at regular intervals.

[0009]

According to the self-inspecting apparatus for a semiconductor device of the present invention having the above structure, the output of the circuit under test is input to the circuit under test, and the test data to be input to the circuit under test is generated based on the output of the circuit under test. ing. That is, the inspection circuit automatically generates inspection data, the inspection data is input to the circuit to be inspected, and output based on this inspection data. Then, the output is inspected by the inspection circuit and the next inspection data is automatically generated, so that the self-inspection can be performed.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of a semiconductor device self-inspection apparatus. As shown in FIG. 1, the self-testing apparatus for a semiconductor device receives an internal logic circuit 1 which is a circuit to be tested, an output value of the internal logic circuit 1, and outputs test data to the internal logic circuit 1. And an inspection circuit 7 for outputting. The inspection circuit 7 is composed of a timing adjustment circuit 3 and an inspection data generation circuit 4, and a specific configuration of each will be described below with reference to the drawings.

FIG. 2 shows a specific example of the circuit under test 1
An example of a hexadecimal 16-bit multiplier 200 is shown. In FIG. 2, signal lines AI _{00 to} AI ₁₅ and BI _{00 to} BI ₁₅ are binary 16-bit inputs a and b, respectively, and the control line MUL is “HIGH” through the enables 210 to 241.
When it becomes, the value of the 32 pit internal bus 202 is fetched.

The signal lines OUT _{00 to} OUT ₃₁ are binary 32-bit outputs, and the operation result of a × b is output through the 32-bit signal lines OUT _{00 to} OUT ₃₁ . Signal line OUT
_{00 to} OUT ₃₁ are connected to enables 250 to 281. The enables 250 to 281 are connected to the 32 pit internal bus 201, and the signal line MUL is "HIG.
When it becomes “H”, the values of the 32-bit outputs OUT _{00 to} OUT ₃₁ are output to the 32-pit internal bus 201.

FIG. 3 is a diagram showing an example of the configuration of the timing adjustment circuit 3. In FIG. 3, signal lines D _{00 to} D ₃₁
Is connected to the 32-pit internal bus 201. The selectors 300 to 331 operate as shift registers that output the values of the signal lines D _{00 to} D ₃₁ when the signal line SEL is “LOW” and output the logical values of the flip-flops 350 to 380 when the signal line SEL is “HIGH”. The signal line SCAN-IN is
It is connected to an inspection ROM (not shown) or an external input line (not shown), and inputs an initial value required for inspection through the selector 300. The flip-flop 381 is
The signal line SCAN-OUT is connected to the signal line SCAN-OUT, which is connected to an inspection result determination circuit (not shown). The signal lines Q of the flip-flops 350 to 381 are connected to the signal lines E _{00 to} E ₃₁ .

FIG. 4 shows an example of the configuration of the inspection data generating circuit 4.
FIG. In FIG. 4, the signal line EI₀₀~ EI₃₁
Is an input to the inspection data generation circuit 4, and is shown in FIG.
E₀₀~ E₃₁It is connected to the. Signal line A₀₀~ A₁₅, B
₀₀~ B₁₅Is the output, and the 32 pit internal bus 20 in FIG.
Connected to 2. Signal line EI ₀₀~ EI₃₁Is the signal line
400-431 are connected only by the black dots in the figure,
Lines 400-430 through inverters 450-480
Signal line A₀₀~ A₁₅, B₀₀~ B₁₄It is connected to the. Line number
Line 431 is signal line B₁₅It is connected to the.

Next, the operation of the above configuration will be described based on a timing chart showing a series of inspection operations after the start of inspection shown in FIG. First, the signal line SEL shown in FIG. 3 is fixed to “HIGH” so that the timing adjustment circuit 3 operates as a shift register. A clock signal is supplied to the control line CLK from an inspection ROM (not shown), and flip-flops 350 to 379 are supplied from the signal line SCAN-IN.
Input 0 to 381 and 1 to 380.

Then, the control line MUL in FIG.
H ”and the SEL signal in FIG. 3 is 0, the 16-bit multiplier 20 is transmitted via the 32-pit internal buses 201 and 202.
0 and timing adjustment circuit 3 and inspection data generation circuit 4
Simultaneously with the connection of and, the initial value obtained by the scan-in is output from the signal lines E _{00 to} E _{31 of} FIG. 3 and the first stage inspection is executed. The inspection signal output from the signal lines E _{00 to} E ₃₁ is 32 through the signal lines A _{00 to} A ₁₅ and B _{00 to} B ₁₅ in FIG.
Is output to the pit internal bus 202, a × b = HexFF through the 32 pit internal bus 202 in _{AI 00 ~AI 15, BI 00 ~BI} 15 input to the 16-bit multiplier 200.
The operation of FF × HexFFFF is executed.

Then, the 16-bit multiplier 200 is positive
If it is always OUT of FIG.₀₀~ OUT₃₁To HexFFF
E0001 is through 32 pit internal bus 201
Signal line D₀₀~ D₃₁Be fed back to. In addition, here
HexFFFF is a hexadecimal FFFF. And
HexFFF when the control line CLK in FIG. 3 becomes "HIGH"
E0001 through flip-flops 350-381
Signal line E₀₀~ E₃₁Output to the second stage inspection from this value
A vector is generated. Signal line E₀₀~ E₃₁Is output from
The value HexFFFE0001 is the same as the check vector in the first stage.
The signal line EI of FIG.₀₀~ EI ₃₁Input to the inspection circuit
And the signal line A as the inspection vector of the second stage₀₀~ A₁₅Or
Hex00FF, B₀₀~ B₁₅Output from Hex81FE
To be done.

The above procedure is applied to the binary 16-bit multiplier 200.
Repeat until all stuck-at failures and open failures are detected. Table 1 shows the relationship between the number of inspection stages and the number of undetected faults in the binary 16-bit multiplier 200. In the present embodiment, all the failures can be detected at the 26th inspection stage. Therefore, in FIG. 3, after the clock of the 26th stage rises from the start of the inspection, the inspection result (if the circuit is normal,
Hex118D9E1C) is incorporated in the flip-flop of FIG. 3, the control line SEL of FIG. 3 is set to “HIGH” to operate the timing adjustment circuit in the shift register, and the signal line SC
The inspection result signal is scanned out from the AN-OUT and taken out, and the judgment circuit (not shown) compares it with the expected value at the normal time to judge the correctness of the circuit.

By using the inspection mechanism shown in FIG.
Input _{AI 00 ~AI 15, BI 00 ~BI} 15 that pseudo-random number is generated in the in the test circuit, for example, the correlation coefficient next stage each other C are represented as the following equation,

[0020]

[Equation 1]

[0021]

[0022]

## EQU2 ## r = x ₁ x ₂ + x ₂ x ₃ + ... + x _n-1 x _n +
x _n x ₁

[0023]

[Formula 3] s ₁ = x ₁ + x ₂ + ... + x _n

[0024]

S ₂ = x ₁ ² + x ₂ ² + ... + x _n ² This correlation coefficient C is C = 0.08≈0.0 (n = 50
It can be confirmed from 0). Here, n is the number of inspection steps, and x _i is a hexadecimal representation of AI _{00 to} AI ₁₅ and BI _{00 to} BI ₁₅ as one logical value, and Hex00000000 to Fx
FFFFFFF is a value normalized to 0.0 to 1.0.

Therefore, according to the semiconductor device self-inspection apparatus having the above-described configuration, the output (c) from the circuit under test 1 in FIG. 1 is used as the input (d) to the inspection circuit, and this signal (d) is output.
By generating the pseudo random number for inspection (a) in the next stage from the pseudo random number generation circuit, the pseudo random number generation circuit also serves as the output data compression circuit required in the conventional self-inspection apparatus for semiconductor devices. Compared with the above, there is an effect that the inspection circuit is simplified and the increase in the area of the semiconductor device is small.

At this time, the test circuit 7 is constructed so that the input to the circuit under test 1 is a pseudo random number, and if the test is performed by this test circuit 7, the test series input to each input terminal of the circuit under test 1 is tested. Since a combination of 0 and 1 appears randomly, it becomes easy to detect an arbitrary stack (degeneration) fault or open fault in the internal logic circuit 1, and the fault detection rate becomes high.

Also, in the i-th stage inspection step,
Failure is detected and the inspection result is different from normal (c)_i
Is output to, it is generated based on this i-th stage inspection result.
I + 1th inspection input (a)_{i + 1}Is also different from normal
After that, the inspection input of the i + 2th and i + 3th stage
(A)_{i + 2}, (A)_{i + 3},,, and inspection result (c)
_{i + 2}, (C)_{i + 3}, ... are different from normal one after another
Therefore, after the appropriate inspection stage, for example, the kth stage,
Inspection result (c) output from circuit 1_kTake out only
By observing, the correctness of the circuit under test 1 can be judged,
The inspection can be easily performed.

Since it is impossible to predict the output of the next stage in the pseudo-random number system, it can be considered that there is no correlation between the inspection data of each stage. Even if different inspection signals are output once, they can be restored to normal signals. The probability that it will return and become indistinguishable (error-missing probability) will decrease, and reliability will be high. The present system has the above-mentioned features, which makes it possible to automatically and easily test the internal logic circuit of the semiconductor device with high reliability.

[0029]

[Table 1]

[Second Embodiment] In the first embodiment described above.
Is set to the initial value by the timing adjustment circuit shown in FIG.
I scanned in, but the timing adjustment circuit shown in Figure 7
You may use. In FIG. 7, 700 to 731 are enable
Signal line when the control line EN becomes "HIGH"
D₀₀~ D₃₁Value of signal line E₀₀~ E₃₁Output to. In addition,
Signal line D₀₀~ D ₃₁And signal line E₀₀~ E₃₁Is shown in Figure 3.
Signal line D₀₀~ D₃₁And signal line E₀₀~ E₃₁Corresponds to
It

In this configuration, the initial value may be directly input from the internal bus, and the final inspection result may be directly input from the internal bus to the inspection result judging circuit (not shown).

[0032]

According to the semiconductor device inspection apparatus of the present invention having the above-described configuration, the output of the circuit under test is input to the circuit under test, and the test data to be input to the circuit under test is generated based on the output of the circuit under test. is doing. By inputting the inspection data generated by the inspection circuit to the inspected circuit and inspecting the inspected circuit based on this inspection data, the dedicated pseudo random number generation circuit is not required and the area of the semiconductor device is reduced. There is an effect that can be. Further, there is an effect that the amount of inspection data can be small.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of a circuit under test.

FIG. 3 is a configuration diagram showing a timing adjustment circuit.

FIG. 4 is a configuration diagram showing an inspection data generation circuit.

FIG. 5 is a timing chart showing a series of inspection operations.

FIG. 6 is a diagram showing a conventional example.

FIG. 7 is a configuration diagram showing another timing adjustment circuit.

[Explanation of symbols]

 1 Internal logic circuit (circuit to be inspected) 2 Internal bus 3 Timing adjustment circuit 4 Inspection data generation circuit 7 Inspection circuit

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Claims (2)

[Claims] 1. A self-inspection apparatus for self-inspecting a semiconductor device, comprising: an inspected circuit to be inspected; and an output of the inspected circuit, and the inspected circuit based on the output of the inspected circuit. A semiconductor device self-inspection device comprising: an inspection circuit that generates inspection data to be input to the circuit. 2. The inspection circuit generates inspection pseudo random inspection data for inspecting the circuit to be inspected, and inputs the inspection data to the circuit to be inspected, and the circuit to be inspected. The self-inspection apparatus for semiconductor inspection according to claim 1, further comprising: a timing adjustment circuit that outputs the output of the above to the inspection data generating unit at a constant interval.