JPH07101947B2 - Sampling clock recovery circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to generation of a sampling clock of a device for sampling and encoding and transmitting a television signal, and particularly to a clock synchronized in phase with the sampling clock on the transmission side. It relates to a circuit reproduced on the receiving side.

(Prior Art) When encoding and transmitting a color television signal, when sampling is performed with a sampling clock synchronized with an input television signal,
It is necessary to recover the sampling clock on the receiving side. As a method of regenerating the sampling clock on the receiving side, there is a method of synchronizing the frequencies so that the number of sampling clocks in a fixed cycle is the same in both transmission and reception (for example, Japanese Patent Application No. 52-1176).
No. 13, "Sampling frequency synchronizer").

(Problems to be Solved by the Invention) In the conventional direction, only the frequencies of the sampling clock on the transmitting side and the sampling clock on the receiving side are made to match, and the phase relationship between both sampling clocks is synchronized. Not the way. Therefore, in the conventional method, when a television signal is coded and transmitted (the color burst phase of the television signal reproduced on the receiving side is delayed by the phase shift of the sampling clock with respect to the color burst phase of the input television signal on the transmitting side. Therefore, when the coded and transmitted signals are switched and edited to create a television signal, the phase of each color burst fluctuates with time.
In order to synchronize the phase of the color burst, another device for phase synchronization such as a frame synchronizer is required.

(Means for Solving the Problem) The sampling clock regenerating circuit of the present invention divides the first sampling clock by means for generating a first sampling clock phase-synchronized with the color subcarrier of the input television signal. Means for generating a first phase reference signal synchronized with the phase of the color subcarrier by means of frequency division, and means for sampling the first phase reference signal at fixed intervals obtained by dividing the transmission path clock Means for transmitting the sampled first phase reference signal by multiplexing it with the encoded information of the input television signal, and transmitting the second sampling clock reproduced on the receiving side. Means for generating the phase reference signal, the means for sampling the second phase reference signal for each frame period obtained by dividing the frequency of the transmission path clock reproduced on the receiving side, and the means for separating from the received signal. Got sampled Means for generating a phase difference signal representing the phase difference between the sampled first phase reference signal and the sampled second phase reference signal, and smoothing and outputting the phase difference signal; Means for generating a second sampling clock that is phase-locked with the first sampling clock in response to the phase difference signal.

(Example) Next, this invention is demonstrated with reference to drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this embodiment, an NTSC color television signal is A / D converted at a frequency three times as high as the subcarrier frequency f _SC and band compression encoded.
Transmit at a bit rate of 45 Mb / s, decrypt on the receiving side,
By performing D / A conversion with a sampling clock that is phase-synchronized with the sampling clock on the transmission side, the color burst phase of the reproduced color TV signal is synchronized with the color burst of the input TV signal on the transmission side. .

The NTSC color television signal input to the input terminal 1 is supplied to the A / D converter 2 and the clock generation circuit 3. The clock generation circuit 3 generates a first sampling clock whose frequency is 3f _SC and which is phase-locked with the color burst signal. Frequency divider circuit 5
Then, the clock is divided into 1/6 in synchronism with the phase of the subcarrier to generate the first phase reference signal that coincides with the cycle of an integral multiple of the subcarrier. By performing phase synchronization, the rising edge of the phase reference signal and the phase of the color subcarrier are synchronized.

The clock generation circuit 9 generates a 44.736 MHz clock, and the frequency division circuit 7 divides the frequency to 1/4760 corresponding to the cycle of the DS3 multiframe, and first divides the first of each multiframe.
The phase reference signal of is sampled, and the sampled value is multiplexed into a predetermined time slot of the DS3 multiframe. In other time slots, the video signal digitized by the A / D converter 2 is band-compressed and encoded by the encoder 4 and multiplexed with other necessary control signals and the like.
A U / B converted 44.736 Mb / s bipolar signal is output to the output terminal 10 on the transmission side.

The bipolar signal input to the input terminal 11 on the receiving side is guided to the separation circuit 12 and the clock recovery circuit 13. Upon receiving the bipolar signal, the clock recovery circuit 13 recovers the 44.736 MHz transmission path clock and supplies it to the separation circuit 12.

The separation circuit 12 B / U-converts the input signal, DMPX the DS3 frame, separates it into image data, control data, a first phase reference signal, and a pulse signal indicating the beginning of the DS3 frame, and sends it to each part. Supply.

The clock recovery circuit 21 recovers the second sampling clock. The frequency dividing circuit 19 frequency-divides the second sampling clock into 1/6, similarly to the transmitting side, to generate a second phase reference signal.
The sampling circuit 15 samples the second phase reference signal every DS3 frame period and supplies it to the phase comparison circuit 14.

The phase comparison circuit 14 performs a phase comparison between the sampled first phase reference signal supplied from the separation circuit 12 and the sampled second phase reference signal. The phase comparison is performed by exclusive OR of each binary signal. The phase comparison circuit 14 generates a phase comparison signal represented by a binary value of 0 or 1 by the phase comparison and outputs it to the smoothing circuit 18. The smoothing circuit 18 performs digital integration on the value of -1 when the phase comparison signal is 1 and -1 when the phase comparison signal is 0 to perform smoothing, and performs D / A conversion on the integrated value to perform smoothing. The converted phase comparison signal is supplied to the clock recovery circuit 21. Clock recovery circuit
Reference numeral 21 is provided with a voltage controlled oscillator, receives the smoothed phase comparison signal from the smoothing circuit 18, supplies the phase comparison signal to the voltage controlled oscillator as a control voltage, and outputs a first signal having a frequency corresponding to the control voltage. Generate 2 sampling clocks. Second
The sampling clock phase of is divided by the frequency divider circuit 19, sampling circuit 15
It is fed back to the phase comparison circuit 14 via. Finally, the first phase reference signal and the second phase reference signal are High
Or, it becomes balanced when the phase difference of 50% is averaged between the low level sections. Therefore, the first sampling clock and the second sampling clock are phase-synchronized.

The image data separated by the separation circuit 12 is supplied to the decoder 17. The decoder 17 decodes the image data to obtain a digital image.
Plays NTSC color TV signals. The D / A converter 20 performs D / A conversion on the digital NTSC color television signal to generate an analog television signal and outputs it to the output terminal 22.

In the embodiment shown in FIG. 1, the color burst signal is sampled in the A / D converter 2 in synchronization with the first sampling clock, and the color burst signal is converted into the first sampling clock in the D / A converter 20 on the receiving side. D / A using the second sampling clock phase-synchronized
Since they are converted, the color burst of the television signal input to the input terminal 1 and the color burst of the television signal output to the output terminal 22 can be relatively synchronized in phase.

As described above, according to the present invention, the color subcarrier and the first phase reference signal synchronized with the sampling clock are sampled and transmitted for every fixed sample of the transmission path clock. , The receiving side can synchronize the first sampling clock on the transmitting side and the second sampling clock on the receiving side by performing a phase comparison with the second phase reference signal generated from the recovered clock, As a result, the relative phase between the color burst of the input analog color television signal and the color burst of the reproduced color television signal of the receiver output can be synchronized. Since the present invention has such effects, it is not necessary to use a frame synchronizer or the like to suppress the phase fluctuation by adopting the sampling clock regenerating circuit of the present invention.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1 ... Input terminal, 2 ... A / D converter, 3 ... Clock generation circuit, 4 ... Encoder, 5 ... Dividing circuit, 6 ... Sampling circuit, 7 ... Dividing circuit, 8 ...... Multiplexing circuit, 9 ... Clock generation circuit, 10 ... Output terminal, 11 ... Input terminal, 12 ...
... Separation circuit, 13 ... Clock recovery circuit, 14 ... Phase comparison circuit, 15 ... Sampling circuit, 17 ... Decoder, 18 ... Smoothing circuit, 19 ... Dividing circuit, 20 ... D / A Converter, 21 …… Clock recovery circuit, 22 …… Output terminal.

Claims (1)

[Claims] 1. A means for generating a first sampling clock phase-synchronized with a color subcarrier of an input television signal, and a first sampling clock divided by frequency to synchronize with a phase of the color subcarrier. A means for generating a phase reference signal; a means for sampling the first phase reference signal at a constant period obtained by dividing the transmission path clock; and a means for sampling the sampled first phase reference signal. Means for multiplexing and transmitting an input television signal with encoded information, means for dividing a second sampling clock reproduced at the receiving side to generate a second phase reference signal, and reproduction at the receiving side The second transmission is performed for each frame period obtained by dividing the generated transmission path clock.
And a phase difference signal representing a phase difference between the sampled first phase reference signal and the sampled second phase reference signal obtained by separating the phase reference signal from the received signal. And means for generating and smoothing and outputting the phase difference signal, and means for generating a second sampling clock phase-locked with the first sampling clock in response to the smoothed phase difference signal. Sampling clock recovery circuit.