JPH07105786B2 - Pseudo random signal receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to a signal receiving apparatus for detecting a bit error occurring when data is transferred by using a pseudo random signal, and the pattern of the pseudo random signal is out of synchronization. The present invention relates to a pseudo-random signal receiving device capable of quickly detecting noise.

More specifically, the receiving side is provided with two pseudo random signal generating circuits for generating a signal having the same pattern as the pattern of the pseudo random signal prepared for the transmitting side, and one of the pseudo random signal generating circuits detects a bit error. And the other is used for out-of-sync detection.

[Prior Art] When a pulse is transmitted in a digital communication line,
Pulses may disappear or unnecessary pulses may occur due to jitter, level fluctuations, and the like due to noise and crosstalk. In this case, the data transmitted from the transmitting side is changed and transmitted to the receiving side, and the transmission quality of the digital communication line deteriorates. The transmission quality of a digital communication line can be evaluated by the bit error rate. In the measuring instrument for that purpose, the receiving side is equipped with a PN signal generation circuit that generates a signal of the same pattern as the pseudo random signal pattern prepared on the transmitting side, and the synchronization of the pattern between the PN signal and the receiving signal is established. After that, the respective bits of both are compared, and the error rate is obtained from the difference. In addition to the pattern synchronization, it is of course necessary that clock synchronization be established, but the present invention relates to pattern synchronization, and a description of clock synchronization will be omitted. Hereinafter, out-of-sync of a pattern is simply referred to as out-of-sync.

Here, the terms used in the following description are defined.

First, the transmission signal is a pseudo-random signal generated by a transmission device paired with the reception device of the pseudo-random signal according to the present invention. This signal is guided to the receiving device via a certain transmission medium.

Next, the received signal is a signal guided to the input end of the receiving device, and the transmitted signal has passed through the transmission medium.
When no bit error occurs between the transmission end and the reception end, the transmission signal and the reception signal are essentially the same. However, when a bit error occurs, the received signal is different from the transmitted signal because some bits are missing or extra bits are superposed.

The PN signal is a pseudo-random signal generated by a pseudo-random signal generating circuit configured by the shift register 11 or 41 and the exclusive OR gate 12 or 42 provided in the receiving device, It has exactly the same pattern as the transmitted signal pattern.

Hereinafter, the operation procedure of out-of-sync detection according to the conventional technique will be described with reference to FIG.

i) In the case of generating a PN signal that is repeated in a cycle of (2 ^M −1) bits in an M-bit shift register,
First, the control signal from the control unit 28 forms a path 2c-2a with the first switch 2, and the received signal is a shift register.
Switch to the state that is read in 11.

ii) The shift register 11 reads the M-bit string in the received signal.

iii) After reading the M-bit string of the received signal into the shift register 11, the control signal of the control unit 28 switches the first switch 2 to form a path between 2c-2b. As a result, the measuring synchronization circuit 1 generates a PN signal having the same pattern as that of the M-bit string of the transmission signal and thereafter and having the same phase as the reception signal. That is, the synchronization of the measuring synchronization circuit 1 is established. This is based on the assumption that there is no error in the M bit string read into the shift register 11.

iv) Generally, the following procedure is performed in consideration of the fact that the bit of the received signal that has been read has an error. That is,
The signal generated inside the measuring synchronization circuit 1 and the received signal are compared by the comparator 3 for M bits or more, and if there is no error, it is assumed that the synchronization is established (this operation is called synchronization protection).

v) After the synchronization is established, the received signal and the PN signal output from the measuring synchronization circuit 1 are compared by the comparator 3, and the number of times of comparison is counted by the first counter 14. Then, the second counter 15 counts the number of bit errors that have occurred within a certain time, and when the number exceeds a preset number, it is considered that synchronization is lost.

The above is the method for detecting the synchronization loss according to the conventional technique.

[Problems to be Solved by the Invention]

The conventional method counts the number of bit error occurrences in detecting out-of-sync and determines that the out-of-sync occurs only when the number of bit error occurrences exceeds the preset number. , Although the synchronization between the received signal and the PN signal output from the PN signal generation circuit on the receiving side does not occur, it is judged that the synchronization is out of sync only by the occurrence of a bit error. There is a problem that it ends up.

There is also a drawback that it takes time to detect the loss of synchronization.

Also, even if they are out of sync, there was no way to know exactly how much they were out of sync.

[Means for Solving the Problems]

In order to solve the above-mentioned problems, the present invention includes a measurement synchronization circuit 1 having a shift register 11 and an exclusive OR gate 12 as shown in FIG. , A synchronization loss detecting synchronization circuit 4 having the same configuration as the above measurement synchronization circuit for determining whether or not a synchronization loss has occurred, and the shift registers 11 and 41 in both synchronization circuits are also provided. A bit pattern comparator 7 for comparing logic states in parallel is provided.

[Action]

Next, the operation procedure of out-of-sync detection according to the present invention will be described.

After synchronization is established between the received signal and the PN signal on the receiving side generated by the shift register 11 and the exclusive OR gate 12 of the measurement synchronization circuit 1, the reception signal and the output of the measurement synchronization circuit 1 Are compared by the comparator 3.

When the comparator 3 detects a bit error, the reception signal is read into the shift register 41 on the side of the synchronization loss detection synchronization circuit 4 having the same configuration as the measurement synchronization circuit 1 described above. Then, the received signal and the synchronization circuit 4 for out-of-sync detection
Establishes synchronization with the PN signal on the receiving side generated in.

The bit pattern comparator 7 compares the logical states of the shift registers 11 and 41 of the measurement synchronization circuit 1 and the out-of-synchronization detection synchronization circuit 4 in parallel, and both logic states are 1
If the bits are different, it is determined that the synchronization is lost.

〔Example〕

 Examples of the present invention will be described below.

First, the configuration of one embodiment of the present invention shown in FIG. 3 will be described.

The measurement synchronization circuit 1 is composed of a shift register 11 and an exclusive OR gate 12. The first switch 2 includes a control unit 8
2c-2a or 2c-2b is formed by the control signal from. When the first switch 2 forms the path 2c-2a, the received signal is input to the shift register 11 during the period when the path is formed. On the other hand, the first switch 2 is 2c-
When forming the path of 2b, the output of the exclusive OR gate 12 is led to the input of the shift register 11. Further, the output of the shift register 11 and the output of a predetermined bit of the shift register 11 are led to the respective inputs of the exclusive OR gate 12. In this state, the measuring synchronization circuit 1 generates a PN signal having a pattern that is essentially the same as the transmitted signal. The comparator 3 compares the received signal with the PN signal generated inside the measuring synchronization circuit 1 and, if they are different, informs the control unit 8 that a bit error has occurred. The control unit 8 receives an error notification from the comparator 3 and outputs a switching signal to the second switch 5. The out-of-synchronization detection synchronizing circuit 4 has exactly the same configuration as the measuring synchronizing circuit 1, and is composed of a shift register 41 and an exclusive OR gate 42. Also, the second switch 5 has exactly the same configuration as the first switch 2. The bit pattern comparator 7 compares the logical states of the two shift registers 11 and 41 in parallel, and outputs the result when out-of-synchronization is detected.

Next, the operation procedure of the present invention will be described. The operation is performed by executing the procedure described in the related arts i) to iv), and the synchronization between the received signal and the PN signal generated from the measurement synchronization circuit 1 is established. , It will be described from the state where the synchronization protection is obtained. Further, in this embodiment, the shift register has 5 bits (M = 5).

The once-established synchronization between the received signal and the PN signal generated from the measurement synchronization circuit 1 is also present in the extraction error when extracting the clock from the received signal or in the middle of the transmitter and the receiver. There is a possibility that the device or the transmission medium may come off due to bit loss or the like. When the synchronization is lost, the following procedure is performed as a method for detecting this.

(1) The received signal is compared with the PN signal generated by the measuring synchronization circuit 1.

(2) The comparator 3 detects a bit error.

(3) When the comparator 3 detects an error, the comparator 3 notifies the control unit 8 of the occurrence of the error.

(4) The control signal from the control unit 8 forms a path 5c-5a with the second switch 5, and the received signal is a shift register.
Switch to the state that can be read by 41.

(5) Read the M-bit string in the received signal into the shift register 41.

(6) After the M-bit string in the received signal is read into the shift register 41, the second switch 5 is switched by the control signal of the control unit 8 to form a path between 5c-5b. As a result, the out-of-synchronization detection synchronizing circuit 4 generates a PN signal having the same pattern as that of the M-bit string and thereafter of the transmission signal and having the same phase as the reception signal. That is, the synchronization of the out-of-synchronization detection synchronization circuit 4 is established. This is a case where it is assumed that there is no error in the M bit string read into the shift register 41.

(7) In general, the following procedure is continuously performed in consideration of an error in the received signal that has been read. The PN signal generated inside the out-of-synchronization detection synchronizing circuit 4 and the received signal are compared by the comparator 6 for M bits or more, and if there is no error, it is assumed that the synchronization is established (this operation is called synchronization protection). .

(8) After the synchronization of the out-of-synchronization detection synchronization circuit 4 is established, the bit pattern comparator 7 causes the shift register 11, 41 of each of the measurement synchronization circuit 1 and the out-of-synchronization detection synchronization circuit 4 to parallelize the logical states. Compare to.

(9) When all the comparison results are the same, the procedure (1) is performed.
Since the bit error detected in step 3 is merely a bit error and is not due to loss of synchronization, the procedure returns to the state of the above procedure (1) and waits for the next bit error detection.

(10) On the other hand, if the comparison result is different even by one bit, the bit error detected in the above step (1) is due to the loss of synchronization, and it is determined that the synchronization circuit for measurement 1 has lost the synchronization.

The result of this synchronization loss is displayed on the display unit 10 so that the operator of the measuring instrument can recognize it. Alternatively, the received signal and the PN signal output from the measurement synchronization circuit 1 are compared by the comparator 3, and the number of times of comparison and the number of bit errors are counted, respectively.
Processing may be performed so that the counting results of the second counters 14 and 15 are invalidated.

Further, when it is determined that the out-of-synchronization occurs, the control unit 8 is notified of the out-of-synchronization occurrence. Normally, the synchronization of the measurement synchronization circuit 1 is re-established, but in the present invention, the measurement synchronization circuit 1 and the out-of-synchronization detection synchronization circuit 4 have exactly the same configuration, so that the control unit 8 In response to the instruction, the out-of-synchronization detection synchronizing circuit 4 which is synchronized by the above steps (4) to (6) is replaced with the out-of-synchronization detection synchronizing circuit 4 as the measuring synchronization circuit 1. It is naturally possible to continue counting the number of bit errors. In this case, the third switch 13 switches the path 13a-13c to 13b-13c in response to an instruction from the control unit 8 and compares the received signal with the PN signal output from the out-of-synchronization detection synchronization circuit 4. The counted number and the bit error number are counted by the first counter 14 and the second counter 15, respectively.

The above description corresponds directly to the flow chart shown by FIG. Steps i) to iv) are procedures of the conventional technique, and steps (1) to (10) are combined with steps i) to iv) to form the procedure of the present invention.

Next, with reference to FIG. 5, the difference in the average synchronization loss detection time between the conventional technique and the present invention will be described. The detection time by the method of the prior art is shown by a broken line, and the detection time by the method of the present invention is shown by a solid line. In the prior art, as a method for detecting out-of-synchronization, the received signal and the PN signal output from the measurement synchronization circuit 1 are compared by the comparator 3, and bit errors exceeding a certain probability set in advance are detected. If it occurs, it is considered as out of synchronization. Usually, the probability is represented by a predetermined number of received signals and a predetermined number of bit errors therein. Generally, the probability is set from 1/10 to 1/5. The number of times the received signal and the PN signal output from the measuring synchronization circuit 1 are compared is counted, and the number of bit errors counted before the count result reaches a predetermined number of bits (m) is determined by a predetermined number. When the number of bit errors (n) is exceeded, it is considered that synchronization is lost.

In FIG. 5, the horizontal axis represents the predetermined number of bits m, and the vertical axis represents the time T required for detecting the average synchronization loss. When the loss of synchronization is detected by the method of the prior art, the time required from the occurrence of the loss of synchronization to the detection of the loss of synchronization is obtained as follows. If it goes out of sync,
The comparator 3 detects an error once every two bits. Therefore, it takes an average period of 2 × n × t until the count value of the number of bit errors reaches the predetermined number n of bit errors. Here, t is a clock cycle.
Further, in this method, the control unit 28 counts the number of times the received signal is compared with the PN signal output from the measurement synchronization circuit 1 and the number of bit errors by the first counter 14 and the second counter 15, respectively. Then, each time the count result reaches m, the counters 14 and 15 that have counted both count values are cleared and counted again, which may take additional time. The probability that the number of times the received signal and the PN signal output from the measurement synchronization circuit 1 are compared before the count value of the number of bit errors reaches n is 2n / m, and the synchronization is lost in that case. The time required to detect is 3 × n × t on average. Therefore, the average value T of the time required for synchronization loss is For example, if n = (1/5) m, T = 0.48mt is required.

As described above, according to the method of the related art, if the number of the predetermined number of bits m is small, the time required for detecting the loss of synchronization can be short, but if the accurate detection of the loss of synchronization is performed, the number of bits m Is increased, the time required to detect out-of-synchronization becomes proportionally longer. If m is reduced and out-of-sync detection is attempted quickly, the relationship between bit error and out-of-sync detection is reduced.

In the present invention, the out-of-synchronization detection synchronous circuit 4 starts detection only when the comparator 3 on the side of the out-of-synchronization detection circuit 1 detects a bit error. Must be read into the shift register 42, the synchronism detection synchronization circuit 4 must generate a PN signal, and the synchronization protection must be performed. Shift register 42
When 5 bits are used and 10 bits of synchronization protection, which is twice the number of bits of the shift register, are performed, the time required to establish synchronization is 16T. It has the following formula T = (Mt + t + 2M
t). The first term Mt on the right-hand side of this equation is the time required for reading into the shift register, the second term t is the time for detecting a bit error, and the third term 2Mt is the time required for synchronization protection.

Further, after that, the shift register 11 of the measurement synchronization circuit 1
And the contents of the shift register 41 of the synchronization circuit 4 for detecting synchronization loss are directly compared bit by bit to determine whether or not synchronization is lost. Therefore, the time required to detect out-of-sync is constant regardless of m and n, and the accuracy of out-of-sync detection is always maintained.

The above-mentioned bit pattern comparator 7 includes each shift register 11,
Although the logical states of 42 are compared in parallel to detect only coincidence or non-coincidence, as another embodiment, the bit pattern comparator 7 compares the shift registers 11 and 41 in parallel, and synchronizes for measurement. It is also possible to output how many bits (the number of slips) the PN signal outputs from the circuit 1 and the synchronization detection synchronous circuit 4 are shifted. A method of detecting the number of slips of this bit pattern will be described with reference to FIGS. 6 and 7.

FIG. 6 shows a memory 81 in which the number of slips of a bit pattern corresponding to the possible states of the two shift registers 11, 41 is written in advance, and the memory 81 and the shift register 11,
Shows the interrelationship with 41. This memory is shift register 1
Inputs from 1 and 41 are received as addresses, and the slip count and the out-of-synchronization detection signal (a) are output.

FIG. 7 is a diagram showing the internal state of the memory 81. In this memory 81, the last 1 bit (a) of the data is used as a bit indicating whether or not synchronization is lost.

The number of slips of this bit pattern is detected by the following procedure. First, an address is generated with the logical state of the shift register 11 as the upper bit and the logical state of the shift register 41 as the lower bit. Then, the data (slip number) indicated by the address is output from the memory 81. This address and data are related in advance to the state of any two shift registers and the slip number of the PN signal in that case. For example, the input from the shift register 11 is 00001
Then, when the input from the shift register 41 is 01001, the address is 0000101001, the data pointed to by the address is 26, and the patterns of both PN signals slip 26. By preparing such a table in the memory 81 and configuring the bit pattern comparator 7, not only can the out-of-sync be detected, but the number of bit-pattern misalignments can be easily detected together.

〔The invention's effect〕

According to the pseudo-random signal receiving apparatus of the present invention, the synchronization loss detecting synchronization circuit 4 having the same structure as the measurement synchronization circuit 1 is provided, and each shift register 11 in the two synchronization circuits is
Since the bit pattern comparator 7 for comparing the 41 logical states in parallel is provided, it is possible to accurately distinguish between the occurrence of a simple bit error and the occurrence of loss of synchronization, and even if a large number of bit errors occur. There is no need to erroneously recognize that a synchronization loss has occurred and perform measurement again.

In addition, as a method of detecting the loss of synchronization, the received signal and the PN signal output from the measurement synchronizing circuit 1 are compared by the comparator 3, and a predetermined number or more of bit errors occurred in advance. In this case, as compared with the conventional method that considers that there is a loss of synchronization, the detection of the loss of synchronization can be determined in a fixed time regardless of the predetermined number of bits, so if the loss of synchronization occurs, re-measure immediately. Can be done easily.

In addition, the synchronization circuit for measurement 1 and the synchronization circuit for detection of out-of-sync 4
When the sync loss detection synchronization circuit 4 detects the synchronization loss of the measurement synchronization circuit 1, the synchronization loss detection synchronization circuit 4 can continue to detect the bit error. In the measurement synchronization circuit 1, it is possible to save the time required to start the detection of the bit error as compared with the case where the synchronization with the received signal is reestablished.

Further, it is possible to detect the number of bit pattern slips, which has been impossible in the past.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is a block diagram showing the configuration of the prior art, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a prior art and the present invention. FIG. 5 is a flowchart showing the operation of the above, and FIG. 5 is a diagram showing the difference in the average out-of-sync detection time between the prior art and the present invention. FIG. 6 is a diagram showing a configuration in which the bit pattern comparator 7 is provided with a memory 81 for detecting the number of slips of the bit pattern,
FIG. 7 is a diagram showing the inside of the memory. 1 ... Synchronous circuit for measurement, 2 ... First switch, 3 ...
Comparator, 4 ... Synchronous circuit for detecting loss of synchronization, 5 ... Second
Switch, 6 ... comparator, 7 ... bit pattern comparator, 8 ... control unit, 9 ... counter, 10 ... display unit, 11
...... Shift register, 12 …… Exclusive OR gate, 41 …… Shift register, 42 …… Exclusive OR gate, 28
...... Control unit, 14 ... First counter, 15 ... Second counter, 13 ...
Third switch, 81 ... Memory.

Claims (1)

[Claims] 1. A synchronizing circuit for measurement (1) having a shift register and an exclusive OR gate, a reception signal composed of a pseudo-random signal and an output from the exclusive OR gate are switched and input to a shift register. 1 switch (2)
And a comparator (3) for comparing the received signal with the output from the measuring synchronization circuit, wherein a synchronization error detection synchronization having the same configuration as the measuring synchronization circuit is provided. A second switch (5) for switching between the circuit (4), the received signal and the output from the exclusive OR gate of the out-of-synchronization detection synchronization circuit and inputting them to the shift register.
And a comparator (6) for comparing the received signal with the output from the synchronization loss detection synchronization circuit, and a bit comparison between the shift register of the measurement synchronization circuit and the shift register of the synchronization loss detection synchronization circuit. And a bit pattern comparator (7) for performing the pseudo random signal reception device.