JPH07104659B2 - Driver-Built-in active matrix panel - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a driver-embedded active matrix panel formed of thin film transistors (hereinafter abbreviated as TFT).

[Prior art]

Successful trial production of active matrix panels in which a TFT matrix for switching was formed by a thin film layer of polycrystalline silicon or amorphous silicon on a transparent substrate, and LCD TVs using amtive matrix panels were mass produced and commercialized. Is being done. Attempts have been made to form scan line or data line drivers on the same transparent substrate on which the switching TFT matrix is formed, and the results have already been announced. (Y.Oana SID84DIGEST, P.312, S.Morozumi, et al SI
D84DIGEST, P316) The conventional driver built in the active matrix panel, especially the data line driver, is configured as shown in Fig. 1, and the analog switches 106, 107, ... are connected to the data lines 111, 112, ..., respectively. , The opening and closing of each analog switch is controlled by the output signals of the shift registers 101, 102, .... In the figure, 121 is a video signal line, 1
22 is a scanning line. When the data line driver is configured as described above, the shift register must operate at the same frequency as the sampling frequency of the video signal, and high speed is required. However, the on-resistance of TFT is generally high, and high-speed operation like single crystal silicon MOSFET cannot be expected. Therefore, according to the conventional active matrix panel with a built-in driver, the sampling frequency of the video signal is limited due to the characteristics of the TFT, and the high definition is also limited.

〔Purpose〕

An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to realize an active matrix panel with a built-in driver, which is capable of sampling a video signal at a high frequency and has a high display quality.

〔Overview〕

According to the present invention, there are provided N data lines and M scanning lines orthogonal to each other, a pixel electrode and a thin film transistor arranged near an intersection of the data line and the scanning line, and a data line driver for driving the data line. In the formed active matrix panel with built-in driver, the data line driver includes an N / K-stage shift register and N / K sampling pulse generating means paired with the N / K-stage shift register. , The sampling pulse generation means have different sampling timings based on the output of the shift register of each stage and K clock signals having different phases,
And the sampling time partially overlaps with the adjacent pixel,
It is characterized in that K sampling pulses are generated.

〔Example〕

 Hereinafter, the present invention will be described in detail based on examples.

FIG. 2 is a block diagram for explaining the gist of the present invention. In the figure, 201 to 203 are shift registers, 20
4 to 206 are sampling pulse generation circuits, 207 to 209 are reset clock signal lines, 210 is a video signal line, 211
Reference numerals 219 to 219 denote analog switches for sample hold, and the above blocks constitute a data line driver. On the other hand, reference numerals 229 to 231 are shift registers forming a scanning line driver. Further, 220 to 228 are data lines, 232 to 234 are scanning lines, and 235, 236, 237 and the like are pixels. FIG. 2 shows an example in which N data lines are driven by an N / 3-stage shift register and a sampling pulse generation circuit.

FIG. 3 shows a concrete embodiment of the present invention. This embodiment is also an example in which N data lines are driven by N / 3 stages of shift registers. In the figure, 301 is a shift register,
Its output terminals are P-type TFTs 302, 303, 304 and N-type TFTs 305, 30
The reset clock signal lines 314, 315 and 316 are connected to the gates of the N-type TFTs 306, 308 and 310, respectively. Output terminals 317, 318 and 319 of the sampling pulse generation circuit composed of TFTs 302 to 310 are analog switches 311, 312 and 313 for sample and hold, respectively.
Connected to the control terminal of. Further, 320 and 321 are the positive power supply and negative power supply of the sampling pulse generation circuit, respectively, and 322 is
It is a video signal line. FIG. 4 is a diagram for explaining the operation of the embodiment shown in FIG. In FIG. 4, 401 is the transfer clock of the shift register 301, and 405 is the shift register.
Transfer data of 301, 402, 403, 404 are respectively shown in FIG.
Reset clock signal transmitted by 5,316, 406,4
07 and 408 are timing charts of sampling pulses output to the terminals 317, 318 and 319 of FIG. 3, respectively. First, at the falling time 409 of the shift register output, the P-type TFT 30
The sampling pulses 406, 407 and 408 are set to a high level by turning on the 2 to 304 and turning off the N-type TFTs 305, 307 and 309. Next, at 410, the shift register output rises, turning off the TFTs 302, 303, 304 and turning on the TFTs 305, 307, 309.
Then, when the reset clocks 402, 403, 404 rise, the TFTs 306, 308, 310 are turned on, so that the sampling pulses 406, 407, 408 are sequentially reset to the low level at the timings of 410, 411, 412. By configuring the analog switches 311, 312, 313 in FIG. 3 so that the sampling pulse is turned on when high, and turned off when it is low, the sample hold of the video signal is 410, 411, 41.
It can be done at 2,413,414, .... As described above, according to the present invention, N data lines can be driven by the N / K stage shift register. However, K
Is the number of outputs of one sampling pulse generation circuit.

In the above-mentioned embodiment, the pulse width T of the sampling pulse is different as shown in 406, 407 and 408 of FIG. If the on resistance of the analog switch formed by the TFT is not sufficiently low, display unevenness may occur in the active matrix panel due to the difference in the pulse width of the sampling pulse.

An embodiment in which the pulse widths of the sampling pulses are all equal is shown in FIG. This embodiment has a structure in which P-type transistors 501, 502 and 503 are added to the sampling pulse generation circuit in the embodiment shown in FIG. In FIG. 5, the same symbols as those in FIG. 3 mean the same components as described in FIG. FIG. 6 is a diagram for explaining the operation of the embodiment shown in FIG. In the figure, reference numeral 40
1 to 405 mean the same as 401 to 405 in FIG. Also, 601, 602, and 603 are terminals 31 of FIG. 5, respectively.
It is a timing diagram of the sampling pulse in 7,318,319. In FIG. 5, the clock signals 404, 402, 403 applied to the gates of the P-type TFTs 501, 502, 503 sequentially fall at the times of 604, 605, 606 in FIG. 6 during the period when the low level is output to the output terminal 323 of the shift register 301. As a result, the sampling pulses 601, 602, 603 are set to the high level. Next, after the output terminal 323 of the shift register 301 rises from the low level to the high level, at the time of 607, 608, 609 in FIG.
Clock signals 402,403,404 applied to the gate of 310
Sampling pulse 601,
602 and 603 are reset to low level. The same operation is performed on all the bits of the shift register, so that sampling and holding of the video signal are performed by the sampling pulses having the same pulse width T.

〔effect〕

As mentioned in the section of the prior art, a TFT composed of polycrystalline silicon, amorphous silicon, etc. is a single crystal silicon F
Its characteristics are inferior to those of ET, and its ON resistance is particularly high. For this reason,
The shift register incorporated in the thin film active matrix panel has a limited operating speed. As in the present invention, the operation required for the shift register by providing the means for driving the N data lines by the N / K-stage shift register and the K-stage sampling pulse generating circuit for each shift register The speed can be reduced to 1 / K of the conventional one.

Further, according to the present invention, the number of stages of the shift register is 1 /
K is sufficient, and instead, a sampling pulse generation circuit composed of 3 to 4 TFTs per stage as shown in FIGS. 3 and 5 is used, so the driver is configured as a whole.
The number of TFTs is reduced. Therefore, the area occupied by the driver portion is reduced, the manufacturing yield is improved, and the power consumption is reduced.

According to the present invention, the active matrix panel with a built-in driver brings about the remarkable effects as described above.

[Brief description of drawings]

 FIG. 1 is a diagram for explaining a conventional technique. FIG. 2 is a block diagram of an embodiment of the present invention. FIG. 3 is a diagram showing an embodiment of the present invention. FIG. 4 is a view for explaining the operation of FIG. FIG. 5 is a diagram showing another embodiment of the present invention. FIG. 6 is a diagram for explaining the operation of FIG. 5.

Claims (1)

[Claims] 1. N data lines and M scan lines orthogonal to each other, pixel electrodes and thin film transistors arranged near intersections of the data lines and the scan lines, and a data line driver for driving the data lines. In the active matrix panel with a built-in driver, the data line driver includes an N / K stage shift register,
The N / K stage shift register and N / K sampling pulse generation means paired with each other, each sampling pulse generation means is based on the shift register output of each stage and K clock signals having different phases. An active matrix panel with a built-in driver is characterized in that it generates K sampling pulses having different sampling timings and a part of the sampling time overlapping with an adjacent pixel.