JPH0684357A - Semiconductor device - Google Patents

Abstract

PURPOSE:To always execute a stable action by actuating a pair of first differential amplifier transistors and actuating also a pair of second differential amplifier transistors when an active state is attained. CONSTITUTION:A lease regulator circuit is mounted on a chip. The P channel type MOS transistors MTrQ3, MTrQ4 and MTrQR and the N channel type MOS transistors MTrQ1, MTrQ2 and MTrQ5-MTrQ8 and a capacitor CC are provided. Then, the transistors MTrQ1 and MTrQ2 constitute a pair of first differential amplifier transistors and the transistors MTrQ6 and MTrQ7 constitute a pair of second differential amplifier transistors. The first transistors MTrQ1 and MTrQ2 are always actuated and a current to the extent of 10muA flows to it through the transistor MTrQ5. At an active time, the gate of the transistor MTrQR is driven by the comparatively large current of an mA level by a prescribed circuit and a pair of second transistors MTrQ6 and MTrQ7 are also actuated. Then, a voltage control circuit to which the current to the extent of some mA flows through the transistor MTrQ8 and which can execute the stable action under any condition is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a voltage control circuit for supplying a stable voltage is mounted on a chip. In recent years, a voltage control circuit is mounted on a chip of an integrated circuit such as a semiconductor memory device such as a DRAM or an SRAM, and a voltage generated by a reference voltage generating means provided in the chip with respect to a voltage supplied from the outside is There is provided a semiconductor device having a circuit for supplying a constant voltage to and. The advantage of mounting a constant voltage generation circuit on the chip is the same as that of the device generally known as "stabilized power supply", and even if an unstable power supply is supplied, a stable voltage is required in the load circuit part. Is in the point of being able to supply. For example, 5V from outside
Even if the power is supplied, the inside of the chip is designed with a power supply voltage specification of 3V, and a series regulator type stabilized power supply circuit is inserted between them to slightly change the 5V of the voltage supplied from the outside. Also, the internal 3V is stably supplied. In recent years, there has been a demand for provision of a semiconductor device equipped with a voltage control circuit capable of stable operation under any circumstances.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing an example of a conventional semiconductor device, showing a feedback control type series regulator circuit. As shown in the figure, a general series regulator circuit mounted on a chip includes P-channel type MOS transistors Q ₃ , Q ₄ and QR _; N-channel type MOS transistors Q ₁ , Q ₂ and Q ₅ and capacitors. It is configured with C _C.

Reference numeral V _EXT indicates a power supply voltage supplied from the outside, V _ref indicates, for example, a reference voltage generated by reference voltage generating means provided in the chip, and V _ref
INT indicates the voltage supplied to the internal circuit. Further, as shown in FIG. 5, the transistors Q ₃ and Q _{4 form} a pair of load devices, and the transistors Q ₁ and Q _{2 form} a differential amplification transistor pair. here,
The transistor Q ₅ is a differential amplification transistor pair Q ₁ and Q _2.
And a ground, and a reference voltage V _ref is applied to its gate.

First, the series regulator (internal step-down regulator) circuit shown in FIG. 5 is used as a target circuit to perform a logical analysis of a transient response. In other words, the transient response of the internal step-down regulator is clarified by mainly estimating the transient response of the internal step-down regulator, and the key points to be noted in the design are clarified. Perform a theoretical analysis of.

In the circuit of FIG. 5, the feedback control is only for long-cycle fluctuations, and the differential amplifier is designed to minimize the current. That is, the size of the transistor Q _R is set relatively large. On the other hand, for short cycle fluctuations, the capacitor C
By modulating the gate voltage of the transistor Q _R through _C , the drain current of the transistor Q _R is changed to respond.

FIG. 6 is a diagram showing an equivalent circuit for the short cycle fluctuation of the semiconductor device of FIG. The circuit of FIG. 5 described above is
Equivalently, it becomes like FIG. 6 with respect to a short period fluctuation. Figure 6
In the equivalent circuit, the bias voltages V _1, the transistor Q _R has become a sufficient voltage to supply the I _CC2 (about 50 .mu.A) corresponding to the _{standby, V 1 = V EXT - |} V ThQR | ...... ( 1) It will be about. Incidentally, in FIG. 6, reference numeral R _A is the internal resistance of the differential amplifier, and since the amplifier section minimizes the current, it has a sufficiently large impedance that can be ignored with respect to C _{C in} the target range of the signal frequency. Has become. That is, the gate of the transistor Q _R can be considered AC-to be floating.

Next, the model circuit of FIG. 7 will be considered based on FIG. 6 in order to perform the operation analysis. FIG. 7 is a diagram showing a model circuit for explaining the problem of the conventional semiconductor device. In FIG. 7, reference symbol C _O indicates a load wiring system fixed capacitance, and C _L operates instantaneously by a clock operation. It is the internal capacitance of the circuit (for example, the bit line capacitance that is seen immediately when the sense amplifier operates, or the precharge capacitance of the decoder or the like that is seen at reset).

During standby of V _{G (t)} and V _{INT (t)} (t = 0
^- The value in) is,

[0009]

[Equation 1]

Is flowing. Now, V_{INT (t)}And I_{D (t)}connection of
Is I_DBy C_O+ C_LAnd C _Cand
C_GSSince it has a relationship to charge the series capacitance of,
Can be represented.

[0011]

[Equation 2]

Here, in order to solve this differential equation (9),

[0013]

[Equation 3]

From the relationship of equation (3),

[0015]

[Equation 4]

Is obtained. Here, according to equation (17),
If only each circuit constant is known, the transient change of V _INT can be calculated. Looking at the functional form of the equation (17), V _{INT (t)} is a hyperbola, and the larger the value of A, the closer to the asymptote. Note that increasing the value of A, the transistor Q _R
To increase the gain and the capacitance C _C.

FIG. 8 is a diagram showing the time change V _{INT (t)} of the internal voltage in the model circuit of FIG. Next, the change in FIG. 8 is calculated with the parameters of the actual device, and verification is performed with the parameters of the actual device. First, we introduce the following assumptions.

[0018]

[Equation 5]

In the above case,

[0020]

[Equation 6]

Further, the influence of the resistance component will be considered. Figure 9
FIG. 1 is a diagram showing a result of calculation of changes in internal voltage using actual parameters in a conventional semiconductor device.
0 is a diagram showing a circuit when a resistance component is included in the model circuit of FIG. 7. In the result of FIG. 9, since the resistance of the wiring system is not inserted, a _drastic drop of the internal voltage V _INT occurs at t = 0 ⁺ . However, in reality, the wiring resistance or the internal resistance of the transistor T _r is always included in C _L as in the circuit shown in FIG. The response of this circuit is analytically poor, so it is better to focus on simulation, but the response is qualitatively as follows.

Immediately after the switch SW was turned on, in the analysis before R = 0, there was a rapid drop in the internal voltage V _{INT (t)} due to the charge redistribution immediately. However, if the resistance R _L exists,
If the effect of the transistor Q _R is not considered, the internal voltage V
_{INT (t)} is the response of C _O , C _L , and R _L when solving the differential equation (without solving),

[0023]

[Equation 7]

It is In the circuit of FIG. 10, the change of the internal voltage V _{INT (t),} the charge redistribution between the current and the capacitance C _O and C _L from the transistor Q _R is determined by the synthesis of current due to the current flowing through the resistor R _L Therefore, as shown in FIG. 12, the sudden drop of the internal voltage V _{INT (t)} is limited due to the influence of the resistance R _L near the time t = 0 ⁺ , and the characteristics of the transistor Q _R are governed with time. become. That is, the presence of the resistor R _L does not cause a rapid decrease in the internal voltage V _{INT (t)} as shown in FIG. How much it depends depends on the resistance R _L and the capacitance C _{O according} to the equation (21).

[0025]

[Equation 8]

Is obtained. Using the above values (C _o = 1
000 pF, C _L = 3,500 pF), t ₁ = 777.8 × 10 ⁻¹² _RL (25). When R _L = 10Ω, t ₁ = 7.78 ns, R _L =
Since it is 77.8 ns at 100Ω, t in FIG.
In the vicinity of = 0, the internal voltage V _{INT (t)} does not change abruptly, and the voltage drops toward t = 7.78 ns even when R _L = 10Ω. In addition, the transistor Q by the effect of _R, t = since the mid 7~8ns internal voltage V _{INT (t)} has recovered significantly, the internal voltage V Looking at these in a comprehensive manner
The transient change of _{INT (t)} seems surprisingly small. It should be noted that it is better to use the simulation for the detailed value of the fluctuation range than the analytical method.

Next, the operation of the feedback circuit will be considered.
When V _{INT (t)} drops with respect to V _INTO by the action of the feedback circuit, the gate voltage of the transistor Q _R is pulled to the ground side, and driving of Q ₁ is started so as to increase V _{INT (t).} . The driving force of Q ₁ and Q ₂ (see Fig. 5) is set weakly, and C _{C of} Q _R looks like a large capacity due to the Miller effect. Therefore, the driving effect from Q ₁ side is near t = 0 ^+. Does not appear in.

However, for Q ₁ and Q ₂ , V _{INT (t)} is V
_While it is lower than _INTO , the drive is continued to increase V _{INT (t)} . As is clear from FIG. 9, it takes about 100 ns to recover V _{INT (t)} to V _INTO almost completely (when the feedback effect is not considered), so that driving of Q ₁ and Q ₂ continues for a correspondingly long time. It will be. The operations of Q ₁ and Q ₂ are approximated to those of a comparator, and it is considered that Q ₁ is on and Q ₂ is off. In this case, the driving current of Q ₁ is determined by the current of Q ₃ , so if Q ₃ is approximately a constant current source, this value is the consumption current allowed for the amplification system during standby (≈10 μA).
It is itself. When this is expressed as I _S, C at t = t ₁ near _O, Q and disappears charge redistribution effects at C _{L R}
Charging operation from that circuit operation at t = t ₂ consisting mainly (t _2> t _1), as shown in FIG. 13, can be considered, ignoring the effect of R _L (the C _L R _L The series circuit looks completely capacitive). At this time, the circuit equation is

[0029]

[Equation 9]

It becomes This equation is Runge-Kut
Numerical solution by the ta method yields the characteristics shown in FIG. Note that t =
In the vicinity of 0, the influence of R _L is strong and the solution of the above equation is not valid, so that it is shown at t ≧ 20 ns where R _L can be ignored. Looking at the result of the numerical solution described above, it can be seen that V _{INT (t)} ≧ 2.4 V is t
= 190 ns (W = 100000 μm, I _S = 10 μ
A, C _C = 100 pF) and V after t ≧ 190 ns
_{Since INT (t)} > V _INTO , the comparators of Q ₁ and Q ₂ are inverted and the operation of pulling I _S does not occur. W = 1000
At 0 μm this is when t = 300 ns. On the other hand, V
Considering the change with time of _{G (t)} , from Eq. (27), when W = 100000 μm, VG _{(t = 190 ns)} = V _EXT − | V _ThP │−0.00841 W = 10000 μm, VG _{(t = 300 ns )} = V _EXT − | V _ThP | −0.01327. That is, 8.4 at W = 100000 μm
At mV, 10,000 μm, the gate bias is applied only by 13.3 mV, and V _{INT (t)} crosses V _INTO , so that the error amplifiers Q ₁ and Q ₂ stop pulling I _S , and conversely, I _S is changed. for a while even so as to supply Q _R since continue the on-state V _{INT (t)} would be an overshoot.

In practice, DRAM is faster than 190ns.
V moves because it moves during the crew time_{INT (t)}Before the full recovery
Will enter the cycle. As a result V_{INT (t)}<V_INTO
Continues for a long time, during which the error amplifier_SPull
I will leave it. This result Q _RGate voltage is quite V
_SSSudden standby because operation continues while pulled to the side
Q when entering_RCan not cut off immediately, V
_{INT (t)}The overshoot of will not be negligible
There is a fear.

[0032]

As described above, as shown in FIG.
Series regulator (internal step-down regulator)
The circuit consumes itself when the chip is in the standby state, along with the voltage control ability to supply a constant voltage to the consumption current of the chip which changes rapidly and transiently in the active state. There is a need to minimize power. Therefore, conventionally, in order to suppress the current consumption during standby, the current passed through the feedback control amplifier is set to about several tens of microamperes. As a result, long-term (eg, a few seconds)
The feedback control has an effect to make the output voltage always equal to the reference voltage (reference voltage), but for short-term (several tens of nanoseconds) changes, , The current of the amplifier is small and there is no ability to drive the load at high speed.

A large capacitance is intentionally inserted between the gate and drain of the pMOS transistor for series control, and when the load side current changes abruptly to change the drain voltage of the control transistor, Bring change to the gate. That is, the control by the differential amplifier has no effect on the fast change of the load current, and only the gate voltage is modulated by the capacitive coupling.

By the way, in the case of the conventional circuit, when the load current suddenly increases, the output voltage drops and gradually recovers. However, according to the analysis made by the present inventor, the internal power supply system of the DRAM has a capacity of about 3000 picofarads for charging and discharging, and a capacity for voltage stabilization is added in parallel to the capacity. With this capacity of 2000 picofarads, recovery of this terminal voltage requires several hundreds of nanoseconds, so in a device with a cycle time of about 120 nanoseconds, such as DRAM, the next cycle is started before the voltage is completely recovered. And a large load current flows again. If this is repeated, the voltage inside the chip will always remain slightly lower than the normal voltage, so the feedback control circuit that operates in response to long-term changes will increase the output voltage by increasing the series control transistor. Will always be driven.

As a result, when the chip, which was operating at high speed with a short cycle time, suddenly entered the standby state, the capacitance (several hundred picofarads) inserted between the gate and drain of the series control transistor was included in the transistor. Since the bias voltage in the direction that lowers the internal resistance of the transistor is charged, the transistor continues to have a low internal resistance until it is charged by the current of the control amplifier. As a result, an unstable cycle may occur in which the chip internal power supply voltage in the standby state where there is almost no load current increases above the specified value, and the internal power supply voltage drops again in the next non-active state.

Such instability of the power supply voltage causes an effect called "power supply bump" for the accumulated charge in the memory cell to cause the effective reduction of the charge amount rather than the normal charge amount. have. As a result, when the sensitivity of the sense amplifier is poor, or when the α ray is incident on the chip to generate noise signal charge, the DRA can be easily
This will cause the M chip to malfunction.

In view of the problems of the conventional semiconductor device described above, it is an object of the present invention to provide a semiconductor device equipped with a voltage control circuit capable of stable operation under any circumstances.

[0038]

According to the present invention, there is provided a semiconductor device having a voltage control circuit mounted on a chip, the voltage control circuit having a pair of load devices Q ₃ and Q ₄ in common, A plurality of differential amplification transistor pairs Q ₁ and Q ₂ ; Q ₆ and Q ₇ whose gates and drains are commonly connected are provided, and the plurality of differential amplification transistor pairs are always operated including a standby state. A first differential amplification transistor pair Q ₁ and Q ₂ and a second differential amplification transistor pair Q ₆ and Q ₇ that operates when in an active state. A device is provided.

[0039]

According to the semiconductor device of the present invention, the plurality of differential amplification transistor pairs are brought into the active state together with the first differential amplification transistor pair Q ₁ and Q ₂ which are always operating including the standby state. And a second differential amplification transistor pair Q ₆ and Q ₇ that operates when Then, the internal resistance of the source side bias circuit of the second differential amplification transistor pair Q ₆ and Q ₇ which operates when in the active state causes the chip to enter the standby state after detecting the transition to the active state. In the meantime, it gradually decreases.

As a result, the semiconductor device having the voltage control circuit mounted on the chip according to the present invention can perform a stable operation under any circumstances.

[0041]

Embodiments of the semiconductor device according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention, showing a feedback control type series regulator circuit (internal step-down regulator circuit). As shown in the figure, the series regulator circuit mounted on the chip of this embodiment is
P channel type MOS transistors Q ₃ , Q ₄ , QR _; N channel type MOS transistors Q ₁ , Q ₂ , Q ₅ , Q ₆ , Q ₇ , Q ₈ and a capacitor C _C.

Reference numeral V _EXT indicates a power supply voltage supplied from the outside, V _ref indicates, for example, a reference voltage generated by reference voltage generating means provided in the chip, and V _ref
INT indicates the voltage supplied to the internal circuit. Further, as shown in FIG. 1, the transistors Q ₃ and Q _{4 form} a pair of load devices, the transistors Q ₁ and Q _{2 form} a first differential amplification transistor pair, and the transistors Q ₆ and Q ₇ constitutes a second differential amplification transistor pair. Here, the transistor Q ₅ is provided between the sources of the differential amplification transistor pair Q ₁ and Q ₂ and the ground, and the reference voltage V _ref is applied to its gate.
The transistor Q ₈ is a differential amplification transistor pair Q.
_It is provided between the sources of ₆ and Q ₇ and the ground, and the gate thereof is supplied with the chip activation clock signal RASZ.

First differential amplifier transistor pair Q ₁ , Q
No. ₂ always operates including the standby state, and a current of about 10 μA is always supplied through the transistor Q ₅ . In addition, the second differential amplification transistor pair Q ₆ ,
Q ₇ operates only when it is in the active state, and in the active state, a current of about several mA flows through the transistor Q ₈ .

As described above, in the semiconductor device of this embodiment, the overshoot of the internal voltage V _{INT (t) in} the conventional semiconductor device in which the voltage control circuit is mounted on the chip is a voltage control circuit under the condition of a specific cycle time. It is designed to prevent the existence of the (internal step-down regulator circuit) from being meaningless. That is, in order to prevent overshoot, it is necessary to restore the fast stable value of the gate voltage of the transistor Q _R, in the semiconductor device of this embodiment, by the circuit of FIG. 1, it is in the active relatively large current and drives the gate of the transistor Q _R at (mA level). Incidentally, in the standby mode, in order to suppress power consumption to a minimum, so as to drive the gate of the transistor Q _R with a small current (.mu.A level).

[0045] Figure 2 is a diagram showing the relationship between the recovery time and the driving transistor current of the internal voltage in the semiconductor device of FIG. 1, in the circuit of FIG. 1, V _INT to the value of pull-out current of the transistor Q _{8 ( t)} is the time required to recover to 2.4 V which is V _INTO (after that, the error amplifier is inverted to suppress the overshoot of V _{INT (t)} )
It shows the result obtained. In this calculation, the value of I _S is changed by the equation (29), and the time at which V _{INT (t)} = V _INTO is obtained by the Runge-Kutta method.

As is clear from the results shown in FIG.
If a current of about 1 mA is passed through the error amplifier, one R
V _{INT (t)} recovers within the AS cycle active period, and as a result, voltage overshoot due to V _{INT (t)} remaining low when the cycle is continued can be prevented. Since the current of about 1 mA is applied to the error amplifier only within the active cycle, no problem occurs in power consumption.

By the way, when the transistor Q ₈ is rapidly turned on, the gain of the feedback loop changes abruptly, and its transient response may cause disturbance of V _{INT (t)} . Therefore, the transistor Q ₈ is preferably applied to the gate of the transistor Q ₈ and blunted RASZ waveform entering the gate to turn slowly. That is, the internal resistance of the source side bias circuit of the second differential amplification transistor pair Q ₆ and Q ₇ which operates when in the active state is detected, and after the transition to the active state is detected, the chip enters the standby state. Gradually lower it before entering.

FIG. 3 is a diagram for explaining the RASZ signal in the semiconductor device of FIG. 1. FIG. 3 (a) shows a waveform diagram of the RASZ signal, and FIG. 3 (b) is for generating a preferable RASZ signal. The circuit of is shown. As shown in FIG. 3 (b), the signal supplied to the gate of the transistor Q ₈ inverts the activation signal RASZ chip inverter I _0, the integrating circuit II constructed it with resistor R ₀ and capacitor C ₀ It is designed to dull the waveform. That is, as shown in (a) of FIG. 3, when the chip activation signal RASZ changes from the high level to the low level when the chip is selected, the signal is output from the inverter I _0.
After being inverted by (in FIG. 3 (a)), it is supplied to the integrating circuit II. Then, the signal whose waveform is blunted by the integrating circuit II (in FIG. 3 (a)) is transferred to the transistor Q ₈
It is supplied to the gate, by which the resistance value of the transistor Q ₈ (ON resistance), during a period from after the chip is activated by the chip enters the standby state, (to increase the current gradually) gradually decreases It will be.

As a result, the semiconductor device equipped with the voltage control circuit can be stably operated under any circumstances. Note that the above-described configuration does not cause a problem because there is some time before the sense amplifier operates after the activation signal RASZ of the chip has fallen (activated). FIG. 4 is a circuit diagram showing a modified example of the main part of the semiconductor device of FIG. In the embodiment described with reference to FIGS. 1 to 3, the chip activation via the integrating circuit is applied to the gate of the transistor Q ₈ which constitutes the source side bias circuit of the differential amplification transistor pair Q ₆ and Q ₇ . Although it adapted to apply a clock signal, in the present embodiment, a plurality of transistors Q which is connected in parallel the transistor Q _8
81 , Q ₈₂ , Q ₈₃ , and these transistors Q ₈₁ ,
Chip activation clock signals having different delays are applied to Q ₈₂ and Q ₈₃ .

That is, as shown in FIG. 4, the delay circuit DD includes a plurality of inverters I _{1 to} I _6, and the gate of the transistor Q ₈₁ has a chip activation clock signal RASZ.
Is directly supplied to the gate of the transistor Q ₈₂ via the inverters I _{1 to} I ₄ and the delayed chip activation clock signal RASZ, and the gates of the transistor Q ₈₃ are connected to the inverters I _{1 to} I ₆ . The chip activation clock signal RASZ, which has been further delayed, is supplied via this. As a result, the transistors Q _{81 to} Q ₈₃ are switched on with the lapse of time, and the current can be gradually increased after activation of the chip and before the chip enters the standby state. In FIG. 4, transistors (bias circuit transistors) are Q _{81 to} Q
₈₃ 3 Tsutosare, also to have been 6 Tsutosa delay circuit number be I ₁ ~I ₆ of the inverter constituting the DD, these configurations says can be variously changed if necessary Nor.

[0051]

As described above in detail, according to the semiconductor device of the present invention, the first differential amplification transistor pair which is always operating including the standby state and the operation when it is in the active state. By providing the second differential amplifying transistor pair that operates, stable operation can be performed under any circumstances.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a relationship between a recovery time of an internal voltage and a drive transistor current in the semiconductor device of FIG.

3 is a diagram showing a waveform of a RASZ signal in the semiconductor device of FIG.

FIG. 4 is a circuit diagram showing a modified example of a main part of the semiconductor device of FIG.

FIG. 5 is a circuit diagram showing an example of a conventional semiconductor device.

6 is a diagram showing an equivalent circuit of the semiconductor device of FIG. 5 with respect to a short cycle variation.

FIG. 7 is a diagram showing a model circuit for explaining a problem of a conventional semiconductor device.

8 is a diagram showing a time change of an internal voltage in the model circuit of FIG.

FIG. 9 is a diagram showing a result of calculation of changes in internal voltage using actual parameters in a conventional semiconductor device.

10 is a diagram showing a circuit when a resistance component is included in the model circuit of FIG.

11 is a diagram showing a transient change of an internal voltage in charge distribution in the model circuit of FIG.

12 is a diagram showing a time change of an internal voltage in the model circuit of FIG.

FIG. 13 is a diagram showing an equivalent circuit of a regulator portion when feedback control occurs in a conventional semiconductor device.

FIG. 14 is a diagram showing a time change of an internal voltage in a conventional semiconductor device when feedback control is occurring.

[Explanation of symbols]

Q ₁ , Q ₂ ... First differential amplification transistor pair (N-type MOS
Transistor) Q _3, Q ₄ ... loading device (P-type MOS _{transistor) Q 5: Q 8; Q} 81, Q 82, Q 83 ... bias circuit transistor (N-type MOS transistor) Q _6, Q ₇ ... second Differential amplification transistor pair (N-type MOS
Transistor) DD ... Delay circuit

Claims (4)

[Claims] 1. A semiconductor device in which a voltage control circuit is mounted on a chip, wherein the voltage control circuit has a pair of load devices (Q ₃ , Q ₄ ) in common, and gates and drains in common. A plurality of connected differential amplification transistor pairs (Q ₁ , Q ₂ ; Q ₆ ,
Q ₇ ), wherein the plurality of differential amplification transistor pairs are in an active state with the first differential amplification transistor pair (Q ₁ , Q ₂ ) which is always operating including the standby state. And a second differential amplification transistor pair (Q ₆ , Q ₇ ) that operates in accordance with the above. 2. The internal resistance of the source side bias circuit of the second differential amplification transistor pair (Q ₆ , Q ₇ ) which operates when in the active state is detected after detecting the transition to the active state. 2. The semiconductor device according to claim 1, wherein the chip is gradually lowered until it enters a standby state. 3. The second differential amplification transistor pair (Q
_6, the claims to the gate of the transistor constituting the source bias circuit of the Q ₇₎ (Q _8), characterized by being adapted to apply a chip enable clock signal passed through the integrating circuit (RASZ) 2 semiconductor devices. 4. The second differential amplification transistor pair (Q
₆, Q₇) Source side bias circuit
(Q₈) Are connected in parallel to each other (Q₈₁, Q
₈₂, Q₈₃), And a plurality of transistors connected in parallel.
(Q₈₁, Q ₈₂, Q₈₃) For each gate, a different delay
Chip activation clock via delay circuit (DD)
The feature is that a clock signal (RASZ) is applied.
The semiconductor device according to claim 2.