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JPH0684910A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device

Info

Publication number
JPH0684910A
JPH0684910A JP25572792A JP25572792A JPH0684910A JP H0684910 A JPH0684910 A JP H0684910A JP 25572792 A JP25572792 A JP 25572792A JP 25572792 A JP25572792 A JP 25572792A JP H0684910 A JPH0684910 A JP H0684910A
Authority
JP
Japan
Prior art keywords
metal layer
barrier metal
connection bore
connection hole
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP25572792A
Other languages
Japanese (ja)
Inventor
Ryuya Hara
竜弥 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP25572792A priority Critical patent/JPH0684910A/en
Publication of JPH0684910A publication Critical patent/JPH0684910A/en
Withdrawn legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device having high reliability in spite of a fineness by a method wherein a diameter of a connection bore is made small and further a reaction between a metallic layer within the connection bore and a conductive region is prevented. CONSTITUTION:After a tapering connection bore 14 is formed in an insulation film 12, and a barrier metal layer 15 and a metallic layer 16 are formed on the entire surface, the metallic layer 16 having a vertical shape and a barrier metal layer 15 are left on only the bottom of the connection bore 14. Thereafter, a liquefied insulation material is applied thereto to fill the connection bore 14 therewith to harden this insulation material to form an insulation film 18. Therefore, a diameter of the connection bore 14 can be made small and also a covering ratio of the barrier metal layer 15 to the connection bore 14 is high to enhance barrier effects. Further, the connection bore 14 can be readily filled with the insulation film 18.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、接続孔をバリアメタル
層と金属層とで埋めるようにした半導体装置の製造方法
に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a contact hole is filled with a barrier metal layer and a metal layer.

【0002】[0002]

【従来の技術】近年における半導体装置の微細化に伴っ
て、接続孔の径も小さくなってきているが、絶縁耐圧を
確保するために層間絶縁膜の膜厚は殆ど変わっていない
ので、接続孔のアスペクト比が大きくなってきている。
このため、Al配線等のように元々段差被覆性が良くな
い配線では、接続孔で導通不良を生じ易く、半導体装置
の信頼性が低くなってきている。
2. Description of the Related Art In recent years, with the miniaturization of semiconductor devices, the diameter of connection holes has become smaller. However, since the film thickness of the interlayer insulating film has not changed in order to secure the withstand voltage, the connection holes are not changed. The aspect ratio is increasing.
For this reason, in a wiring such as an Al wiring which originally has a poor step coverage, a conduction failure is likely to occur in the connection hole, and the reliability of the semiconductor device is becoming low.

【0003】そこで、タングステン層等の金属層で接続
孔を埋め、更にこの金属層と半導体基板等との反応を防
止すると共に金属層と層間絶縁膜との密着性を向上させ
るためにバリアメタル層を金属層の下地として用いてい
る。
Therefore, a barrier metal layer is formed by filling the contact hole with a metal layer such as a tungsten layer, preventing the reaction between the metal layer and the semiconductor substrate, and improving the adhesion between the metal layer and the interlayer insulating film. Is used as the base of the metal layer.

【0004】[0004]

【発明が解決しようとする課題】ところで、バリアメタ
ル層はスパッタリングやCVDで形成するが、上述のよ
うに接続孔のアスペクト比が大きくなってくると、接続
孔に対するバリアメタル層の被覆率も低下してきてお
り、バリア効果が減少してきている。この結果、金属層
と半導体基板等との反応が発生し、信頼性の高い半導体
装置を製造することが困難になってきている。
The barrier metal layer is formed by sputtering or CVD. When the aspect ratio of the contact hole becomes large as described above, the coverage of the barrier metal layer with respect to the contact hole also decreases. The barrier effect is decreasing. As a result, a reaction between the metal layer and the semiconductor substrate or the like occurs, making it difficult to manufacture a highly reliable semiconductor device.

【0005】従って本発明は、接続孔の径を小さくする
ことができ、微細であるにも拘らず、接続孔内の金属層
と導電領域との反応を防止することができるので、信頼
性の高い半導体装置の製造方法を提供することを目的と
している。
Therefore, according to the present invention, the diameter of the connection hole can be reduced, and the reaction between the metal layer in the connection hole and the conductive region can be prevented even though the connection hole is fine. An object of the present invention is to provide a high manufacturing method of a semiconductor device.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置の製
造方法は、導電性領域上の第1の絶縁膜に、導電性領域
に達すると共に外方に向かって広がるように内壁面が傾
斜している接続孔を形成する第1の工程と、接続孔を形
成した後に、バリアメタル層と金属層とを順次に積層さ
せる第2の工程と、金属層及びバリアメタル層を接続孔
の底部上にのみ残す第3の工程と、底部上にのみ残した
金属層及びバリアメタル層と内壁面との間を第2の絶縁
膜で埋める第4の工程とを有するものである。
According to a method of manufacturing a semiconductor device of the present invention, an inner wall surface of a first insulating film on a conductive region is inclined so that it reaches the conductive region and expands outward. Forming a connection hole, a second step of sequentially forming a barrier metal layer and a metal layer after forming the connection hole, and a metal layer and a barrier metal layer on the bottom of the connection hole. And a fourth step of filling a space between the metal layer and the barrier metal layer left only on the bottom and the inner wall surface with the second insulating film.

【0007】また、本発明の半導体装置の製造方法は、
上記製造方法において、底部上にのみ残した金属層及び
バリアメタル層と内壁面との間を液状の絶縁性材料で埋
め、この液状の絶縁性材料を固化させて第2の絶縁膜を
形成するものである。
A method of manufacturing a semiconductor device according to the present invention is
In the above-described manufacturing method, a liquid insulating material is filled between the metal layer and the barrier metal layer left only on the bottom and the inner wall surface, and the liquid insulating material is solidified to form a second insulating film. It is a thing.

【0008】[0008]

【作用】本発明の半導体装置の製造方法では、接続孔の
内壁面を外方に向かって広がる様に傾斜させているの
で、接続孔の径が小さくても、この接続孔に対するバリ
アメタル層の被覆率が高い。このため、バリアメタル層
によるバリア効果が高く、接続孔内の金属層と導電領域
との反応を防止することができる。
In the method of manufacturing a semiconductor device of the present invention, the inner wall surface of the connection hole is inclined so as to widen outward. Therefore, even if the diameter of the connection hole is small, the barrier metal layer for the connection hole is formed. High coverage. Therefore, the barrier effect of the barrier metal layer is high, and the reaction between the metal layer in the connection hole and the conductive region can be prevented.

【0009】また、接続孔の内壁面を外方に向かって広
げているが、接続孔の底部上にのみ残した金属層及びバ
リアメタル層と内壁面との間は第2の絶縁膜で埋めてい
るので、接続孔の径を小さくすることができる。
Although the inner wall surface of the connection hole is widened outward, the second insulating film fills the space between the inner wall surface and the metal layer and barrier metal layer left only on the bottom of the connection hole. Therefore, the diameter of the connection hole can be reduced.

【0010】さらに本発明の半導体装置の製造方法で
は、接続孔の底部上にのみ残した金属層及びバリアメタ
ル層と内壁面との間を液状の絶縁性材料で埋め、これを
固化させて第2の絶縁膜にしているので、接続孔の径が
小さくても、金属層及びバリアメタル層と内壁面との間
を絶縁膜で容易に埋めることができる。
Further, according to the method of manufacturing a semiconductor device of the present invention, a liquid insulating material is filled between the metal layer and the barrier metal layer left only on the bottom of the connection hole and the inner wall surface, and the liquid insulating material is solidified. Since the second insulating film is used, even if the diameter of the connection hole is small, the space between the metal layer and the barrier metal layer and the inner wall surface can be easily filled with the insulating film.

【0011】[0011]

【実施例】以下、本発明の一実施例を、図1を参照しな
がら説明する。本実施例では、図1(a)に示すよう
に、拡散層が形成されているシリコン基板11を絶縁膜
12で覆い、この絶縁膜12に対して従来公知のテーパ
エッチング等を施すことによって、拡散層に達すると共
に外方に向かって広がるように内壁面13が傾斜してい
る接続孔14を形成する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, as shown in FIG. 1A, a silicon substrate 11 having a diffusion layer formed thereon is covered with an insulating film 12, and the insulating film 12 is subjected to a conventionally known taper etching or the like. A connection hole 14 is formed in which the inner wall surface 13 is inclined so as to reach the diffusion layer and spread outward.

【0012】次に、スパッタリングまたはCVDで、図
1(b)に示す様に、バリアメタル層15を全面に形成
する。バリアメタル層15としては、チタン層、チタン
シリサイド層、窒化チタン層、チタン−タングステン合
金層及びこれらの2種以上の組み合わせから成る複合層
を用いる。
Next, a barrier metal layer 15 is formed on the entire surface by sputtering or CVD as shown in FIG. 1 (b). As the barrier metal layer 15, a titanium layer, a titanium silicide layer, a titanium nitride layer, a titanium-tungsten alloy layer, and a composite layer composed of a combination of two or more thereof are used.

【0013】次に、図1(c)に示すように、接続孔1
4を埋め込むようにバリアメタル層15上の全面に金属
層16を形成する。金属層16としては、タングステン
層等を用いる。
Next, as shown in FIG. 1 (c), the connection hole 1
A metal layer 16 is formed on the entire surface of the barrier metal layer 15 so as to bury 4 therein. A tungsten layer or the like is used as the metal layer 16.

【0014】次に、図1(d)に示すように、金属層1
6上にレジスト17を塗布し、このレジスト17のうち
で接続孔14の底部上の部分のみを残すパターニングを
行う。そして、レジスト17をマスクにして、金属層1
6とバリアメタル層15とを異方性エッチングして、垂
直な形状の金属層16とバリアメタル層15とを接続孔
14の底部上にのみ残す。
Next, as shown in FIG. 1D, the metal layer 1
6 is coated with a resist 17, and patterning is performed so that only a portion of the resist 17 on the bottom of the connection hole 14 is left. Then, using the resist 17 as a mask, the metal layer 1
6 and the barrier metal layer 15 are anisotropically etched to leave the vertically-shaped metal layer 16 and the barrier metal layer 15 only on the bottom of the connection hole 14.

【0015】次に、図1(e)に示すように、レジスト
17を除去した後、SOG溶液等の液状の絶縁性材料を
塗布して接続孔14を埋め、この絶縁性材料を焼成して
固化させることによって、絶縁膜18を形成する。
Next, as shown in FIG. 1E, after removing the resist 17, a liquid insulating material such as an SOG solution is applied to fill the connection holes 14, and the insulating material is baked. The insulating film 18 is formed by solidifying.

【0016】次に、レジスト(図示せず)の回転塗布等
を行って全面を平坦にし、このレジストと金属層16と
絶縁膜18とのエッチング速度が等しい条件で、これら
の全面をエッチバックして、図1(f)に示すように、
金属層16と絶縁膜12、18とを平坦にする。
Next, a resist (not shown) is spin-coated to make the entire surface flat, and the entire surface of the resist, the metal layer 16 and the insulating film 18 is etched back under the same etching rate. Then, as shown in FIG.
The metal layer 16 and the insulating films 12 and 18 are flattened.

【0017】なお、図1(f)に示した平坦化の工程は
必ずしも必要ではない。また、以上の実施例ではシリコ
ン基板11中の拡散層を導電領域としたが、シリコン基
板11上の多結晶シリコン膜を導電領域とし、この多結
晶シリコン膜に対する接続孔をバリアメタル層と金属層
とで埋める構造の半導体装置の製造にも本発明を適用す
ることができる。
The flattening step shown in FIG. 1F is not always necessary. Further, although the diffusion layer in the silicon substrate 11 is used as the conductive region in the above embodiments, the polycrystalline silicon film on the silicon substrate 11 is used as the conductive region, and the connection hole for this polycrystalline silicon film is formed with the barrier metal layer and the metal layer. The present invention can be applied to the manufacture of a semiconductor device having a structure filled with

【0018】[0018]

【発明の効果】本発明の半導体装置の製造方法によれ
ば、接続孔の径を小さくすることができるので、微細で
あるにも拘らず、接続孔内の金属層と導電領域との反応
を防止することができるので、信頼性の高い半導体装置
を製造することができる。
According to the method of manufacturing a semiconductor device of the present invention, since the diameter of the connection hole can be made small, the reaction between the metal layer in the connection hole and the conductive region can be prevented even though it is fine. Since this can be prevented, a highly reliable semiconductor device can be manufactured.

【0019】また、本発明の半導体装置の製造方法で
は、接続孔の底部上にのみ残した金属層及びバリアメタ
ル層と内壁面との間を絶縁膜で容易に埋めることができ
るので、微細であるにも拘らず信頼性の高い半導体装置
を効率的に製造することができる。
Further, in the method for manufacturing a semiconductor device of the present invention, since it is possible to easily fill the gap between the metal layer and the barrier metal layer left only on the bottom of the connection hole and the inner wall surface with the insulating film, it is possible to form a fine structure. Despite this, a highly reliable semiconductor device can be efficiently manufactured.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を工程順に示す側断面図であ
る。
FIG. 1 is a side sectional view showing an embodiment of the present invention in the order of steps.

【符号の説明】[Explanation of symbols]

12 絶縁膜 13 内壁面 14 接続孔 15 バリアメタル層 16 金属層 18 絶縁膜 12 Insulating film 13 Inner wall surface 14 Connection hole 15 Barrier metal layer 16 Metal layer 18 Insulating film

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 導電性領域上の第1の絶縁膜に、前記導
電性領域に達すると共に外方に向かって広がるように内
壁面が傾斜している接続孔を形成する第1の工程と、 前記接続孔を形成した後に、バリアメタル層と金属層と
を順次に積層させる第2の工程と、 前記金属層及び前記バリアメタル層を前記接続孔の底部
上にのみ残す第3の工程と、 前記底部上にのみ残した前記金属層及び前記バリアメタ
ル層と前記内壁面との間を第2の絶縁膜で埋める第4の
工程とを有することを特徴とする半導体装置の製造方
法。
1. A first step of forming, in a first insulating film on a conductive region, a connection hole whose inner wall surface is inclined so as to reach the conductive region and spread outward. A second step of sequentially laminating a barrier metal layer and a metal layer after forming the connection hole, and a third step of leaving the metal layer and the barrier metal layer only on the bottom of the connection hole, And a fourth step of filling a space between the metal layer and the barrier metal layer left only on the bottom and the inner wall surface with a second insulating film.
【請求項2】 前記底部上にのみ残した前記金属層及び
前記バリアメタル層と前記内壁面との間を液状の絶縁性
材料で埋め、この液状の絶縁性材料を固化させて前記第
2の絶縁膜を形成することを特徴とする請求項1に記載
の半導体装置の製造方法。
2. A liquid insulating material is filled between the metal layer and the barrier metal layer left only on the bottom and the inner wall surface, and the liquid insulating material is solidified to form the second insulating material. The method of manufacturing a semiconductor device according to claim 1, wherein an insulating film is formed.
JP25572792A 1992-08-31 1992-08-31 Method of manufacturing semiconductor device Withdrawn JPH0684910A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25572792A JPH0684910A (en) 1992-08-31 1992-08-31 Method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25572792A JPH0684910A (en) 1992-08-31 1992-08-31 Method of manufacturing semiconductor device

Publications (1)

Publication Number Publication Date
JPH0684910A true JPH0684910A (en) 1994-03-25

Family

ID=17282800

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25572792A Withdrawn JPH0684910A (en) 1992-08-31 1992-08-31 Method of manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0684910A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404058B1 (en) 1999-02-05 2002-06-11 Nec Corporation Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6404058B1 (en) 1999-02-05 2002-06-11 Nec Corporation Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991102