JPH0683290A - Display control device - Google Patents

Abstract

PURPOSE:To shorten processing time of display control when display control of a ferroelectric liquid crystal display device having a storing characteristic of a display state is performed using a display control circuit for a CRT. CONSTITUTION:When display data is read out from a VRAM to a display control circuit and it is requested to transfer to FLCD side, a format of a line address data is made as the following shown in Fig. (A). Next 6 bits of a start bit are made '0', next requested 8 bits are made '1', and next n bits are made '0'. Thereby, address data of 8 lines for reading and transferring can be sent with a block unit, and reading and transferring also can be performed with a block unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device,
More specifically, the present invention relates to a display control device for a display device that includes a display element that can maintain a display state updated by applying an electric field or the like using a ferroelectric liquid crystal as an operation medium for display update.

[0002]

2. Description of the Related Art In information processing systems and the like, a display device is used as an information display means having a function of visually expressing information. As such a display device, a CRT display device (hereinafter, simply referred to as CRT) is generally used. Target.

There are various types of information processing systems available as so-called personal computers depending on the hardware, software, signal transmission system, etc. used therein. In this case, the display control device (CRTC) of the CRT is also unique to each system. As such a CRTC, for example, a VGA (Vi
VG as a Deo Graphics Array)
A81 (by IBM) or 86C as SVGA (Super VGA) with an accelerator function etc. added when displaying a predetermined image such as a circle or rectangle.
911 (according to S3 company) is known.

FIG. 1 is a block diagram showing an example of a configuration using SVGA for CRTC.

When the host CPU of the information processing system rewrites a part of the display memory window area in the host side memory space, the rewritten display data is transferred to the VRAM 3 via the system bus 40 and the SVGA 1. The SVGA 1 generates a VRAM address based on the address of the display memory window area,
In 3, the display data specified by this VRAM address is rewritten.

On the other hand, the SVGA1 accesses the VRAM3 in the same cycle as the scanning cycle in the CRT, and the VRAM3
The display data that is expanded to are sequentially read, and RAMDAC2
Transfer to. The RAMDAC 2 sequentially converts the display data into R, G, B analog signals and transfers them to the CRT 4. Thus, the SVGA used as the display control device for the CRT functions to unilaterally transfer the display data to the CRT side at a predetermined cycle.

In the case of the above-mentioned CRT display control, VRAM
Since 3 is a dual port RAM, writing of display data to the VRAM for changing display information and the like, and operation of reading the display data from the VRAM and displaying the data can be performed independently of each other. For this reason,
The host CPU has an advantage that desired display data can be written at any timing without any consideration of display timing and the like.

However, since the CRT requires a certain length in the thickness direction of the display screen, the volume of the CRT becomes large as a whole, and it is difficult to reduce the size of the entire display device.
In addition, the degree of freedom in using an information processing system that uses such a CRT as a display is also improved.
That is, the degree of freedom in installation location, portability, etc. is impaired.

A liquid crystal display (hereinafter referred to as LCD) can be used as a display device that compensates for this point. That is, according to the LCD, it is possible to reduce the size (in particular, reduce the thickness) of the entire display device. In such LCD,
Ferroelectric liquid crystal (hereinafter, FLC: Ferroelectric
There is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of ic Liquid Crystal), and one of the features is that the liquid crystal cell has a storage state of a display state against the application of an electric field. It is in. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and excluding the electric field. However, each alignment state is maintained. Due to the bistability of the FLC molecule, the FLCD
Has memory. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357.

Although the FLCD has the above-mentioned memory property, the display update operation of the FLC is relatively slow, and therefore, for example, cursor movement, character input, scrolling, etc.
In some cases, it is not possible to follow the change in the display information that requires the display to be immediately rewritten.

An FLCD having such contradictory characteristics
Are derived from these characteristics or supplement these characteristics, so that various driving modes for display thereof are possible. That is, in the refresh driving in which the scanning lines on the display screen are sequentially and continuously driven like the CRT and other liquid crystal display devices, a relatively long margin can be provided in the driving cycle. In addition to this refresh driving, partial rewriting driving for updating the display state of only a portion (line) corresponding to a change on the display screen and interlaced driving for driving by thinning out scanning lines on the display screen are possible. Then, the partial rewriting drive and the interlace drive can improve the followability to the change of the display information.

If the display control of the FLCD having the above advantages can be performed by using the existing CRT dedicated display control circuit, an information processing system using the FLCD as a display device can be constructed at a relatively low cost. It is advantageous.

[0013]

An object of the present invention is to provide a display control device which can control the display of an FLCD satisfactorily and which has a high processing speed by utilizing a display control circuit for a CRT.

[0014]

Therefore, according to the present invention,
In a display control device of a display device capable of updating a display state only for a display element associated with a display change, a display data storage unit storing display data and a display data stored in the storage unit A display control circuit that can be sequentially read and transferred to the display device at regular intervals and that can partially rewrite the display data stored in the storage means; and a display control circuit for rewriting the display data. Further, a rewrite detecting means for detecting an address to be accessed in the display data storage means, an address detected by the rewrite detecting means are read, and only the read address and the display data of the address are transferred to the display control circuit. Transfer permission means for transmitting a permission signal, the transfer permission means for transmitting the read address in block units. That.

[0015]

According to the above structure, when the display control circuit is allowed to read and transfer the display data, it is possible to send the addresses of the plurality of display data for the reading in block units.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 2 is a block diagram of an information processing system in which an FLC display device having a display control device according to an embodiment of the present invention is used as a display device for displaying various characters and image information.

In the figure, reference numeral 21 is a CPU for controlling the entire information processing system, 22 is a ROM for storing a program executed by the CPU 21, and 28 is a main memory used as a work area or the like for executing the program. is there. Reference numeral 14 is a DMA controller (Direct Me) that transfers data between the main memory 28 and various devices constituting this system without going through the CPU 21.
(more access controller, hereinafter referred to as DMAC). 32 is Ethernet (XER
It is a LAN interface between a LAN (Local Area Network) 37 such as OX Company and this system. Reference numerals 26 and 27 are a hard disk device and its interface and a floppy disk device and its interface as external storage devices, respectively. 36 is a printer which can be constituted by an ink jet printer, laser beam printer or the like capable of relatively high resolution recording, 31 is a parallel interface for making a signal connection between the printer and this system, and 29 is A keyboard and a controller for inputting character information such as various characters and control information. 33 is a communication modem for performing signal modulation between the communication line and the system of this example, 34 is a mouse as a pointing device, 35 is an image scanner for reading images, etc. Example Exchange signals with the system. The interrupt controller 24 controls interrupt processing in program execution, and the real-time clock 25
Controls the timekeeping function in this system. Reference numeral 20 denotes an F display whose display is controlled by the FLCD interface 10 as a display control device according to an embodiment of the present invention.
It is an LC display device (also called FLCD), and has a display screen using the above-mentioned ferroelectric liquid crystal as its display operation medium.
A display memory window area accessible by the CPU 21 is also expanded in the FLCD interface 10. Reference numeral 40 is a system bus composed of a data bus, a control bus, and an address bus for connecting signals between the above-mentioned devices.

In the information processing system in which the various devices described above are connected, generally, the system user is
The operation is performed while responding to various information displayed on the display screen of the FLCD 20. That is, the external device connected to the LAN 37, the hard disk 26, the floppy disk 27, the scanner 35, the characters supplied from the keyboard 29, the mouse 34, image information, and the main memory 2
The operation information related to the user's system operation stored in 8 is displayed on the display screen of the FLCD 20, and the user edits the information and gives an instruction operation to the system while watching this display. Here, the above various devices are
A display information supply unit is configured for the LCD 20.

First Embodiment FIG. 3 is a block diagram showing details of the FLCD interface 10 according to the first embodiment of the present invention.

As shown in the figure, the FLCD interface 10 of this embodiment, that is, the display control device, uses an existing SVGA which is a display control circuit for a CRT.
A1 is used. The configuration of the SVGA 1 of this example will be described with reference to FIG.

In FIG. 4, the rewrite display data that the host CPU 21 (see FIG. 2) accesses for writing in the display memory window area of the FLCD interface 10 (see FIG. 2) is transferred via the system bus 40, It is temporarily stored in the FIFO 101. Also,
Bank address data for projecting the display memory window area onto an arbitrary area of the VRAM 3 is transferred to the system bus 4
Transferred via 0. The display data has a form of 24-bit data representing 256 gradations of R, G and B colors. Further, the control information such as the command from the CPU 21 and the above-mentioned bank address data is transferred in the form of register set data, and the register get data is transferred to the CPU 21 side for the CPU 21 to know the state of the SVGA side. The resist set data and display data stored in the FIFO 101 are sequentially output, and the bus interface unit 103 and VGA are output according to these data.
It is set in each register in 111. The VGA 111 can know the bank address, its display data and the control command depending on the set state of these registers.

The VGA 111 generates a VRAM address in the VRAM 3 corresponding to the address of the display memory window area and the bank address,
At the same time, the strobe signals RAS and CAS as the memory control signals, the chip select signal CS, and the write enable signal WE are transferred to the VRAM 3 via the memory interface unit 109, whereby the display data is written to the VRAM address. be able to. At this time, the display data to be rewritten is similarly VRA via the memory interface unit 109.
Transferred to M3.

On the other hand, the VGA 111 is a VRAM specified by a requested line address transferred from the line address generation circuit 7 (see FIG. 3), as will be described later.
The display data of No. 3 is read from the VRAM 3 in accordance with the line data transfer enable signal similarly transferred, and the FIF
Store in O113. From the FIFO 113, the display data is sent to the FLCD side in the order in which the display data was stored.

The SVGA 1 is provided with the data manipulator 105 and the graphics engine 107 that fulfill the accelerator function as described above. For example, when the CPU 21 sets a circle and its center and radius data in the register of the bus interface 103 and instructs drawing of the circle, the graphics engine 10
7 generates the circle display data, and the data manipulator 105 writes this data in the VRAM 3.

The SVGA1 described above with reference to FIG.
Is obtained by making a slight modification to the VGA portion of the existing SVGA for CRT.

Referring again to FIG. 3, the rewrite detection / flag generation circuit 5 monitors the VRAM address generated by the SVGA 1, and the VRAM address when the display data of the VRAM 3 is rewritten (written), that is, a write operation. The VRAM address when the enable signal and the chip select signal CS become "1" is fetched. Then, this VRAM address and the VRA obtained from the CPU 9
A line address is calculated based on each data of M address offset, total line number, and total line bit number. The concept of this calculation is shown in FIG.

As shown in FIG. 5, the pixel indicated by the address X on the VRAM 3 corresponds to the line N of the FLCD screen, one line is composed of a plurality of pixels, and one pixel is composed of a plurality of pixels. It shall consist of (n) bytes. At this time, the line address (line number N)
Is calculated as follows:

[0029]

[Equation 1]

The rewrite detection / flag generation circuit 5 sets a partial rewrite line flag register provided therein according to the calculated line address. This state is shown in FIG.
Shown in.

As is apparent from FIG. 6, when the display of the corresponding address on the VRAM 3 is rewritten in order to display the character "L", for example, the rewritten line address is detected by the above calculation, and this address is detected. A flag is set in the corresponding register (“1” is set).

The CPU 9 reads the contents of the rewrite line flag register of the rewrite detection / flag generation circuit 5 via the line address generation circuit 7 and sends the line address in which the flag is set to the SVGA 1. At this time, the line address generation circuit 7 sends a line data transfer enable signal corresponding to the line address data, and S
The display data of the above address is transferred from the VGA 1 (FIFO 113 thereof) to the binarization halftone processing circuit 11.

The binarization halftone processing circuit 11 includes R, G, B
The multi-value display data of 256 gradations represented by 8 bits for each color is converted into binary pixel data corresponding to each pixel on the display screen of the FLCD 20. In this example, one pixel of the display screen has display cells having different areas for each color as shown in FIG. Accordingly, the data for one pixel also has 2 bits (R1, R2, G1, G2, B1, B2) for each color, as shown in FIG. Therefore, the binarization halftone processing circuit 11 converts 8-bit display data into 2-bit binary data of each color (that is, 4-value data of each color).

FIG. 9 shows the flow of data until the pixel data for FLCD display is converted as described above.

As is apparent from FIG. 9, in this example, VRA
The display data of M3 is stored as multi-valued data of 8 bits for each color of R, G and B, and is binarized when these are read out and displayed. As a result, the host CPU 21 (see FIG. 2) can access the FLCD 20 side as in the case of using a CRT, and can ensure compatibility with the CRT.

A known method can be used as the method used in the binarization and halftone processing. As such a method, for example, an error diffusion method, an average density method, a dither method, etc. are known. There is.

In FIG. 3, the border generation circuit 13 is
The pixel data of the border portion on the FLCD display screen is generated. That is, as shown in FIG.
The display screen of 0 has 10 lines per line consisting of 1280 pixels.
There are 24 lines, and a border portion of this display screen that is not used for display is formed so as to frame the display screen.

Due to the existence of this border portion, F
The format of the pixel data transferred to the LCD 20 is
It becomes what is shown in FIG. 8 (A) or FIG. 8 (B). Figure 8
7A shows the data format of the display line A shown in FIG. 7, that is, the display line in which all the display lines are included in the border portion, and FIG. 8B shows the display line B shown in FIG. This is the data format of the line used. The data format of display line A is
A line address is added to the beginning, and this is followed by border pixel data. On the other hand, since both ends of the display line B are included in the border portion, the data format thereof follows the line address, followed by border pixel data, pixel data, and border pixel data in this order.

The border pixel data generated by the border generation circuit 13 is serially synthesized by the synthesis circuit 15 with the pixel data from the binarization halftone processing circuit 11. Further, the combined line 17 is combined with the display line address from the line address generation circuit 7 in the combined circuit 17 and then sent to the FLCD 20.

The CPU 9 controls the entire configuration described above. That is, the CPU 9 is the host CPU 2
1 (see FIG. 2), the total number of lines on the display screen, the total number of line bits, and cursor information are received. Also, CP
U9 sends VRA to the rewrite detection / flag generation circuit 5.
The M address offset, the total number of lines, and the total number of line bits are transmitted, the line flag register is initialized, and the line address generation circuit 7 receives a display start line address, a continuous display line number, The total number of lines, the total number of line bits, and the data of the border area are transmitted, and the partial rewriting line flag information is obtained from the circuit 7. Further, the CPU 9 sends each data of the bandwidth, the total number of line bits and the processing mode to the binarization halftone processing circuit 11 and sends the border pattern data to the border generation circuit 13.

Further, the CPU 9 receives the temperature information and status signals such as a Busy signal from the FLCD 20, and sends a command signal and a reset signal to the FLCD 20.

In the above structure, the requested line address sent from the line address generation circuit 7 to the SVGA 1 is sent for each block. The transmission of the request line address will be described below.

FIG. 10 is a diagram schematically showing the display screen of the FLCD 20. The figure shows the case where the display line is not rewritten on the 6th line from the top of the display screen, the 8th line from the 7th line is rewritten, and the subsequent lines are not rewritten.

At this time, the line address generation circuit 7 outputs S
The data format of the request line address transferred to the VGA 1 is shown in FIG. As shown in the figure, this data first has a start bit indicating that it is the beginning of the data. In this start bit, the predetermined number a is "0" and the predetermined number b is "1". After this start bit, the 6 bits corresponding to the 6 lines where rewriting is not performed are "0", the 8 bits corresponding to the 8 lines where the next rewriting is performed are "1", and the remaining rewriting is further performed. The non-existing n bits become "0".

FIG. 11B is a schematic diagram showing another example of the data format of the request line address shown in FIG. 11A. In this example, a code corresponding to a predetermined number of lines for the communication method is sent after the start bit.
That is, first, the code corresponding to the line number 6 for which rewriting is not performed is transmitted, then the code corresponding to the line number for rewriting 8 is transmitted, and the code corresponding to the line number n for which rewriting is not performed is further transmitted.

More specifically, in this format, the number indicated by the first code after the start bit indicates the number of lines that are not rewritten, and the number indicated by the next code indicates the number of lines that are rewritten. Therefore, when rewriting from the first line of the FLCD screen, the number indicated by the code to be sent first may be set to zero.

FIGS. 12A and 12B are views showing two examples of data formats when there are two rewriting portions in the FLCD screen.

In FIG. 12A, as in FIG. 11A, the number of bits of "0" indicates the number of lines that are not rewritten, and the bit of "1" indicates the bits that are rewritten.

The data format shown in FIG. 12B is the same as that shown in FIG. 11B, but the number indicated by the first code after the start bit is the number of portions to be rewritten, that is, rewriting. This shows the number of blocks in the line. In this example, two blocks are rewritten, so a code indicating 2 is sent. The code sent after this code indicates the number of lines from which rewriting is not performed on the FLCD screen, as in FIG. 11B, and "8" indicated by the next code indicates the number of rewriting lines. Similarly, “12” indicated by the next code indicates the number of lines that are not rewritten, and “10” indicated by the next code indicates the number of lines that are rewritten.

According to the data format of the requested line address shown above, the following effects can be obtained as compared with the conventional data format.

FIGS. 13A and 13B are explanatory views showing the address request of the present example and the conventional example and the state of data transfer in response thereto, respectively.

In the conventional example shown in FIG. 13B, in order to obtain the display data of a certain rewriting block, the address data is sent out for each line and the display data is obtained accordingly. According to this, the S that received the address data
Since the VGA accesses the VRAM line by line and reads the display data and transfers the display data to the FLCD side, the time from the address data transmission to the display data transfer for all the rewriting lines becomes relatively long.

On the other hand, according to the data format of this example, as shown in FIG. 13A, all the rewriting line address data is sent in blocks, and the display data is read by the SVGA in response to this. And, the transfer can be continuously performed in block units. Therefore, compared with the conventional example, the time from the address data transmission to the display data transfer becomes shorter.

[0054]

As is apparent from the above description, according to the present invention, when the display control circuit is allowed to read and transfer the display data, the addresses of the plurality of display data for the reading are block by block. Can be sent.

As a result, the time required to access the display data storage means to read the display data and transfer it to the display device side can be shortened, and a display control device having a high processing speed can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a conventional display control device.

FIG. 2 is a block diagram showing an information processing system according to an embodiment of the present invention.

FIG. 3 is a block diagram showing a display control device according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing details of the SVGA shown in FIG.

FIG. 5 is a schematic diagram for explaining conversion from a VRAM address to a line address in the embodiment of the present invention.

FIG. 6 is a schematic diagram showing a relationship between a rewriting display pixel and a rewriting line flag register in the embodiment of the present invention.

FIG. 7 is a schematic view showing an FLCD display screen in the embodiment of the present invention.

8A and 8B are schematic diagrams showing a data format of display data in the embodiment of the present invention.

FIG. 9 is a block diagram showing a flow of processing of display data in the embodiment of the present invention.

FIG. 10 is a schematic diagram of an FLCD display screen used for explaining a format of line address data according to an embodiment of the present invention.

11A and 11B are explanatory diagrams showing two examples of the data format.

12A and 12B are explanatory diagrams showing two examples of the data format according to another embodiment.

13A and 13B are explanatory diagrams for comparing the line address transfer of the present example and the conventional line address transfer.

[Explanation of symbols]

 1 SVGA 3 VRAM 5 Rewrite Detection / Flag Generation Circuit 7 Line Address Generation Circuit 9 CPU 10 FLCD Interface 11 Binary Halftone Processing Circuit 13 Border Generation Circuit 15, 17 Synthesis Circuit 20 FLCD 21 CPU / FPU 101, 103 FIFO 103 Bus Interface unit 105 Data manipulator 107 Graphics engine 109 Memory interface unit 111 VGA

Front page continued (72) Inventor Kenichiro Ono 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Masami Shimakura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Eiichi Matsuzaki 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc.

Claims (1)

[Claims] 1. A display control device of a display device capable of updating a display state only for a display element associated with a display change, and a display data storage unit storing display data, and a display data storage unit stored in the storage unit. A display control circuit capable of sequentially reading display data at a predetermined cycle and transferring the display data to the display device, and partially rewriting the display data stored in the storage means, and the display control circuit. A rewriting detection means for detecting an address accessed by the display data storage means for the rewriting, an address detected by the rewriting detection means, and a display of the read address and the address on the display control circuit. Transfer permission means for transmitting a signal for permitting the transfer of only data, the transfer permission means for transmitting the read address in block units. Display control device, characterized in that the.