JPH0677400B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial field of application> The present invention relates to a serial circuit including a plurality of selected circuits and a plurality of cascade-connected selectors that sequentially output selection signals to the plurality of selected circuits. A selector circuit, in which each stage selector receives the activation signal from the preceding stage selector, is activated by the activation signal, outputs the selection signal, and outputs the activation signal to the latter stage selector. The present invention relates to a semiconductor integrated circuit device having a selector circuit, and particularly to a semiconductor integrated circuit device provided with means for replacing a defective selected circuit with a normal selected circuit.

<Prior Art> First, a configuration of a conventional semiconductor integrated circuit device will be described in detail by taking a case of a DRAM as an example.

FIG. 8 is a block diagram of a conventional DRAM.

In the figure, MA 'is a memory cell array, RD' is a row decoder, SA 'is a sense amplifier, DH' is a data holding circuit,
T _'1, ..., T'n the N-channel MOS transistor, IO' is I
/ O ports, SS 'is, s' the MOS transistor T based on a ₀ signal input _'1, ..., a selection signal s are sequentially turned on T'n' _1, ..., and outputs the S'n, cascaded n number of selectors S _'1, ..., a serial selector circuit consisting S'n (column selector). The configuration of each of the above selectors is shown in FIG. In the figure, CK 'is a clock signal and RST' is a reset signal.

Data read in 'data holding circuit DH from' a memory cell array MA, 'selection signal s outputted from' ₁ serial selector circuit SS, ..., by S'n, sequential I / O ports IO ' Is output to. Further, I / O ports IO 'data sequentially input from the serial selector circuit SS' selection signals s _'1, ..., by S'n, sequential data holding circuit DH' output from the input to, are retained , And then written to the memory cell array MA '.

<Problems to be Solved by the Invention> The conventional semiconductor integrated circuit device has been described by taking a DRAM as an example. However, in the conventional semiconductor integrated circuit device, even one of the plurality of selected circuits is defective. If the selected circuit exists, the device becomes a defective product. In the case of the conventional DRAM, if there is _I 'defective memory cell M in 1 bit in the' memory cell array MA, the DRAM becomes defective.

The present invention has been made in view of the above conventional problems, and even if a defective selected circuit exists among a plurality of selected circuits, the defective selected circuit can be replaced with a normal selected circuit. The purpose of this structure is to reduce the defect occurrence rate, improve yield, and reduce costs.

<Means for Solving Problems> A serial selector circuit including a plurality of selected circuits and a plurality of cascade-connected selectors that sequentially output selection signals to the plurality of selected circuits, each stage comprising: The selector is a semiconductor integrated circuit having a serial selector circuit configured to receive an activation signal from the preceding stage selector, activate the activation signal to output the selection signal, and output the activation signal to the succeeding stage selector. In the circuit device, the preselected circuit and the final stage selector of the serial selector circuit are cascade-connected, and the preselected circuit is activated by an activation signal from the final stage selector to select the preselected circuit. Is provided with a spare selector having the same configuration as that of each stage selector of the serial selector circuit for outputting the fuse link and the fuse link. By cutting
A switching control circuit that inhibits the activation of the selector by the activation signal from the preceding stage selector and short-circuits the activation signal from the preceding stage selector to the latter stage selector is provided in each stage selector that constitutes the serial selector circuit. At the same time, the spare link is provided with a fuse link and a switching control circuit for enabling activation by an activation signal input from the final stage selector of the serial selector circuit by cutting the fuse link.

<Operation> By disconnecting the fuse link of the selector corresponding to the defective selected circuit, the selector is skipped.
As a result, the selection signal output to the defective selected circuit is prohibited and the circuit is deselected. On the other hand, by cutting the fuse link of the spare selector, the inactive spare selector is activated. by this,
The preselected circuit which has been prohibited from being selected is selected, and the non-selection of the defective selected circuit is compensated.

<Examples> Hereinafter, the present invention will be described in detail based on Examples.

FIG. 2 is a block diagram of a DRAM which is an embodiment of the present invention.
Figure 1 shows the serial selector circuit in the same DRAM.
It is a block diagram of SS. In FIG. 1, CK is a clock signal and RST is a reset signal.

In FIG, MA is a memory cell array, MC _R is spare memory cell columns included in the memory cell array MA, RD row decoder, SA a sense amplifier, DH is the data holding circuit, T _1, ...,
Tn, T _R is N-channel MOS transistor, IO is the I / O port. N number of selectors S ₁ SS is connected in cascade, ..., a Shishiriaru selector circuit consisting of Sn and preliminary selector S _R (column selector). When the fuse links F ₁ , ..., Fn and F _{R in} each of the selectors S ₁ , ..., Sn and S _R are not cut, the serial selector circuit SS receives the s ₀ signal based on the s ₀ signal input. transistor T _1, ..., a selection signal s ₁ for sequentially turning on the Tn, ..., and outputs the sn. In this case, the spare selector S _R
There is no selection signal output from. _One of the fuse links F ₁ , ..., Fn in each of the selectors S ₁ , ..., Sn and the fuse link F _R in the spare selector S _R is disconnected, and all other fuse links are not disconnected. , The serial selector circuit SS selects the selection signal s ₁ for sequentially turning on the MOS transistors T ₁ , ..., Tk ₋₁ , Tk ₊₁ , ..., Tn, T _R based on the s ₀ signal input. ,, sk _-1 ,, sk ₊₁ , ..., sn, s _R are output. in this case,
There is no selection signal output from the selector Sk.

When the defective memory cell M _I exists at the position shown in FIG. 2, the fuse link F ₃ of the selector S ₃ corresponding to the memory cell column MC _I to which the defective memory cell belongs is cut off. Also, the fuse link F _R of the pre-selector S _R. As a result, the selection signal output becomes s ₁ → s ₂ → s ₄ → ... → sn → s _R , the memory cell column MC _I to which the defective memory cell M _I belongs is skipped, and instead, the spare memory cell column MC _R will be selected.

In the case of a DRAM that is also serially accessed in the row direction, a spare memory cell row may be provided, and a circuit having the same configuration as the serial selector circuit SS may be provided as a row decoder.

Next, a second embodiment will be described.

FIG. 3 is a serial selector circuit according to the second embodiment.
It is a block configuration diagram of SS. Further, FIGS. 4 and 5 show selectors Si (i = 1, ..., N) and spare selectors s _R j (j = 1, 2) that form the serial selector circuit SS, respectively.
It is a block diagram of. In the figure, CL and ▲ ▼ are clock signals. The MOS transistors shown in FIGS. 4 and 5 are all N-channel MOS transistors.

Said each selector S _1, ..., fuse links F ₁ of Sn and during the pre-selector S _R1, S _R2, ..., when all the Fn and F _R1, F _R2 is a non-disconnected, the serial selector circuit SS is, s Based on the ₀ signal input, selection signals s ₁₁ , ..., Sn ₂ whose phases are sequentially shifted are output. In this case, there is no selection signal output from the spare selectors S _R1 and S _R2 .

The time chart at this time is shown in FIG.

Said each selector S _1, ..., fuse links F ₁ in Sn, ..., one Fk and fuse link during the preliminary selector S _R1 or S _R2 F _R1 or F _R2 are disconnected among the Fn, other Serial selector circuit when all fuse links are unbroken
SS is a selection signal whose phase is sequentially shifted based on the s ₀ signal input
s ₁₁ , s ₁₂ , ..., s ₍ k _{-1) 1} , s ₍ k _{-1) 2} , s ₍ k _{+1) 1} , s ₍ k _{+1) 2} , ・ ・ ・, sn ₁ ,
Output sn ₂ , s _R11 (or s _R21 ), s _R12 (or s _R22 ).
In this case, the selector Sk and the spare selector S _R2 (or S _R1 )
There is no selection signal output from.

Fuse links in the selector S ₂ F ₂ and the preliminary selector S _R1
FIG. 7 shows a time chart when the fuse link F _{R1 in the} inside is blown.

<Effect of the Invention> As described in detail below, according to the present invention, even if a defective selected circuit exists in a plurality of selected circuits, the defective selected circuit can be replaced with a normal selected circuit. This makes it possible to reduce the defect occurrence rate, improve the yield, and reduce the cost.

[Brief description of drawings]

1 is a circuit configuration diagram, FIG. 2 is a block diagram, FIG. 3 is a block diagram, FIG. 4 is a circuit configuration diagram, and FIG. 5 is a circuit configuration diagram.
FIG. 6 is a time chart, FIG. 7 is a time chart, FIG. 8 is a block diagram, and FIG. 9 is a circuit configuration diagram. REFERENCE NUMERALS MA: a memory cell array, MC _R: spare memory cell columns, M _I: defective memory cell, RD: row decoder, SA: a sense amplifier, DH:
Data holding circuit, T ₁ , ..., Tn, T _R : N-channel MOS transistor, IO: I / O port, SS: Serial selector circuit, S ₁ ,
…, Sn: Selector, S _R , S _R1,, S _R2 : Spare selector, F ₁ ,…, Fn,
F _R , F _R1 , F _R2 : Fuse link, s ₁ , ..., sn, s _R : Selection signal, s
₁₁ , ..., sn ₂ , s _R11 , ..., s _R22 : Selection signal.

Claims (1)

[Claims] 1. A serial selector circuit comprising a plurality of selected circuits and a plurality of cascade-connected selectors for sequentially outputting selection signals to the plurality of selected circuits, each stage selector being a preceding stage selector. A serial selector circuit configured to receive an activation signal from the second selector, output the selection signal by being activated by the activation signal, and output the activation signal to the subsequent stage selector. A preliminary selected circuit and a final stage selector of the serial selector circuit, which are cascade-connected and output a selection signal to the preliminary selected circuit by being activated by an activation signal from the final stage selector. A spare selector having the same configuration as that of each stage selector of the serial selector circuit is provided. A switching control circuit that inhibits activation of the selector by an activation signal from the selector and short-circuits the activation signal from the preceding stage selector to the latter stage selector is provided in each stage selector that constitutes the serial selector circuit. A fuse link and a switching control circuit for enabling activation by an activation signal input from a final stage selector of the serial selector circuit by disconnecting the fuse link, are provided in the spare selector. Integrated circuit device.