JPH0669082B2 - Semiconductor memory cell - Google Patents
Semiconductor memory cellInfo
- Publication number
- JPH0669082B2 JPH0669082B2 JP60058905A JP5890585A JPH0669082B2 JP H0669082 B2 JPH0669082 B2 JP H0669082B2 JP 60058905 A JP60058905 A JP 60058905A JP 5890585 A JP5890585 A JP 5890585A JP H0669082 B2 JPH0669082 B2 JP H0669082B2
- Authority
- JP
- Japan
- Prior art keywords
- memory cell
- wiring
- side wiring
- pair
- control electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims description 19
- 239000010410 layer Substances 0.000 description 48
- 238000002955 isolation Methods 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 9
- 230000010354 integration Effects 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】 〔概要〕 SRAM（スタティックランダムアクセスメモリ）のメモリ
セルのＶss配線は、従来ｐ型基板内に形成されたn+型活
性層を用いていた。DETAILED DESCRIPTION OF THE INVENTION [Outline] The V ss wiring of a memory cell of SRAM (Static Random Access Memory) conventionally uses an n + type active layer formed in a p type substrate.
本発明では、Ｖss配線を半導体基板上の第２層目に形成
し、Ｖcc配線及びメモリセルの負荷素子を第３層目に形
成する。この負荷素子はメモリセルの駆動トランジスタ
の制御電極上にレイアウトされているが、Ｖss配線をコ
ンタクトホールを介して駆動トランジスタのソース領域
に接続する際、Ｖss配線を第２層目に形成しておくと、
Ｖss配線よりあとに形成されるＶcc配線及び負荷素子と
の位置合わせ余裕を考慮する必要はない。In the present invention, the V ss wiring is formed on the second layer on the semiconductor substrate, and the V cc wiring and the load element of the memory cell are formed on the third layer. This load element is laid out on the control electrode of the driving transistor of the memory cell, when connecting the V ss line to the source region of the drive transistor through the contact hole, forming a V ss line for the second layer If you keep
It is not necessary to consider the alignment margin with the V cc wiring formed after the V ss wiring and the load element.
また、従来のごとくＶss配線を基板内に形成された不純
物活性層を利用している場合、隣り合っているメモリセ
ルの間隔は、 素子間分離領域の幅＋n+活性層の幅＋素子間分離領域の
幅 となり、大きな面積を必要としたが、本発明によればＶ
ss配線を基板上に被着された導電層を用いて行うことに
より、上記の間隔は、 素子分離領域の幅 のみでよく、高集積化を可能とする半導体メモリセルが
得られる。Further, when the impurity active layer formed in the substrate is used for the V ss wiring as in the conventional case, the distance between the adjacent memory cells is calculated by: the width of the isolation region between elements + n + the width of the active layer + the distance between the elements. The width of the isolation region is large and a large area is required.
By performing the ss wiring by using the conductive layer deposited on the substrate, the above-mentioned interval may be only the width of the element isolation region, and a semiconductor memory cell capable of high integration can be obtained.
本発明はSRAMのメモリセルのＶss配線構造に関する。The present invention relates to a V ss wiring structure of a memory cell of SRAM.
SRAMはDRAM（ダイナミックランダムアクセスメモリ）よ
り同一チップサイズに対する記憶容量は小さいが、各種
機器に広く使用され、これらのシステムの大規模化にと
もない、DRAM同様年々集積度が増している。Although SRAM has a smaller storage capacity for the same chip size than DRAM (Dynamic Random Access Memory), it is widely used in various devices, and with the increase in the scale of these systems, the degree of integration is increasing year by year like DRAM.
そのため、高密度化、高集積化のための試みが種々なさ
れている。Therefore, various attempts have been made to increase the density and integration.
第２図（１），（２）はそれぞれSRAMセルの回路図と、
従来例による平面図である。2 (1) and 2 (2) are circuit diagrams of SRAM cells,
It is a top view by a prior art example.
第２図（１）において、Ｖccは電源電位、Ｖssは接地電
位、Q1,Q2,Q3,Q4はトランジスタ、Ｒは負荷抵抗、WLは
ワード線、BLはビット線である。In FIG. 2 (1), V cc is a power supply potential, V ss is a ground potential, Q 1 , Q 2 , Q 3 , and Q 4 are transistors, R is a load resistance, WL is a word line, and BL is a bit line. .
図はSRAMセルの典型的な回路例で４トランジスタ２抵抗
で構成されている。The figure shows a typical circuit example of an SRAM cell, which is composed of 4 transistors and 2 resistors.
第２図（２）において、21はトランジスタのゲートで左
下がりの斜線を施した領域で示され、多結晶珪素（ポリ
Si）よりなる第１の導電層（ポリSi Ａ層）である。In FIG. 2 (2), reference numeral 21 designates a gate of the transistor, which is indicated by a diagonally downward-sloping region.
It is a first conductive layer (poly-SiA layer) made of Si).
22は負荷抵抗Ｒ、およびＶcc配線層で点線で囲まれた領
域で示され、ポリSiよりなる第２の導電層（ポリSi Ｂ
層）である。 Reference numeral 22 designates a region surrounded by a load resistance R and a Vcc wiring layer surrounded by a dotted line, and includes a second conductive layer made of poly Si (poly Si B
Layer).
23はＶss配線層で右下がりの斜線を施した領域で示さ
れ、ｐ型基板内に形成されたn+型活性層である。 Reference numeral 23 denotes a V ss wiring layer, which is shown by a diagonally downward-sloping region, and is an n + -type active layer formed in the p-type substrate.
アルミニウム（A1）よりなるビット線BLは鎖線で囲まれ
た領域で示され、コンタクトホール24でn+型活性層23と
接続される。The bit line BL made of aluminum (A1) is shown by a region surrounded by a chain line, and is connected to the n + type active layer 23 through the contact hole 24.
図示Ａ−Ａ′は本発明の対象とする領域で、メモリセル
と、となりのメモリセルとの間隔を含み、この領域内に
Ｖss配線層を配設している。つぎの第３図にこの領域の
み抽出して示す。AA 'in the figure is a target area of the present invention, which includes a space between a memory cell and a neighboring memory cell, and the V ss wiring layer is arranged in this area. Only this area is extracted and shown in FIG.
第３図（１）乃至（３）はそれぞれ従来例によるSRAMセ
ルのＶss配線の平面図、Ａ−Ａ′断面図、Ｂ−Ｂ′断面
図である。3 (1) to 3 (3) are a plan view, an AA ′ sectional view, and a BB ′ sectional view of the V ss wiring of the SRAM cell according to the conventional example, respectively.
図において、1Aは素子間分離領域のフィールド酸化膜で
ある。In the figure, 1A is a field oxide film in the element isolation region.
第３図の従来例における、メモリセル間の間隔は、 素子間分離領域の幅（ａ） ＋n+型活性層の幅（ｂ） ＋素子間分離領域の幅（ａ）． となる。In the conventional example of FIG. 3, the space between the memory cells is defined by the width of the element isolation region (a) + the width of the n + active layer (b) + the width of the element isolation region (a). Becomes
すなわち、Ｖss配線を基板内に形成されたn+型活性層を
導電層として用いると、その両側にフィールド酸化膜を
形成するため、セル間の間隔に大きな面積を必要とし
た。That is, when the n + type active layer formed by using the V ss wiring in the substrate is used as a conductive layer, a field oxide film is formed on both sides of the active layer, so that a large area is required for the interval between cells.
上記問題点の解決は、半導体基板に形成され第１の領域
がそれぞれ低電位側配線（Ｖss）に接続され第２の領域
及び制御電極が交差接続された一対の駆動トランジスタ
（Q2,Q3）と、前記駆動トランジスタの該第２の領域と
高電位側配線（Ｖcc）との間にそれぞれ接続された一対
の負荷素子（Ｒ）と、該駆動トランジスタと負荷素子と
の結節点とビット線（BL）との間に接続されたスイッチ
手段（Q1,Q4）で構成されるメモリセルにおいて、前記
制御電極を該半導体基板上に設け、前記低電位側配線を
前記制御電極を覆う第１の絶縁膜上に設け該第１の絶縁
膜に設けられた第１のコンタクトホールを介して前記一
対の駆動トランジスタの第１の領域に接続し、前記高電
位側配線及び一対の負荷素子を前記低電位側配線を覆う
第２の絶縁膜上に設け、且つ前記一対の負荷素子のそれ
ぞれを該第１及び第２の絶縁膜に設けられた第２のコン
タクトホールを介して前記一対の駆動トランジスタの制
御電極及び前記駆動トランジスタの第２の領域に接続
し、さらに、前記低電位側配線及び高電位側配線をメモ
リセルの第１の方向に沿って両者が重なりあうように延
在させ、前記負荷素子を前記制御電極と重なるように配
置し、且つ該制御電極の幅方向及び該負荷素子の長さ方
向を、該第１の方向と直交する第２の方向に沿って延在
させ、前記低電位側配線と前記駆動トランジスタの第１
の領域を接続する導電路の方向を、前記第２の方向に平
行にすることによって解決される。To solve the above problems, a pair of drive transistors (Q 2 , Q 2 ) formed on a semiconductor substrate, in which the first regions are connected to the low potential side wiring (V ss ) and the second regions and the control electrodes are cross-connected, respectively. 3 ), a pair of load elements (R) connected between the second region of the drive transistor and the high potential side wiring (V cc ), respectively, and a node between the drive transistor and the load element. In a memory cell composed of switch means (Q 1 , Q 4 ) connected to a bit line (BL), the control electrode is provided on the semiconductor substrate, and the low potential side wiring is connected to the control electrode. The high potential side wiring and the pair of loads are provided on the first insulating film that covers and are connected to the first regions of the pair of drive transistors through the first contact holes provided in the first insulating film. The element on the second insulating film that covers the low potential side wiring. And each of the pair of load elements is in the control electrode of the pair of drive transistors and the second region of the drive transistor through a second contact hole provided in the first and second insulating films. Connecting, further extending the low potential side wiring and the high potential side wiring along the first direction of the memory cell so as to overlap each other, the load element is arranged so as to overlap with the control electrode, The width direction of the control electrode and the length direction of the load element are extended along a second direction orthogonal to the first direction, and the low potential side wiring and the first of the drive transistor are provided.
The problem is solved by making the direction of the conductive path connecting the regions of (1) and (2) parallel to the second direction.
本発明はＶss配線として基板内に形成されたn+型活性層
を利用する代わりに、第３の配線層を採用している。特
にこのＶss配線を半導体基板上の第２層目に形成し、Ｖ
cc配線及びメモリセルの負荷素子を第３層目に形成す
る。この負荷素子はメモリセルの駆動トランジスタの制
御電極上にレイアウトされているが、Ｖss配線をコンタ
クトホールを介して駆動トランジスタのソース領域に接
続する際、Ｖss配線を第２層目に形成しておくと、Ｖss
配線よりあとに形成されるＶcc配線及び負荷素子との位
置合わせ余裕を考慮する必要がない。The present invention employs a third wiring layer instead of utilizing the n + type active layer formed in the substrate as the V ss wiring. In particular, when this V ss wiring is formed on the second layer on the semiconductor substrate,
The cc wiring and the load element of the memory cell are formed on the third layer. This load element is laid out on the control electrode of the driving transistor of the memory cell, when connecting the V ss line to the source region of the drive transistor through the contact hole, forming a V ss line for the second layer V ss
It is not necessary to consider the alignment margin with the V cc wiring formed after the wiring and the load element.
また、本発明によればＶss配線を基板上に被着された導
電層を用いて行うことにより、ただ１つのフィールド酸
化膜を隔てるのみで、セル間の分離ができ、集積度を向
上させることができる。Further, according to the present invention, the V ss wiring is performed by using the conductive layer deposited on the substrate, so that only one field oxide film is separated and the cells can be separated from each other to improve the integration degree. be able to.
第１図は本発明によるSRAMセルのＶss配線の平面図と、
Ｃ−Ｃ′断面図ある。FIG. 1 is a plan view of a V ss wiring of an SRAM cell according to the present invention,
It is CC 'sectional drawing.
図において、１は半導体基板でｐ型珪素（Si）基板、
１′は層間絶縁層で二酸化珪素（SiO2）層である。In the figure, 1 is a semiconductor substrate, a p-type silicon (Si) substrate,
1 'is a silicon dioxide (SiO 2) layer in the interlayer insulating layer.
２はＶss配線層でポリSiよりなる第３の導電層（ポリSi
Ｃ層）で、コンタクトホール３においてn+型活性層23
と接続される。2 is a V ss wiring layer and is a third conductive layer (poly Si
C layer), the n + -type active layer 23 in the contact hole 3
Connected with.
例示のSRAMセルにおいては、回路パターンのレイアウト
上、第３の導電層（ポリSi Ｃ層）は第２層目に被着す
ると好都合である。In the illustrated SRAM cell, it is convenient to deposit the third conductive layer (poly-SiC layer) on the second layer because of the layout of the circuit pattern.
この場合のメモリセル間の間隔は、 素子分離領域の幅（ａ） だけとなる。In this case, the distance between the memory cells is only the width (a) of the element isolation region.
以上詳細に説明したように本発明によれば、Ｖss配線を
基板内に形成されたn+型活性層を導電層として用いる代
わりに、第３の導電層を用いることにより、ただ１つの
フィールド酸化膜でセル間の分離を行うことができ、高
集積化が可能となる。As described in detail above, according to the present invention, by using the third conductive layer instead of using the n + -type active layer formed in the substrate as the V ss wiring, only one field is formed. The oxide film can be used to separate cells, which enables high integration.
第１図は本発明によるSRAMセルのＶss配線の平面図と、
Ｃ−Ｃ′断面図、 第２図（１），（２）はそれぞれSRAMセルの回路図と、
従来例による平面図、 第３図（１）乃至（３）はそれぞれ従来例によるSRAMセ
ルのＶss配線の平面図、Ａ−Ａ′断面図、Ｂ−Ｂ′断面
図である。 図において、 １は半導体基板でｐ型珪素（Si）基板、 1Aは素子間分離領域でフィールド酸化膜、 １′は層間絶縁層でSiO2層、 ２は第３の導電層でポリSiよりなＶss配線層（ポリSi
Ｃ層）、 ３はコンタクトホール、 21は第１の導電層でポリSiよりなるゲート（ポリSi Ａ
層）、 22は第２の導電層でポリSiよりなる負荷抵抗Ｒ、および
Ｖcc配線層（ポリSi Ｂ層）、 23はn+型活性層でＶss配線層、 24はコンタクトホール、 Ｖccは電源電位、 Ｖssは接地電位、 Q1,Q2,Q3,Q4はトランジスタ、 Ｒは負荷抵抗、 WLはワード線、 BLはビット線である。 ａは素子間分離領域の幅、 ｂはn+型活性層の幅 である。FIG. 1 is a plan view of a V ss wiring of an SRAM cell according to the present invention,
A sectional view taken along the line CC ', and FIGS. 2 (1) and 2 (2) are circuit diagrams of SRAM cells, respectively.
A plan view of the conventional example and FIGS. 3A to 3C are a plan view, an AA ′ sectional view, and a BB ′ sectional view of the V ss wiring of the SRAM cell according to the conventional example, respectively. In the figure, 1 is a semiconductor substrate, a p-type silicon (Si) substrate, 1A is a field oxide film in an element isolation region, 1'is an interlayer insulating layer being a SiO 2 layer, 2 is a third conductive layer made of poly-Si. V ss wiring layer (poly Si
C layer), 3 is a contact hole, 21 is a first conductive layer, which is a gate made of poly-Si (poly-Si A
Layer), 22 is a second conductive layer and is a load resistance R made of poly-Si, and V cc wiring layer (poly-Si B layer), 23 is an n + type active layer, V ss wiring layer, 24 is a contact hole, V cc is a power supply potential, V ss is a ground potential, Q 1 , Q 2 , Q 3 , and Q 4 are transistors, R is a load resistance, WL is a word line, and BL is a bit line. a is the width of the element isolation region, and b is the width of the n + type active layer.
Claims (2)
れ低電位側配線（Ｖss）に接続され第２の領域及び制御
電極が交差接続された一対の駆動トランジスタ（Q2,
Q3）と、前記駆動トランジスタの該第２の領域と高電位
側配線（Ｖcc）との間にそれぞれ接続された一対の負荷
素子（Ｒ）と、該駆動トランジスタと負荷素子との結節
点とビット線（BL）との間に接続されたスイッチ手段
（Q1,Q4）で構成されるメモリセルにおいて、 前記制御電極は該半導体基板上に設けられ、 前記低電位側配線は、前記制御電極を覆う第１の絶縁膜
上に設けられ、該第１の絶縁膜に設けられた第１のコン
タクトホールを介して前記一対の駆動トランジスタの第
１の領域に接続され、 前記高電位側配線及び一対の負荷素子は、前記低電位側
配線を覆う第２の絶縁膜上に設けられ、且つ前記一対の
負荷素子のそれぞれは該第１及び第２の絶縁膜に設けら
れた第２のコンタクトホールを介して前記一対の駆動ト
ランジスタの制御電極及び前記駆動トランジスタの第２
の領域に接続され、 さらに、前記低電位側配線及び高電位側配線はメモリセ
ルの第１の方向に沿って両者が重なりあうように延在
し、 前記負荷素子は前記制御電極と重なるように配置され、
且つ該制御電極の幅方向及び該負荷素子の長さ方向は、
該第１の方向と直交する第２の方向に沿って延在し、 前記低電位側配線と前記駆動トランジスタの第１の領域
を接続する導電路の方向は、前記第２の方向に平行であ
る ことを特徴とする半導体メモリセル。1. A pair of drive transistors (Q 2 , formed on a semiconductor substrate, each of which has a first region connected to a low potential side wiring (V ss ), and a second region and a control electrode cross-connected to each other.
Q 3) and, a pair of load elements (R) connected respectively between the driving transistor said second region and the high-potential line of the (V cc), nodal point between the driving transistor and a load element In a memory cell composed of switch means (Q 1 , Q 4 ) connected between a bit line and a bit line (BL), the control electrode is provided on the semiconductor substrate, and the low potential side wiring is A first insulating film covering the control electrode, connected to a first region of the pair of drive transistors through a first contact hole formed in the first insulating film, The wiring and the pair of load elements are provided on a second insulating film that covers the low potential side wiring, and each of the pair of load elements is a second insulating film provided on the first and second insulating films. Control of the pair of drive transistors is performed through a contact hole. Second electrode of the control electrode and the drive transistor
And the low-potential side wiring and the high-potential side wiring extend along the first direction of the memory cell so that they overlap each other, and the load element overlaps with the control electrode. Placed,
And the width direction of the control electrode and the length direction of the load element are
The direction of a conductive path extending along a second direction orthogonal to the first direction and connecting the low-potential-side wiring and the first region of the drive transistor is parallel to the second direction. A semiconductor memory cell characterized by being.
タ同士は、半導体基板内にフィールド酸化膜を介して隣
接して配置され、前記低電位側配線は、隣接するメモリ
セルにそれぞれ属する該駆動トランジスタに挟まれてい
る該フィールド酸化膜上に設けられていることを特徴と
する特許請求の範囲第１項記載の半導体メモリセル。2. The drive transistors of adjacent memory cells are arranged adjacent to each other in a semiconductor substrate through a field oxide film, and the low potential side wiring is connected to the drive transistors belonging to the adjacent memory cells, respectively. The semiconductor memory cell according to claim 1, wherein the semiconductor memory cell is provided on the sandwiched field oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60058905A JPH0669082B2 (en) | 1985-03-22 | 1985-03-22 | Semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60058905A JPH0669082B2 (en) | 1985-03-22 | 1985-03-22 | Semiconductor memory cell |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61216461A JPS61216461A (en) | 1986-09-26 |
| JPH0669082B2 true JPH0669082B2 (en) | 1994-08-31 |
Family
ID=13097820
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60058905A Expired - Lifetime JPH0669082B2 (en) | 1985-03-22 | 1985-03-22 | Semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0669082B2 (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5651853A (en) * | 1979-10-04 | 1981-05-09 | Toshiba Corp | Semiconductor device |
| JPS58165375A (en) * | 1982-03-03 | 1983-09-30 | Fujitsu Ltd | Semiconductor memory device |
| JPS604253A (en) * | 1983-06-23 | 1985-01-10 | Nec Corp | Semiconductor integrated circuit memory |
-
1985
- 1985-03-22 JP JP60058905A patent/JPH0669082B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61216461A (en) | 1986-09-26 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |