JPH0668677A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To eliminate a leakage current flowing through the defective part of a memory cell. CONSTITUTION:A bit line 11 and a word line 12 are corresponded to the respective columns and rows of a memory cell 10 arranged in a matrix-shape and a power source line 13 is arranged corresponding to each row. This power source line 13 is connected to a main power source line 16 through a transistor 14 executing switching operation and a fusible fuse 15 and to a spare power source line 18 through a transistor 17 to the gate of which the word line 12 is inputted. At the time of an operation test for the memory cell 10, the transistor 14 is turned off and the voltage Vs of the spare power source 18 is made to be a power source voltage. Then, when the word line 12 is selectively activated and the specified transistor is turned on, by allowing the current to flow from the spare power source line 18 into the memory cell 10, it is decided that a defective part is present in the memory cell 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a redundancy means capable of repairing a defective portion.

[0002]

2. Description of the Related Art Conventional static RAM (SRA
The memory cell of M) is a complete CM consisting of 6 transistors.
There are two types, an OS type and a high resistance load type composed of 4 transistors and 2 resistors. Of these, the complete CMOS type cell has a flip-flop configuration in which a pair of CMOS inverters are cross-coupled, and is superior to the high resistance load type cell in terms of storage stability and power consumption in a stationary state. There is.

FIG. 2 is a circuit diagram showing the structure of a complete CMOS type cell. The memory cell 10 includes a pair of CMOS inverters 1 and 2 and two access transistors 3 and 4. The output of the CMOS inverter 1 is connected to the input of the CMOS inverter 2, and the output of the CMOS inverter 2 is the output of the CMOS inverter 1. A bistable flip-flop is formed by being connected to the input. These CMOs
The respective outputs of the S inverters 1 and 2 are connected to a pair of bit lines 6 via the access transistors 3 and 4 having the word line 5 as a gate input, whereby the memory cell 10 and the bit are connected through the access transistors 3 and 4. Line 6
Read and write data transfer is performed between and. As shown in FIG. 3, a plurality of memory cells 10 are arranged in rows and columns, and word lines 5 and bit lines 6 are provided so as to correspond to the respective rows and columns. A power supply line 7 for supplying power to the memory cell 10 is arranged corresponding to each row of the memory cell 10, and a main power supply line 8 connected to each power supply line 7 is arranged in the peripheral portion of the memory cell 10. It The above plurality of word lines 5 and bit lines 6 are selectively activated based on the designation of address data, and are configured to select the memory cell 10 at a specific address.

By the way, as the capacity and integration of the device are increased, the probability of occurrence of a defective portion becomes high, and therefore a redundant means for relieving the defective portion is indispensable. This redundant means includes a spare memory cell having the same structure as the original memory cell, and a bit line and a word line connected to this spare memory cell. The generated bit line or word line is inactivated and at the same time the spare bit line or word line is activated. A memory device having such redundancy means is disclosed in, for example, Japanese Patent Laid-Open No. 63-235.
It is proposed in Japanese Patent No.

[0005]

In the above redundancy means, a memory cell having a defective portion is replaced with a memory cell provided as a spare. However, when a leakage due to insulation failure occurs, Even if the defective bit line is fixed to the inactive state, a leak current from the power supply line to the memory cell may flow, and this leak current may cause a defect. That is, in the complete CMOS type in which almost no current flows when each memory cell is in the stopped state (standby state), if a slight current flows in the stopped state, it is determined that the standby current is defective during the operation test. Therefore, the result of the operation test is not a good product even though the defective portion is relieved by the redundant circuit.
As a result, the yield is reduced.

Therefore, it is an object of the present invention to reliably repair a defective portion when the defective portion is replaced by a redundant circuit.

[0007]

The present invention has been made to solve the above problems, and is characterized in that a pair of CMOS inverter circuits are connected in a flip-flop configuration and each inverter circuit is connected. A static type memory cell in which a selection transistor is connected to the output side of each of the memory cells, and a plurality of memory cells are arranged in a matrix; , A plurality of second signal lines associated with each row of the memory cells and serving as gate inputs of the selection transistors, and a plurality of first signal lines connected to the power supply side of the inverter circuit for each row of the memory cells. A power line, at least one second power line to which the plurality of first power lines are commonly connected, and a plurality of first power lines to which the plurality of first power lines are selectively connected. In the semiconductor memory device including the power line of the first power line, the first power line includes a first switch element that opens and closes according to specific information and a second switch element that can be disconnected by physical means in series. It is connected to the second power line and is also connected to the third power line via a third switch element that opens and closes according to the information of the second signal line.

[0008]

According to the present invention, a memory cell having insulation failure is formed by cutting the first switch element (fuse) connected between the first power line and the second power line as necessary. The power supply to the memory cell is stopped, and the current flowing from the power line to the memory cell disappears when the memory cell is in the stopped state.

Also, with the first switch element closed, the third switch element is opened to selectively connect the first power line to the third power line, and a voltage is applied from the third power line. As a result, when the first power line corresponding to the memory cell in which the leak current flows is selected, a current flows from the third power line to the first power line. Therefore, the presence or absence of a defective portion is determined by detecting this current.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the essential parts of a semiconductor memory device according to the present invention.
It is a circuit diagram shown. In this figure, the memory cell 10 is
It is a complete CMOS type and is the same as that shown in FIG.
It Each column of the memory cells 10 arranged in a matrix has
The memory cell 10 is associated with the pair of bit lines 11.
The outputs of the inverters 1 and 2 are connected to the memory cell 10
A word line 12 is associated with each row of memory cells
Connected to the gates of 10 access transistors 3 and 4
It In addition, a power supply line 1 that serves as a power supply for each memory cell 10
3 are arranged corresponding to each row of the memory cells 10, and
The inverters 1 and 2 of the memory cell 10 are connected to the source line 13.
Will be continued. This power supply line 13 is at a predetermined timing
Switch transistor 14 for switch operation and operation
Through the fuse 15 which is cut according to the result of the test
It is connected to the main power supply line 16. Therefore, the transistor
The voltage V of the main power supply line 16 during the period when 14 is on.
_AIs applied to each memory cell 10 via the power supply line 13.
Will be done. Further, the power line 13 is a word line
12 through the switch transistor 17 whose gate input is
And connected to the auxiliary power line 18 for testing.
Voltage V of auxiliary power line 18_BFrom the power line 13
It is selectively applied to the recell 10. This auxiliary power line
No. 18 works at the time of operation test.
It is connected to the I / O pad for the strike. And the main power source
The in 16 and the auxiliary power supply line 18 are connected to the transistor 14.
Via a switch transistor 19 that switches at the same time
The power line 13 is connected to the main power
Power is supplied from both the source line 16 side and the auxiliary power line 18 side.
Pressure V_AWill be supplied.

A control circuit for controlling the operation of the transistor 14.
Path 20 has its drain grounded and, if necessary, its source
Power supply voltage level voltage V_XMOS transistor that is given
A transistor 21 and a transistor connected in parallel with the transistor 21.
Receives the source potentials of the capacitor 22 and the transistor 21.
An inverter 23 and an input receiving the output of the inverter 23
It consists of a converter 24, and the source of the transistor 21 (in
Voltage V to the input of the barter 23)_XWith or without
Configured to turn transistor 14 on or off
Be done. That is, the voltage V_XIs not applied, the
The output of the transistor 24 is fixed to the low level and the transistor 1
4 is turned on, the voltage V _XIs applied
And the output of the inverter 24 is fixed at high level.
The transistor 14 is turned off.

In the above memory device, when a defective portion is detected by a predetermined operation test, the fuse 15 corresponding to the defective portion is cut and the voltage supply to the defective portion is cut off. The following method is used to detect defective parts. First, the voltage V _X is applied to the control circuit 20 to turn off the transistors 14 and 19 and the auxiliary power supply line 1
The voltage V _B of 8 is raised to the power supply voltage. Therefore, when the word line 12 is selectively activated, the transistor 17 that receives the data of the word line 13 is turned on, the specific power supply line 13 is connected to the auxiliary power supply line 18, and the voltage is applied to the memory cell 10 of the corresponding row. V _B is applied. At this time, if each memory cell 10 is normal, no current will flow from the auxiliary power supply line 18 to the memory cell 10,
If there is a leak current in any of the memory cells 10, a current flows from the auxiliary power supply line 18 to the memory cell 10. Therefore, when the power supply line 13 is selectively connected to the auxiliary power supply line 18, if a current flowing through the auxiliary power supply line 18 is detected, it is determined that there is a defective portion, and the fuse 15 corresponding to that row is blown. It In such a determination method, since the word line 12 is used, the increase in the circuit configuration is small, and the expansion of the substrate area can be suppressed.

[0013]

According to the present invention, by stopping the supply of the voltage to the defective portion, almost no current flows when the memory cell is in the stopped state even if there is a leak at the defective portion, and the operation test is performed. At that time, the standby current is not determined to be defective. Therefore, when the defective portion is relieved by various redundant means, the defective portion can be surely eliminated, and the reduction of the manufacturing yield can be prevented.

Further, since an address having a defective portion can be easily detected during the operation test, the throughput of the operation test is increased and the productivity can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram of a static RAM.

FIG. 3 is a circuit diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 1, 2 CMOS inverter 3, 4 Access transistor 5, 12 Word line 6, 11 Bit line 7, 13 Power supply line 8, 16 Main power supply line 10 Memory cell 14, 17, 19 Switch transistor 18 Auxiliary power supply line 20 Control circuit

Claims (2)

[Claims] 1. A static type memory cell in which a pair of CMOS inverter circuits are connected in a flip-flop configuration, selection transistors are respectively connected to the input and output sides of each inverter circuit, and a plurality of matrix type memory cells are arranged, A plurality of first signal lines associated with each column and connected to the selection transistor, and a plurality of second signal lines associated with each row of the memory cells and serving as a gate input of the selection transistor; A plurality of first power lines connected to the power supply side of the inverter circuit for each row of the memory cells, and at least one second power line commonly connected to the plurality of first power lines; A third power line to which the first power line is selectively connected,
The first power line is opened and closed according to specific information.
Switch element and a second switch element that can be disconnected by physical means are connected in series to the second power line, and a third switch element that opens and closes according to the information of the second signal line. A semiconductor memory device, characterized in that it is connected to the third power line via the. 2. The first switch element is closed, the third switch element is opened according to the information of the second signal line, and one of the plurality of first power lines is connected to the third switch element. The current flowing to the memory cell is detected when the memory cell is connected to a power line and a predetermined voltage is applied to the memory cell, and the second switch element is selectively disconnected according to the detection result. 1. The semiconductor memory device according to 1.