JPH0668540B2 - Semiconductor memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial field" The present invention accesses a memory under test by an address from a pattern generator, writes data from the pattern generator, and then outputs an address signal from the pattern generator. The present invention relates to a semiconductor memory test apparatus for reading the memory under test and comparing the read data with an expected value to test the memory under test.

"Prior Art" A conventional semiconductor memory test apparatus of this type is configured as shown in FIG. 4, for example. An address signal is applied from the address terminal 12 of the pattern generator 11 to the memory under test 13, and the data from the data terminal 14 generated by the pattern generator 11 is written to that address of the memory under test 13. Then, an address is applied from the pattern generator 11 to the memory under test 13 to read it, and the data read at that time is compared with the data output from the pattern generator 11, that is, the expected value data, by the logical comparator 15. Then, the quality of the memory under test 13 is determined.

The pattern generator 11 includes an address generator 21, a data generator 22, a data memory 23, and a clock control signal generator 2.
4. The sequence control unit 25. The sequence controller 25 includes an address generator 21 and a data generator 2.
2. The clock control signal generator 24 is controlled. The address generator 21 generates an address signal to be applied to the memory under test 13. The data generator 22 is the memory under test 13
The data to be applied to, that is, the write data and the expected value data to be output to the logical comparator 15 are generated.

The data memory 23, like the data generator 22, generates data to be applied to the memory under test 13 and expected value data to be output to the logical comparator 15. The data memory 23 generates data by reading the data written in advance. The data generator 22 is used to generate regular data, and the data memory 23 is used to generate random data without regularity. The multiplexer 26 switches whether the data generator 22 outputs the data to the data terminal 14 or the data memory 23 outputs the data to the data terminal 14.

The clock control signal generator 24 generates a clock control signal to be applied to the memory under test 13.

"Problems to be Solved by the Invention" The conventional semiconductor memory test apparatus shown in FIG. 4 has the following drawbacks.

(B) There is a memory having a random access port and a serial access port as shown in FIG. The RAM section 27 of this memory operates similarly to a normal dynamic RAM via a random access port. The SAM section 28 of this memory is accessed by a pointer inside the memory chip, and writing or reading is performed in synchronization with the clock, and the pointer is incremented by 1 when the clock is input. Further, data transfer can be performed between the RAM unit 27 and the SAM unit 28, and the RAM unit 27 and the SAM unit 28 can be independently operated asynchronously.

When testing a memory having such a random access port and a serial access port, since the pattern generator has only one system of the address generation unit and the data generation unit, the RAM unit 27 and the SAM unit 28 are compared with each other. Data cannot be generated independently and simultaneously. Since the address from the address generator 21 is used to access the data memory 23 even when the data memory 23 is used, if this address is used as the address of the SAM unit 28, this occurs in order. No address can be generated for 27.

(B) FIFO having a write pointer and a read pointer
The write address and the read address of the memory are determined by respective pointers, and these pointers are incremented by the write clock and the read clock.
When testing this memory, data was conventionally generated from the data memory. However, in the memory under test, the address is determined by the write pointer at the time of writing and the read pointer at the time of reading, but there is only one system for generating the address for accessing the data memory, so the address for the write pointer is generated. When,
The address for the read pointer cannot be generated.

"Means for Solving Problems" According to the present invention, an address signal generated by a pattern generator is applied to a memory under test for access, and data is applied to the memory under test for writing. At the same time, the buffer memory is accessed by the address signal in the same manner as the memory under test, and the data supplied to the memory under test is written into the buffer memory. That is, data having the same content as the memory under test is written in the buffer memory. When the memory under test is read, the buffer memory also reads the same address, and the data read from the buffer memory is used as an expected value to compare the data read from the memory under test with the logical comparator.

Further, in order to test a memory having a random access port and a serial access port, a multiplexer is provided on the input side of the address of the buffer memory, a counter is further provided, and an address for setting the pointer of the memory under test is loaded into this counter. And the counter can be incremented by clock, and either the contents of the counter or the address to be supplied to the memory under test is selected by the multiplexer to the address of the buffer memory. To supply. When the memory under test is randomly accessed in this way, the address to be supplied to the memory under test is selected by the multiplexer and also supplied to the buffer memory to randomly access the buffer memory, and a pointer is set for the memory under test. Then, when the address is updated automatically for each clock, the pointer is loaded into the counter, the counter is incremented for each clock, and the buffer memory is accessed with the contents of the counter. This makes it possible to test a memory having a random access port and a serial access port. In this case, when reading and writing are performed at the same time, by providing another set of such multiplexer and buffer memory, one buffer memory is written and the other buffer memory is read. It is possible to perform a test when writing and reading are simultaneously performed on the memory under test.

Further, when testing a FIFO memory having a write pointer and a read pointer as the memory under test, a multiplexer is provided on the input side of the address of the buffer memory, and two counters are provided so that the buffer memory can provide an address for the memory under test by the multiplexer. , One of the three contents of each of the two counters is selected so that it can be supplied as an address to the buffer memory, and each counter stores the address to be stored in each pointer of the memory under test in the same manner, Moreover, by utilizing one of these counters to set its write point to the write pointer and the other counter to set its read point to the read pointer, these counters are also incremented by the write clock and read clock of the memory under test. And Manzanillo One to be able to perform the same writing and writing to the memory under test to the buffer memory, and buffer memory similar to the memory under test reading can be read.

[Embodiment] FIG. 1 shows a first embodiment of the present invention, that is, an example in which the present invention is applied to a case where a memory having a random access port and a serial access port is tested, and a portion corresponding to FIG. Are given the same reference numerals.

In the present invention, a buffer memory 31 having a storage capacity equal to or larger than that of the memory under test 13 and a control signal generator 32 for the buffer memory 31 are provided in the pattern generator 11. The buffer memory 31 can change its memory configuration according to the number of data bits of the memory under test 13. That is, when the memory under test 13 has one word and one bit, the buffer memory 31 has a one word and one bit configuration, and when the memory under test 13 has one word and four bits, the buffer memory 31 also has a one word and four bit configuration.

The buffer memory 31 is supplied with the same data as the memory under test 13, the same data is written in the buffer memory at the same address of the memory under test 13, and the buffer memory 31 is accessed at the same address as the memory under test 13. Is done like this. Therefore, the buffer memory 3
2 input multiplexer 3 in series with 1 address input terminal
7 is inserted, and the counter 38 is connected to one 1 input side of the multiplexer 37. The counter 38 has a function of loading an address generated by the pattern generator 11, and a function of incrementing (sequentially adding 1), decrementing (sequentially subtracting 1) and holding the value of the counter 38. The multiplexer 37 selects whether the address applied to the buffer memory 31 is the address of the terminal 12 generated by the pattern generator 11 or the count value of the counter 38.

The counter 38 is controlled by the counter control signal output from the control signal generator 32 of the pattern generator 11.
The switching of the multiplexer 37 is also performed by the multiplexer control signal output from the control signal generator 32 of the pattern generator 11.

In a memory having a random access port and a serial access port, the SAM part is accessed by a pointer. Initialization of the pointer is performed by an address given from the outside, but the initial value is also set in the counter 38.

For the RAM part of the memory under test 13, the pattern generator 1
1 gives an address and data, and at the same time, the address is passed through the multiplexer 37 to the buffer memory 3
1 to access, and the data is written to the buffer memory 31 at the same time, and then the memory under test 1
The data in the RAM section 3 is transferred to the SAM section, and the SA of the memory under test 13 is sent by the address from the pattern generator 11.
The pointer of the M section is initialized, and at the same time, the counter 38 is initialized by the address, the buffer memory 31 is accessed and read by the counter 38, and the read data from the SAM section of the memory under test 13 and the buffer memory are synchronized with this. The memory under test can be tested by logically comparing the read data of 31.

In a memory having a random access port and a serial access port, it is possible to operate each port asynchronously, that is, independently, but as shown in FIG. 2, the buffer memory 31 and multiplexer 3 in FIG.
In addition to the 7 sets, a buffer memory 41 and a multiplexer 42
By providing this group, it is possible to perform a test for writing data from the random access port while reading the memory under test from the serial access port. The buffer 38 is accessed by the counter 38, and the expected value for the serial port is read.
1 and write to the memory under test 13 through the random access port at the same time as the buffer memory 31.
At the same time, the data is written.

FIG. 3 shows a FI having a write pointer and a read pointer.
A second embodiment in which the present invention is applied to a FO memory testing device will be described. A counter 43 is provided for the configuration shown in FIG. 1, and the counters 38 and 43 are the pattern generator 11
It operates independently by the control signal from. The multiplexer 37 uses the address from the pattern generator 11 and the counter 3
Either the count value of 7 or the count value of the counter 43 is selected and applied to the address of the buffer memory 31.

When initializing the write pointer of the memory under test 13,
The counter 38 stores the initialization address from the pattern generator 11, and the counter 43 stores the initialization address when the read pointer of the memory under test 13 is initialized. When a write clock is applied to the memory under test 13 and writing is performed, the multiplexer 37 selects the counter 38 to write to the buffer memory 31. When a read clock is applied to the memory under test 13 and a read operation is performed, the counter 37 is read by the multiplexer 37.
3 is selected and the buffer memory 31 is accessed. The output of the buffer memory 31 and the output of the memory under test 13 are compared by the logical comparator 15. By performing the test in this way, the pattern generator 11 may generate an address only when the counter 38 and the counter 43 are initialized,
It is not necessary to generate an address from the pattern generator 11 in accordance with the write clock and the read clock applied to the memory under test 13.

As described above, according to the present invention, a counter, a multiplexer and a buffer memory are provided, and when an address is set in the pointer of the memory under test, the address is stored in the counter and the counter is stored. Change the pointer of the test memory sequentially in synchronization with the clock that changes sequentially,
By selecting the count value of the counter by the multiplexer and supplying it as an address to the buffer memory,
It is possible to write or read the same data to or from the same address as the memory under test of the buffer memory.
This can be done for the SAM portion of the memory or the FIFO memory, and at that time, it is not necessary for the pattern generator to generate an address for each access. The address generated from the pattern generator can be supplied to the memory under test and the buffer memory by selecting the multiplexer.

Further, as shown in FIG. 2, if two sets of multiplexers and buffer memories are provided, the RAM section of the memory under test and the S
The AM part can be tested independently. Further, if two sets of counters are provided as shown in FIG. 3, reading and writing operations can be easily performed on the FIFO memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention suitable for testing a memory having a random access port and a serial access port, and FIG. 2 is an invention suitable for testing a memory having a random access port and a serial access port. FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 3 is a block diagram showing an embodiment of the present invention suitable for testing a FIFO memory having a write pointer and a read pointer.
FIG. 4 is a block diagram showing a conventional semiconductor memory testing device, and FIG. 5 is a diagram showing the concept of a memory having a random access port and a serial access port.

Claims (1)

[Claims] 1. An address signal from a pattern generator is applied to a memory under test, and data from a pattern generator is applied to a memory under test and written to the memory under test by an address signal from the pattern generator. In a semiconductor memory test apparatus for reading out and comparing the read data and an expected value with a logical comparator to test a memory under test, an address signal from the pattern generator can be loaded from the pattern generator. A counter that can sequentially change the count value by one by a control signal of, a multiplexer that selects and outputs either the count value of the counter or the address signal from the pattern generator, and the multiplexer of the multiplexer. The output is given as an address signal and the data from the pattern generator is given as write data. A buffer memory, the memory under test is read by an address signal from the pattern generator and supplied to the logical comparator, and the outputs simultaneously read from the buffer memory are supplied to the logical comparator as expected values. A semiconductor memory test apparatus characterized by being performed.