JPH0667617A - Display device - Google Patents

Abstract

PURPOSE:To suppress a higher harmonic noise due to a driving voltage applied to a display segment or display dot of the dynamic drive type display device. CONSTITUTION:The driving voltage applied to each display minimum unit part which is a segment or dot is varied within its display period. The applied driving voltage is a continuous staircase wave composed of plural pulses. In another way, the waveform of the applied driving voltage is a voltage waveform obtained by supplying the continuous staircase rectangular wave composed of plural pulses to a smoothing filter means. In further another way, the applied driving voltage waveform is a voltage waveform whose voltage value continuously varies almost in a sine wave shape.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic drive type display device using a display tube, an LED or the like.

[0002]

2. Description of the Related Art A display device using a display tube or an LED has been widely spread and is also used in AV equipment such as tuners and CD players. FIG. 16 shows the configuration of a conventional display device using a display tube. In the display unit 1 capable of displaying 4-digit numbers, a display tube is provided for displaying digits for each digit K _{1 to} K _4. 7 segments (light emitters) a to g are provided.

In the display unit 1, Sa is a for applying a drive voltage to the anode of the segment a in each digit K _{1 to} K ₄ .
It is a segment terminal, and similarly Sb to Sg are each digit K.
_{1 to} K ₄ are b segment terminals to g segment terminals for applying a driving voltage to the anodes of the segments b to g in _{1 to} K ₄ .

G ₁ is a first grid terminal for applying a driving voltage to the grid corresponding to each segment of the digit K ₁ ,
Similarly, G _{2 to} G ₄ indicate the second grid terminal to the fourth grid terminal for applying the driving voltage to the grids corresponding to the segments of the digits K _{2 to} K ₄ , respectively.

Reference numeral 2 denotes a display control section which is composed of a microcomputer having a CPU, a ROM and a RAM. The output ports Pa to Pg are connected to the gates of the FETs Qa to Qg, respectively, and the output pulses thereof turn on / off the FETs Qa to Qg. As the FETs Qa to Qg are turned on / off, the display driving voltage V _F is switched,
The supply of the voltage V _{F to} the segment terminals Sa to g segment terminals Sg is controlled. That is, the segment selection pulse is output from the output ports Pa to Pg.

The output ports P _{G1 to} P _G4 are each F
It is connected to the gate of ETQ _G1 to Q _G4, performs the on / off FETs Q _G1 to Q _G4 by the output pulse. FETQ
With the ON / OFF _G1 to Q _G4, voltage V _F of the display driving
Are switched, and the supply of the voltage V _F to the first grid terminal G ₁ to the fourth grid terminal G ₄ is controlled. That is, the grid scan pulse is output from the output ports P _{G1 to} P _G4 .

For example, when displaying the number "1248" on the display unit 1, the FE is selected by the segment selection pulse and the grid scan pulse output from the display control unit 2.
TQa to Qg and FETs Q _{G1 to} Q _G4 are controlled to be turned on / off, and the first grid to the fourth grid are controlled as shown in FIGS.
A driving voltage V _F is sequentially applied to the grid, and a segment to emit light is selected at each digit.
As shown in FIGS. 17E to 17K, a segment terminal Sa
A voltage V _F is applied to a predetermined segment terminal among the ~ g segment terminals Sg. Note that T is the scan cycle, t _P
Is the pulse width and t _b is the blanking width, so that the duty cycle D _U = t _P / T.

When a positive voltage is applied to the grid and the anode at the same time, the segment performs a light emitting operation. Therefore, according to the applied voltage state shown in FIGS.
Numbers will be sequentially displayed at each digit like 7 (m).

[0009]

However, the application of such a drive voltage as a rectangular wave pulse to the display section 1 causes an adverse effect.

For example, as shown in FIG. 18 (a), in the case of a pulse having a rising and falling edge of a rectangular wave having a period T, as shown in FIG. 18 (b), the original frequency component of 1 / T (Hz) is used. It is known that a large number of odd-order frequency components are included over the third, fifth, and higher orders such as 3 / T and 5 / T. Further, as can be seen from FIG. 17, the pulse of the applied drive voltage is not constant in the time between the “H” section and the “L” section, that is, because the duty is different, harmonic components other than the above will also be generated. .

In particular, the driving voltage V _F tends to be high due to the demand for higher brightness of display by a display tube or LED (for example, 20 to 5 in the case of the segment display system as described above).
0 V, 100 V in the case of dot display system, etc.), which is switched, so that it is greatly affected by harmonic noise, and the receiving sensitivity of a tuner equipped with such a display device or a tuner arranged in the vicinity of the display device. However, in the case of a CD player, an amplifier, or the like, there is a problem in that the sound quality is deteriorated due to harmonic components on the power supply line.

[0012]

SUMMARY OF THE INVENTION In view of such problems, an object of the present invention is to suppress noise generation due to harmonic components in a voltage pulse applied to the display section.

For this reason, in a display device which performs a display operation by driving each display minimum unit, for example, a segment or a dot by a dynamic drive method, the drive voltage applied to each display minimum unit is changed within the display period. Configure to allow. In particular, both a drive voltage applied to each display minimum unit (for example, an anode segment applied voltage) and a drive voltage commonly applied per digit formed by a predetermined number of display minimum units (for example, a grid applied voltage). Is changed within the display period of the minimum display unit.

In these cases, the change in voltage is realized by making the applied drive voltage into a stepwise continuous rectangular wave obtained by synthesizing a plurality of pulses. Alternatively, the applied drive voltage waveform is realized by a voltage waveform obtained by supplying a stepwise continuous rectangular wave obtained by combining a plurality of pulses to the smoothing filter means. Further alternatively, the applied drive voltage waveform is realized by a voltage waveform whose voltage value continuously changes in, for example, a substantially sinusoidal waveform.

[0015]

By using a drive voltage for the display unit that is closer to a sine wave than a rectangular wave pulse, the contained harmonic components can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIGS. This embodiment is a display device using a display tube, and the same parts as those in FIG.

SW _{1 to} SW ₃ represent switch circuits, which connect and disconnect the supply of a power supply voltage of, for example, + 5V.
ON / OFF of each of the switch circuits SW _{1 to} SW ₃ is controlled by control pulses output from the output ports S _{1 to} S ₃ of the display control unit 2.

By turning on / off the switch circuits SW _{1 to} SW ₃ , a power supply voltage of +5 V is divided by all or a part of the resistors R ₁ , R ₂ , R ₃ and the resistor R ₄ and supplied to the operational amplifier 3. The output of the operational amplifier 3 is supplied to the buffer section formed by the complementary transistors Q ₁ and Q ₂ , and the driving voltage V _F of, for example, about 20 to 50 V is taken out.

That is, when the switch circuit SW ₁ is on, the output voltage of the operational amplifier 3 is R ₄ / (R ₄ + R ₁ ) × 5 × {(R ₆ / R ₅ ) +1} [V], for example, As shown in FIG. 5, the drive voltage V _F is V
You get ₁ level. Further, when the switch circuit SW ₂ is on, the output voltage of the operational amplifier 3 becomes R ₄ / (R ₄ + R ₂ ) × 5 × {(R ₆ / R ₅ ) +1} [V], for example, as shown in FIG. V as the drive voltage V _F as shown
You get ₂ levels. Further, when the switch circuit SW ₃ is on, the output voltage of the operational amplifier 3 becomes R ₄ / (R ₄ + R ₃ ) × 5 × {(R ₆ / R ₅ ) +1} [V], for example, as shown in FIG. V as the drive voltage V _F as shown
You get ₃ levels.

This driving voltage V _F is applied to each F through the resistor r.
Applied to the drains of ETQa to Qg and Q _{G1 to} Q _G4 ,
The segment terminals Sa to Sg and the grid terminals G _{1 to} G according to ON / OFF of the FETs Qa to Qg and Q _{G1 to} Q _G4.
Applied to ₄ .

In the display device having such a configuration, when the display operation of the display unit 1 is performed, the display control unit 2 performs the process of FIG. In addition, the displayed numerical value is "12
48 ”is shown in FIG.

When executing the display, the variable n = 1 for the grid scan is first set (F101). Then, "H" is output to the nth grid (F102). That is, in this case, FIG.
As shown in (a), the scan pulse of the first grid is output from the output port P _G1 to turn off the FET Q _{G1 so} that the voltage V _F is applied to the first grid. At the same time, the first
A segment selection pulse corresponding to the displayed numerical value of the digit K ₁ is output from the output ports Pa to Pg (F103). For example, when the display is "1", the outputs of the output ports Pa to Pg are as shown in FIGS. 3 (k) to 3 (r), and the FETs Qb and Qc are shown.
Is turned off so that the voltage V _F is applied to the b segment terminal Sb and the c segment terminal Sc. By maintaining this state during the scan period of the first grid (digit K ₁ ), the number “1” is displayed (FIG. 3).
(S)).

First, from the output port S ₁ to FIG.
The control pulse "H" of the switch circuit SW ₁ performs output to turn on as (e) (F104). Then, it waits until the timer counts up T ₁ (F105). When the time T ₁ has elapsed, the output S _{1 is set} to "L" (F106), and the output S _{2 is set} to "H" as shown in FIG. 3 (f) (F107). Then, it waits until the T ₂ time is counted up (F108). When T ₂ time elapses, S
_{The 2} output is set to “L” (F109), and the S ₃ output is set to “H” (F110) as shown in FIG. Then, it waits until the T ₃ time is counted up (F111).

Further, when the time T ₃ has elapsed, the output S _{3 is set} to "L" and the output S _{2 is set} to "H", and the process waits until the time T ₄ is counted up (F112, F113, F114). When the time T ₄ has elapsed, the S ₂ output is set to “L” and S ₁
T ₅ hours to wait until the count-up output as "H" (F115, F116, F117).

At the time of counting up T ₅ hours, the digit K ₁
Since the scan period of is finished, S ₁ output is set to “L”
(F 118), and waits until the count-up of t _b duration of blanking period is made (F 119). The blanking period t _b is provided to prevent the occurrence of a ghost in the adjacent digit due to the voltage remaining due to the input capacitance of the display tube even though the drive voltage application has actually ended.

During the scanning period of this digit K ₁ , the switch circuits SW _{1 to} SW ₃ are controlled to be opened and closed by the control pulses (FIGS. 3E to 3G) from the output ports S _{1 to} S _3, so that the first The voltage V _F applied to the grid and the selected segments b and c changes stepwise as shown in FIG.

Subsequently, to scan the next digit, it is determined whether the variable n = 4 (F120). If n ≠ 4, the variable n is incremented (F121). If n = 4 at the end of scanning the digit K _4, the variable n = 1 is set to return to scanning the digit K ₁ (F122).

Similarly, for the scanning of the digits K ₂ to K ₄ , the grids G _{2 to} G ₄ are sequentially selected in the same manner (see FIG. 2: F102, FIGS. 3A to 3D) and the displayed numerical values are displayed. Accordingly, the segments a to g to be emitted are selected (see FIG. 2: F103, FIG. 3 (k) to (r)). Then, S ₁ output in each scan period, S ₂ output, S ₃ output by being made in the same manner (Figure 2: F104~F118, 3
(E) to (f)), the voltage V _F applied to the grid to be scanned and the selected segment is assumed to change stepwise as shown in FIG. Therefore, the drive voltage V _F applied to each grid and segment when displaying “1248” is shown in FIG.
~ (K) as shown.

Here, such a stepped shape is shown in FIG.
FIG. 6B shows the frequency spectrum of the signal having the period T as described above. It can be seen from FIG. 18 that the frequency components of the third order, the fifth order, etc. are significantly (40 to 50 dB) reduced as compared with the frequency spectrum of the rectangular wave pulse described above. In other words, by suppressing the harmonic noise by driving the display tube with a signal that is closer to a sine wave than a rectangular wave pulse,
It is possible to prevent deterioration of tuner reception sensitivity and deterioration of sound quality of audio equipment due to harmonic noise.

In this embodiment, the S ₁ output waveform
As another example of the S ₃ output waveform, FIG. 3 (h) (i) (j)
It is also possible to do like this. That is, the resistors R ₁ and R
According to the setting of the resistance values of ₂ and R ₃ , the switch circuit SW ₁
Only when it is on, when the switch circuits SW ₁ and SW ₂ are on, and when all of the switch circuits SW ₁ , SW ₂ and SW ₃ are on, the level of the drive voltage V _F is similarly controlled in three stages. Can be In this case, the output port S that may become a noise factor in some cases
_This is preferable because the high frequency components of the control pulse from _{1 to} S ₃ are also reduced.

Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, as shown in FIG. 7, a smoothing filter 4 including a resistor R ₇ and a capacitor C ₁ is provided in addition to the first embodiment. The driving voltage V _F as shown in FIG. 5 is integrated by the smoothing filter 4 as shown in FIG. 8 and becomes a waveform closer to a sine waveform. Therefore, the harmonic component is further reduced.

In the first and second embodiments, the driving voltage V _F is changed in a stepwise manner of three steps, but of course it may be changed in four or more steps.

A third embodiment will be described with reference to FIGS.
In this embodiment, the drive voltage V _F has a substantially sinusoidal shape, for example, si
A sinusoidal pulse generator 5 having an n ² waveform is provided. Then, a control pulse serving as an output trigger for the sinusoidal pulse generator 5 is supplied from the output port P _ST of the display control unit 2. The control pulse from the output port P _ST is shown in Fig. 1.
0 (d), grid scan pulses corresponding to the first to fourth grids (FIG. 10 (a)-
It is said that the OR of (d) is taken, and the rising of this control pulse is used as a trigger to output a sinusoidal drive voltage V _F.

Therefore, for example, when displaying "1248", the display control section 2 outputs the segment selection pulse shown in FIGS. And the drive voltage V _F applied to each segment is shown in FIG.
As shown in (k). It goes without saying that the harmonic components in the drive voltage V _F are removed more effectively by this embodiment.

FIG. 12 shows a fourth embodiment of the present invention. In this embodiment, the segment selection pulses output from the output ports Pa to Pg are input to the sinusoidal pulse generators 5a to 5g and the sinusoidal pulse generators 5a to 5g.
From 5g, a sinusoidal pulse having, for example, a sin ² waveform is output by using the segment selection pulse as a trigger, and is supplied to the gates of the FETs Qa to Qg. That is,
The drive voltage V _F applied to the drains of the FETs Qa to Qg and supplied to the segment terminals Sa to Sg is
The voltage value is controlled by the sinusoidal pulse (FET gate voltage) that controls Qg.

[0036] Similarly, the grid scan pulse output from the output port P _G1 to P _G4 is inputted to the sinusoidal pulse generator 5 _G1 to 5 _G4, sinusoidal pulse generator 5 _G1 to 5
_A sinusoidal pulse having a sin ² waveform, for example, is output from _{G4 using the} grid scan pulse as a trigger, and is supplied to the gates of the FETs Q _{G1 to} Q _G4 . That is,
The grid terminal G is applied to the drains of the FETs Q _{G1 to} Q _G4.
The driving voltage V _F supplied to _{1 to} G ₄ is FET Q _{G1 to} Q
The voltage value is controlled by the sinusoidal pulse (FET gate voltage) that controls _G4 .

Therefore, for example, when displaying "1248", the display control unit 2 causes the display control section 2 shown in FIGS.
Together with the grid scan pulse of FIG.
By outputting the segment selection pulse of (m), the drive voltage V _F applied to each grid and each segment in the display unit 1 is substantially the same as in the third embodiment shown in FIG.
As shown in (a) to (k).

In the case of this embodiment, not only the drive voltage V _F but also the control voltage to the FET serving as the display driver is close to a sine wave, so that the noise component increases due to the rectangular pulse circulated on the circuit pattern. Can also be prevented. In addition,
As described above, the control pulse to the FET that serves as the display driver may be a stepped pulse as in the first embodiment.

Various embodiments have been described above for the display device which employs the display portion using the electron tube of 1 digit 7 segment and 4 digit display. Of course, the display portion is as shown in FIG.
The above-mentioned various embodiments can be similarly applied to the case of displaying n digits in 14 digits. Furthermore, the same applies to the case where the segments are arranged in a bar display form.

The same applies to a display unit having a dot display form of vertical n dots and horizontal m dots as shown in FIG.
Similar effect by the horizontal dot scanning terminal H ₁ to H _n and the drive voltage waveform applied to the vertical dot scanning terminals V ₁ ~V _m stepped square wave or substantially sinusoidal is obtained.

Further, as shown in FIG. 15, the same applies to a display section for displaying a plurality of digits (for example, four digits) of characters or numbers with one dot of 35 dots, similarly, based on the dot selection pulse for each digit. The drive voltage applied to D _{1 to} D ₃₅ and the drive voltage waveform applied to the grid terminals G _{1 to} G ₄ based on each digit, that is, the grid scan pulse are set as a stepwise rectangular wave or a substantially sine wave.

The FETs Qa to Qf and the FETs Q _{G1 to} Q _G4 functioning as display drivers in the above embodiment.
May actually be built in the microcomputer (display control unit 2).

The display unit is not limited to the one using an electron tube as a light emitting body, and the present invention can be applied to any type of dynamic drive system such as an LED device or a plasma display.

[0044]

As described above, according to the present invention, in a display device which performs a display operation by driving each display minimum unit, for example, a segment or a dot by a dynamic drive system, a drive voltage applied to each display minimum unit. Is changed within the display period, that is, a stepwise waveform, a stepwise smoothed waveform, or a substantially sinusoidal waveform is formed, so that the harmonic noise component included in the drive voltage can be reduced. In an electronic device such as a tuner in which the display device of the present invention is mounted or is arranged in the vicinity, it is possible to eliminate the occurrence of deterioration of reception sensitivity and deterioration of sound quality due to the influence of harmonic noise components. .

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a flowchart of a display operation of the first embodiment.

FIG. 3 is an explanatory diagram of a display control pulse according to the first embodiment.

FIG. 4 is an explanatory diagram of a display drive voltage according to the first embodiment.

FIG. 5 is an explanatory diagram of a display drive voltage waveform according to the first embodiment.

FIG. 6 is an explanatory diagram of harmonic components in a display drive voltage waveform of the first embodiment.

FIG. 7 is an explanatory diagram of a configuration of a second exemplary embodiment of the present invention.

FIG. 8 is an explanatory diagram of a display drive voltage waveform according to the second embodiment.

FIG. 9 is an explanatory diagram of a configuration of a third exemplary embodiment of the present invention.

FIG. 10 is an explanatory diagram of a display control pulse according to the third embodiment.

FIG. 11 is an explanatory diagram of a display drive voltage waveform according to the third embodiment.

FIG. 12 is an explanatory diagram of a configuration of a fourth exemplary embodiment of the present invention.

FIG. 13 is an explanatory diagram of another segment display unit applicable to the present invention.

FIG. 14 is an explanatory diagram of a dot display unit applicable to the present invention.

FIG. 15 is an explanatory diagram of a dot display unit applicable to the present invention.

FIG. 16 is an explanatory diagram of a configuration of a conventional display device.

FIG. 17 is an explanatory diagram of a display drive voltage of a conventional display device.

FIG. 18 is an explanatory diagram of harmonic components in a display drive voltage of a conventional display device.

[Description of symbols] 1 display unit 2 display control unit 3 operational amplifier 4 smoothing filter 5, 5a to 5g, 5 _{G1 to} 5 _G4 sinusoidal pulse generator Qa to Qg, Q _{G1 to} Q _G4 FET SW _{1 to} SW ₃ switch Circuit Sa to Sg Segment terminal G _{1 to} G ₄ Grid terminal

Claims (7)

[Claims] 1. A display device which performs a display operation by driving each display minimum unit by a dynamic drive system, wherein the drive voltage applied to each display minimum unit is changed within the display period. A display device characterized by. 2. The display device according to claim 1, wherein the minimum display unit is a display dot pixel. 3. The display device according to claim 1, wherein the minimum display unit is a display segment. 4. The display period of the display minimum unit is defined by both the drive voltage applied to each display minimum unit and the drive voltage commonly applied per digit formed by a predetermined number of display minimum units. The display device according to claim 1, 2, or 3, wherein the display device is configured to be changed within the display device. 5. The applied drive voltage is a stepwise continuous rectangular wave obtained by combining a plurality of pulses, claim 1, claim 2, claim 3, or claim. Item 5. The display device according to item 4. 6. The applied drive voltage waveform is a voltage waveform obtained by supplying a smoothing filter means with a stepwise continuous rectangular wave obtained by combining a plurality of pulses. The display device according to claim 1, claim 2, claim 3, or claim 4. 7. The display according to claim 1, claim 2, claim 3, or claim 4, wherein the applied drive voltage waveform is a voltage waveform whose voltage value changes continuously. apparatus.