JPH0666771B2 - Phase synchronization circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a phase locked loop circuit suitable for clock recovery.

[Technical background of the invention and its problems]

In recent years, various so-called high-definition television systems have been proposed which are capable of transmitting higher-definition images than the NTSC color television system, and one of them has been proposed: Ninomiya et al., "Satellite 1 channel of high-definition television. Transmission method (M
USE) ”Television Society Technical Report, TEBS 95-
2, MUSE (Multiple, which was proposed in March, 1984
Sub-Nyquist Sampling Encoding).

In the MUSE method, image information represented by sample values for each grid point is thinned out and transmitted according to a predetermined rule in order to reduce the frequency bandwidth required for signal transmission as much as possible. This is a method of approximating grid point information that has not been transmitted by using inter-frame interpolation. In this method, the grid point information to be transmitted has a fixed sampling period, for example, 1 / (16.2MHz)
It is transmitted as a PAM (Pulse Amplitude Modulation) signal with a period, but in order to save the transmission bandwidth, the baseband conversion total transfer characteristic is a Nyquist condition, that is, the sample value of an isolated pulse is t = nT (n ≠ 0, T is a sampling period). ), The band is selected as narrow as possible within the range satisfying the condition of becoming 0. Therefore, if the phase of the sampling clock of the PAM demodulator (sampling circuit) on the receiving side deviates even slightly from the original phase, inter-sample crosstalk occurs in the demodulated output accordingly. This crosstalk between samples will eventually lead to a reduction in the resolution in both the horizontal and vertical directions on the playback screen, so it must be kept as small as possible in the MUSE system intended for high-quality image transmission. That is, in the MUSE system, it is necessary to synchronize the phase of the sampling clock on the receiving side with the clock on the transmitting side very accurately.

By the way, in the MUSE system, the sampling clock itself is not transmitted, and instead, HD (horizontal synchronization) signals and FP (frame pulse) signals as shown in FIGS. 2A and 2B are transmitted as synchronization signals. Has been done. The HD signal is inserted at the head of each horizontal scanning line signal. One horizontal scanning line has a clock cycle of T = 1 / (16.2 MH
z) has a length of 480T, but its first to twelfth
The sampling points are defined as shown in FIG. On the other hand, the FP signal is inserted into one set of two adjacent horizontal scanning lines in one frame consisting of 1125 horizontal scanning lines, and is defined as shown in FIG. 2 (b).

As described above, both the HD signal and the FP signal are created by dividing the clock frequency (16.2 MHz), and the waveform of the HD signal is a waveform in which the amplitude value at the sampling time is accurately specified. Therefore, the receiving side can regenerate the sampling clock based on the HD signal.

To recover the sampling clock on the receiving side, concretely, oscillate by the phase comparator with the received input signal as one input, the loop filter with the output of this phase comparator as the input, and the output of the loop filter. This is performed using a phase locked loop circuit composed of a voltage controlled oscillator whose frequency is controlled. That is, the internal FP created internally based on the FP signal detected from the input signal and the output of the voltage controlled oscillator.
The voltage-controlled oscillator is controlled by the phase error signal obtained by phase comparison with the signal, and the phase error of the sampling clock obtained at the output of the voltage-controlled oscillator is controlled within a certain range. By controlling the voltage-controlled oscillator with the phase error signal obtained by the phase comparison between the signal and the internal HD signal created internally based on the output of the voltage-controlled oscillator, the phase error of the sampling clock can be made very close to zero. By including the sampling clock, the sampling clock that is correctly phase-synchronized with the clock on the transmitting side is reproduced.

However, in such a phase locked loop circuit, there is a problem that the phase jitter of the sampling clock occurs due to the noise component contained in the input signal. That is, in the circuit including the phase locked loop for the HD signal as described above, the amplitude variation range of the original phase error signal is very narrow. Therefore, if the input signal contains large noise, the amplitude of the noise component is The amplitude variation range of the original phase error signal is exceeded, and the oscillation phase of the voltage controlled oscillator fluctuates excessively regardless of the original phase error. The magnitude of this phase jitter is determined by the S / N of the input signal and the parameters (loop gain, damping coefficient) of the phase locked loop, and generally, when trying to reduce the phase jitter, the pull-in characteristic of the phase locked loop deteriorates. is there.

In the MUSE system, such phase jitter of the sampling clock causes amplitude fluctuation of the sample value and directly leads to deterioration of image quality. Therefore, the phase jitter must be suppressed as small as possible. On the other hand, the frequency pull-in range and pull-in time of the phase locked loop must also meet certain required specifications. However, the suppression of the phase jitter and the improvement of the pull-in characteristic are generally conflicting requirements as described above, and it is difficult to satisfy both requirements at the same time, especially when the S / N of the input signal is low.

[Object of the Invention]

An object of the present invention is to provide a phase locked loop circuit which can obtain a recovered clock with less phase jitter due to noise contained in an input signal.

[Outline of Invention]

The phase locked loop circuit according to the present invention, through a loop filter, a phase error signal having an amplitude corresponding to the phase difference between both signals output from a phase comparator that compares the phase of the output signal of the voltage controlled oscillator with the phase of the input signal. In a phase-locked circuit that is supplied as a control voltage to a voltage-controlled oscillator to control its oscillation frequency, a phase error that can occur at the output of the phase comparator when the amplitude limit range has no noise component in the input signal It is characterized in that an amplitude limiter set to a range substantially equal to or smaller than the amplitude change range of the signal is inserted between the phase comparator and the loop filter.

〔The invention's effect〕

If the input signal contains a large noise component, the output of the phase comparator will exceed the amplitude change range of the phase error signal due to the phase difference between the original input signal and the output signal of the voltage controlled oscillator. A signal of amplitude is generated.

According to the present invention, between the phase comparator and the loop filter, the amplitude variation range of the phase error signal that can occur at the output of the phase comparator when there is no noise component in the input signal is approximately equal to or By inserting an amplitude limiter having an amplitude limit range set to a narrower range than the amplitude change range, and suppressing a large-amplitude signal due to the noise component described above by this amplitude limiter, Since the fluctuation of the oscillation phase is suppressed, it is possible to reproduce the clock with less phase jitter.

Example of Invention

FIG. 1 shows an embodiment in which the present invention is applied to a sampling clock reproducing phase locked loop circuit on the receiving side in MUSE television transmission. In the figure, a baseband television signal including HD signal and FP signal shown in FIGS. 2 (a) and 2 (b) is applied to an input terminal 1, and first an A / D converter 2 converts it into a digital signal of about 8 bits. To be converted. The A / D converter 2 operates by a sampling clock supplied from a VCXO (voltage controlled crystal oscillator) 12. The VCXO 12 may be an oscillator that directly outputs the required sampling clock frequency of 16.2 MHz, or may be a combination of an oscillator and a frequency divider that oscillates at another frequency having a fixed ratio with 16.2 MHz. .

The output of the A / D converter 2 is divided into two parts, one of which is introduced into an FP (frame pulse) detection circuit 3 and the other of which is introduced into a phase comparison circuit (hereinafter referred to as HD phase comparison circuit) 5 for an HD (horizontal synchronization) signal. . FP of the outputs of the A / D converter 2
The input to the detection circuit 3 is the MSB (Most Significa
nt Bit) is enough. The function of the FP detection circuit 3 coincides with that during the output of the A / D converter 2, paying attention to the fact that the FP signal has a waveform of a specific shape defined as shown in FIG. It is to detect the time when the pattern appears. That is, in the MSB sequence of the output of the A / D converter 2, a binary pattern as shown in FIG.
The binary pattern obtained by reversing is to detect the event that it exists with a shift of exactly 480 clocks. In the binary pattern series of FIG. 3, the time of the first “1” (indicated by □) of the last sequence of “1” is called a detected FP point, and the time of the FP signal detected from the input signal. Use as a reference.

On the other hand, the output of the VCXO 12 is divided into 1 / (480 × 1125) by the frequency dividing circuits 13 and 14, and a phase synchronization circuit (hereinafter referred to as FP phase comparison circuit) 4 for the FP (frame pulse) as an internal FP signal of 30 Hz 4 Will be introduced to. F
In the P phase comparison circuit 4, the detected FP point is compared with the rising point of the internal FP signal, for example, to determine which one comes first. However, if both are exactly 30Hz
When they are offset from each other by 1/2, it may be determined which is first. This determination result is "1", "-1",
It is sent to the digital integration circuit 9 as a ternary signal of "0" (deviation is within ± 1 clock). Digital integration circuit 9
Increases or decreases the integration result by one unit according to the determination result of the FP phase comparison circuit 4. However, when the determination result of the FP phase comparison circuit 4 is "0", the integration result up to that point is held.
The output of the digital integrator circuit 9 passes through the adder 10 and D / A.
It is supplied to the converter 11 and converted into an analog voltage. The oscillation frequency of the VCXO 12 is controlled by the output voltage of the D / A converter 11, but if the internal FP signal lags behind the detected FP point in the FP phase comparison circuit 4, the oscillation frequency of the VCXO 12 is increased. Set to the direction.

The above-mentioned "VCXO12-frequency divider circuits 13, 14-FP
A first phase-locked loop is formed by a loop composed of the phase comparison circuit 4 to the digital integration circuit 9 to the D / A converter 11 to the VCXO 12 ", and the oscillation frequency of the VCXO 12 will eventually be increased by the action of this phase-locked loop. It becomes almost equal to the transmission clock frequency, and the timings of the internal FP signal and the detected FP point also coincide within a range of ± 1 clock.

When entering this state, the output of the FP phase comparison circuit 4 becomes "0" in principle, and in response to this, the switch 8 "opens".
Becomes "closed". After that, by joining the first phase-locked loop including the FP phase comparison circuit 4 described above, "VCXO
12-dividing circuit 13-phase comparator 16-amplitude limiter 6
~ Loop filter 7 ~ D / A converter 11 ~ VCXO1
A second phase locked loop, consisting of a 2 "loop, also begins operation. However, the phase comparator 16 is a phase comparator in the second phase-locked loop, and the A / D conversion circuit 2 and the HD
This is a part configured with the phase comparison circuit 5.

The HD phase comparison circuit 5 is specifically realized by the configuration shown in FIG. That is, the sample value series consisting of the 8-bit parallel signal from the A / D converter 2 is a four-stage shift register 21-24, coefficient circuits 26, 27, adder circuit 2
5, 28, and the shift register 29 to output as a phase error signal. Here, the shift registers 21 to 24 are A
The shift register 29 is driven by an internal HD signal obtained by dividing the sampling clock by 1/480, while being driven by a 16.2 Hz sampling clock like the / D converter 2. The calculation performed by the phase comparator 10 is expressed by the following equation. Input waveform x to A / D converter 2
(t) is obtained by taking the sixth sampling point, which is the center of the HD signal waveform shown in FIG. 2, as the time origin (t = 0), Is.

Now, the sampling clock phase error is φT (seconds)
(That is, the time origin is shifted by φT). Where φ is the phase error of the sampling clock T
It has been normalized with. In this case, the output y (t) of the adder circuit 28 in the phase comparison circuit 5 shown in FIG. 4 (the value is actually held during the sampling interval T, but for simplicity, it will be described as an analog waveform). Can be expressed as:

That is, the output of the A / D converter 2 that is the input of the HD phase synchronization circuit 5 is a quantized sample value sequence (8 bits) at the sampling interval T. However, for simplification of explanation,
It is expressed as x (t + φT) using the analog signal notation. The inputs of the adder circuit 25 are the output x (t + φT) of the A / D converter 2 and x (t + φT-4T) delayed by 4T by the shift registers 21 to 24. The input of the adder circuit 28 is the output of the adder circuit 25 in the coefficient circuit 26.
1/2 and the output x (t + φT) of the A / D converter 2 delayed by 2T by the shift registers 21 to 22x
The coefficient circuit 27 multiplies (t + φT-2T) by -1.
Therefore, the output y (t) of the adder circuit 28 becomes as shown in the equation (1) '.

Generally, the phase comparison characteristics of the phase locked loop (in this case,
The characteristic indicating the relationship between the output y of the HD phase comparator 5 and the phase error φ of the sampling clock is symmetric with respect to the point of φ = 0 as shown in FIG. 5, and when φ = 0. It is desirable that the value of the internal HD signal be equal to the value x (0) at the time origin t = 0 of the HD signal waveform shown in FIG.

To this end, the internal HD that drives the shift register 29
The signal (cycle 480T) timing is (1) ′ when φ = 0.
Since the second term x (t + φT-2T) on the right side of the equation may be set to x (0), the timing of the internal HD signal is set to t = 2T. At this time, the output y of the phase comparator 10 is the sample value y of the output y (t) of the adder circuit 28 at t = 2T.
Since (2T) is latched in the shift register 29, Becomes

Where t of x (t) is φT-2T, φT + 2T, φ
If the items replaced by T are the terms on the right-hand side of equation (1), the terms on the right-hand side of equation (1) are as follows.

From this, y in equation (1) is Becomes The fifth is shown with φ as the horizontal axis and y as the vertical axis.
The phase comparison characteristics shown in the figure are symmetrical. Although y is a periodic function with a period of 480 with respect to φ, only the limited section of −3 <φ <3 shows the phase comparison characteristic. For the other sections, the phase comparator 1
No meaningful information is obtained from 6 regarding the phase error φ of the sampling clock.

The output of the phase comparator 16, that is, the output of the HD phase comparison circuit 5 is amplitude-limited by the amplitude limiter 6 as will be described later, and then the loop filter 7 having a predetermined transfer characteristic, the changeover switch 8, the addition circuit 10 and D / It becomes a control input of the VCXO 12 via the A converter 11, and another phase locked loop is formed here. While the role of the first phase-locked loop for the FP signal was to keep the phase error φ of the sampling clock within the range of −1 <φ <1, the role of the phase-locked loop for the HD signal was Is to keep φ very close to zero.

Here, in the HD phase comparison circuit 5 shown in FIG. 4, the input to the addition circuit 28 is a path through which the output of the A / D converter 2 is input through the shift registers 21 to 24, the addition circuit 25 and the coefficient circuit 26. (a) and a path through which the output of the A / D converter 2 is input through the adder circuit 25 and the coefficient circuit 26
There are three systems of (b) and the route (c) in which the output of the A / D converter 2 is input via the coefficient circuit 27. If the noise waveform included in the input signal (output of the A / D converter 2) is n (t), then (a)
The signals input to the adding circuit 28 from the paths (b) and (c) are
{X (t + φT-4T) + n (t + φT-4T)}, {x (t + φT)
+ N (t + φT)} and {x (t + φT-2T) + n (t + φT-2
T)}, which is a signal at a time position separated from each other by 2T or 4T.

In terms of noise, not only in the case of wideband noise, even if the band is limited by a low-pass filter with a cut-off frequency of (1 / 2T) [Hz], it is possible to separate it by a time of 2T or more. When observed, they can be considered to be almost independent of each other, so that the signals input to the adder circuit 28 from the paths (a), (b), and (c) are added not in terms of voltage but in terms of power. Of these, the signals passing through the paths (a) and (b) are multiplied by the coefficient 1/2 in voltage in the coefficient circuit 26, so that the noise components are (1/2) ² = It becomes 1/4 times. On the other hand, since the signal passing through the path of (c) is multiplied by the coefficient -1 in voltage in the coefficient circuit 27, the power of the noise component is (-1) ² = 1 times. Therefore, when the signals passing through the three paths (a), (b), and (c) are power-added by the adder circuit 28, the noise component is (1/4) + (1/4) + 1 = 1.5, that is, 1.5. Doubled and converted to voltage Becomes This noise component is generated by the loop filter 7 and D / A.
When applied to the control input terminal of the VCXO 12 via the converter 11, the oscillation frequency of the VCXO 12 fluctuates randomly, resulting in phase jitter in the sampling clock obtained at the output terminal 15. According to the present invention, such a problem is solved by inserting the amplitude limiter 6 between the phase comparator 16 and the loop filter 7. The operation of the amplitude limiter 6 will be described below.

As described above, when the sampling clock supplied to the A / D converter 2 has the phase error φ, the output y of the phase comparator 16 becomes as shown in FIG. 5 as a function of the phase error φ. . The amplitude variation range of the output y of the phase comparator 16 is as shown in FIG.
-64/256 to 64/256.

That is, in the HD signal waveform shown in FIG. 2, the A / D converter 2 has 8-bit accuracy and the output dynamic range is 1/256.
It was drawn as ~ 256/256. The video signal uses the entire dynamic range, but the HD signal x (t) uses the central range of 64/256 to 192/256. Dynamic range of A / D converter 2 is 1/25
6 to 256/256 is not particularly important, as long as the HD signal fits within the dynamic range of the A / D converter 2 with a margin.

As shown in FIG. 4, such an HD signal x (t) is divided into the three paths (a), (b) and (c) which are shifted in time from each other, and the addition circuit 28 is added, and then the shift register is added. When latched at the above-mentioned timing in 29, the output of the shift register 29 will be as shown in FIG.
Takes any value within the range of -64/256 to 64/256 depending on the phase error φ.

However, when the input signal of the phase comparator 16 contains noise, the output y obtained as a result of the calculation of the equation (1) may exceed this range depending on the magnitude of the noise. That is, when the S / N of the input signal is low, the phase comparator 16
At the output of, there may be a large amplitude signal that should not have been caused by the phase error φ of the sampling clock.

The amplitude limiter 6 is for suppressing an output based on such a noise component, and its amplitude limit range is, for example, a phase error signal that may occur in the output of the phase comparator 16 when the input signal does not have a noise component, in other words, Then, the amplitude change range of the original phase error signal caused only by the phase error φ of the sampling clock is set to be substantially equal to -64/256 to 64/256. As a result, no matter what kind of instantaneous amplitude noise is mixed in the input signal, the amplitude change range of the signal supplied to the loop filter 7 is the amplitude change of the original phase error signal caused by the phase error of the sampling clock. It does not exceed the range. The amplitude limiter 6 handles a digital signal in this example, and can be realized by using, for example, a ROM. That is, RO is a table showing the relationship between the phase error φ before amplitude limitation and the phase error φ ′ after amplitude limitation.
It may be configured such that it is stored in M and φ ′ is read using φ as an address. An example of this table is shown in the following table.

By providing such an amplitude limiter 6, the VCXO 1 via the loop filter 7 and the D / A converter 11
The noise component contained in the control input supplied to 2 is suppressed, and as a result, the sampling
The phase jitter of the clock is suppressed. Moreover, since the amplitude limiter 6 has almost no effect on the original phase error signal, the insertion of the amplitude limiter 6 does not cause any adverse effect such as deterioration of the pull-in characteristics (pull-in frequency range and pull-in time) of the phase locked loop.

In the above description, the amplitude limit range of the amplitude limiter 6 is almost equal to the original output change range of the phase comparator 16, but it may be set to a narrower range. In that case, although the pull-in characteristic of the phase-locked loop is somewhat sacrificed, the noise suppression effect is further improved.

FIG. 6 shows another embodiment of the present invention, in which an amplitude limiting range setting circuit 17 is further added to the phase locked loop circuit of FIG. The amplitude limit range setting circuit 17 is a circuit for setting the amplitude limit range of the amplitude limiter 6 by switching to a plurality of types, and as an example, -64/256 to 64/256 and -8 /
It can be set by switching to 2 types of 256 to 8/256.

With the amplitude limit range setting circuit 17, the amplitude limiter 6
The amplitude limit range of is larger than the wide range for a predetermined time after the switch 8 is opened to closed and the second phase-locked loop related to the HD signal starts operating.
Set to 4/256 to 64/256 and thereafter set to -8/256 to 8/256. In this way, since the same operation as in the embodiment of FIG. 1 is performed in the transient state of the phase locked loop, the pull-in characteristic of the phase locked loop is not impaired and the steady state in which the phase locking is established is established. Since the phase error φ is usually sufficiently small in (1), the effect of excessive noise is effectively suppressed by the amplitude limiter 6 whose amplitude limit range is set to be narrow without causing synchronization loss. In addition,
Should the phase synchronization be lost and the phase error φ exceeds ± 1, this is detected by the FP phase comparison circuit 4, so that the switch 8 is once opened and the operation is restarted from the beginning.

The present invention is not limited to the above embodiment,
For example, in the embodiment, the example in which the present invention is applied to the phase synchronizing circuit for clock reproduction on the receiving side in the MUSE type television transmission has been described, but the present invention can be applied to various other phase synchronizing circuits. is there. Further, the present invention can also be applied to a phase locked loop circuit in which an A / D converter or a D / A converter is not included in the phase locked loop and the phase comparator and the loop filter are analog circuits. In addition, the present invention can be variously modified and implemented without departing from the scope of the invention.

[Brief description of drawings]

FIG. 1 is a block diagram of a phase locked loop circuit according to an embodiment of the present invention.
2 (a) and 2 (b) are waveform diagrams of the horizontal synchronizing signal and the frame pulse inserted in the transmission signal in the MUSE system, and FIG. 3 is a diagram showing a binary pattern detected by the frame pulse detection circuit, FIG. Is a concrete configuration diagram of the phase comparison circuit for the horizontal synchronization signal, and FIG. 5 is the output of the phase comparator including the phase comparison circuit for the horizontal synchronization signal and sampling /
FIG. 6 is a characteristic diagram showing the relationship with the phase error of the clock, and FIG. 6 is a block diagram of the phase locked loop circuit of another embodiment of the present invention. 5 ... Phase comparison circuit for horizontal sync signal, 6 ... Amplitude limiter, 7 ... Loop filter, 12 ... Voltage controlled oscillator, 16 ... Phase comparator, 17 ... Amplitude limiting range setting circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masatoshi Mann, 2-2-1 Jinnan, Shibuya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Center (56) Reference JP-A-54-148410 (JP, A)

Claims (2)

[Claims] 1. A voltage-controlled oscillator, and a phase comparator which compares the phases of an output signal and an input signal of the voltage-controlled oscillator and outputs a phase error signal having an amplitude corresponding to the phase difference between the two signals, An amplitude limiter that limits the amplitude of the phase error signal output from the phase comparator to a predetermined amplitude limit range, and a loop filter that receives the output of this amplitude limiter and controls the oscillation frequency of the voltage controlled oscillator by the output. Wherein the amplitude limiter has an amplitude limit range substantially equal to an amplitude change range of a phase error signal that can occur at the output of the phase comparator when a noise component does not exist in the input signal,
Alternatively, the phase-locked loop circuit is characterized in that it is set to a range narrower than the amplitude change range. 2. The amplitude limiter according to claim 1, wherein the amplitude limit range is set to a narrower range as time elapses after the operation of the phase locked loop is started. Phase synchronization circuit.