JPH0661235A - Semiconductor integrated circuit substrate, semiconductor integrated circuit device using the substrate, and their production - Google Patents

Abstract

PURPOSE:To improve the electrical reliability and the production yield of an SOI structure semiconductor integrated circuit device by providing a gettering layer on a junction interface between the top layer wafer (substrate on a semiconductor element forming side) of an SOI substrate formed by using wafer laminating technique an insulating layer. CONSTITUTION:A gettering layer 40 composed of a high-concentration implanting layer, a polycrystalline silicon layer, etc., is provided directly above the burying oxide layer 30 of an SOI structure semiconductor integrated circuit substrate 10 by using wafer laminating technique. Namely, the SOI structure semiconductor integrated circuit substrate 10A is composed of the semiconductor supporting substrate 10 (first substrate) composed of single crystal silicon, the insulating layer 30 composed of silicon oxide film on the substrate 10 and the gettering layer 40 composed of the polycrystalline silicon layer on the insulating layer 30. A semiconductor thin film layer 20a composed of single crystal silicon is provided on the gettering layer 40 and the substrate 10A is formed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an gettering (gettering) technique of a semiconductor integrated circuit device, in particular, a silicon thin film layer formed on the insulating layer, a semiconductor element is formed on the silicon thin film layer S ilicon o n i nsulator (hereinafter S
The present invention relates to a technique effective when applied to a device (referred to as OI).

[0002]

2. Description of the Related Art Recently, a technique for forming a semiconductor device using an SOI substrate has been put into practical use. In the SOI substrate, for example, an insulating layer such as a silicon oxide film is selectively provided in a single crystal silicon substrate (wafer), and a very thin single crystal silicon region on the insulating layer is formed as a semiconductor element formation region. When a semiconductor element is formed in the thin single crystal silicon region, since the insulating layer exists under the semiconductor element, the semiconductor element has essentially low parasitic capacitance and radiation (for example, alpha-ray). Since it has characteristics such as high durability, it has high speed and high reliability.

An example in which a semiconductor integrated circuit device is constructed by using the above-mentioned SOI substrate is described in “I.
Eee Transactions on Electron Devices B / O L-D-32
Number. 3 pp. 589 to 593 "(IEEE TR-
ANSACTIONS ON ELECTRON DEVICES, VOL.ED-32, NO.3, MARC
H 1985 pp589-593).

On the other hand, in the case of manufacturing a semiconductor integrated circuit device using a normal single-layer silicon substrate, heavy metal contamination that leaks the PN junction of the semiconductor element due to heavy metal invading into the silicon substrate during the manufacturing process is prevented. However, in order to improve the yield of the semiconductor integrated circuit device, a method of providing a gettering layer of heavy metal in the silicon substrate has been devised. For example, 1986
No. 150 to No. 157 of "Practical Semiconductor Patent Handbook" published by Science Forum Co., Ltd.
Extrinsic gettering to reduce heavy metal contamination, which reduces reliability of semiconductor devices
sic gettering and intrinsic gettering techniques are disclosed. The extrinsic gettering technique is a technique in which a strained layer is provided on the back surface of a single-layer silicon substrate (wafer) and a heavy metal is fixed in the strained layer. Further, the above-mentioned intrinsic gettering technique forms a high-density minute defect region in the substrate by precipitating oxygen in the substantially central portion of a single-layer silicon substrate (wafer), and captures heavy metals in the defect region. This is a technique, and a semiconductor active element is formed on the remaining surface portion of the silicon substrate other than the above-mentioned defective area.

[0005]

Similar to the case of manufacturing a semiconductor integrated circuit device using the above-mentioned conventional single-layer silicon substrate, the above-mentioned heavy metal is also used in the case of manufacturing a semiconductor integrated circuit device using an SOI substrate. The problem of pollution arises.
That is, in the manufacturing process of the semiconductor integrated circuit device, the SOI
Fe, Cu, P penetrating into the upper silicon thin film layer of the substrate
Heavy metal atoms such as t cause PN junction leakage of semiconductor elements and deterioration of withstand voltage, which causes deterioration of reliability and manufacturing yield of a semiconductor integrated circuit device using an SOI substrate.

Even if the extrinsic gettering technique of the prior art is applied in order to avoid heavy metal contamination of the SOI substrate, a gap between the upper thin single crystal silicon region which is an element formation region and the back surface of the SOI substrate is applied. Since there is a silicon oxide film on the surface, heavy metal atoms cannot be captured. That is, even if the gettering layer is provided on the back surface of the SOI substrate, the diffusion coefficient of heavy metal atoms in the insulating layer (silicon oxide film) is much smaller than that in single crystal silicon.
There is a problem that the heavy metal atoms cannot reach the gettering layer, and the gettering effect cannot be sufficiently exhibited.

Further, even if the conventional intrinsic gettering technique is applied to the SOI substrate, since the film thickness of the upper single-crystal silicon region which is an element forming region is very thin, the element forming region is thin. It is very difficult to accurately form the gettering layer near the lower portion of the single crystal silicon region.

The present invention has been made to solve the above problems and difficulties, and the main object of the present invention is to:
An object of the present invention is to provide a technique for improving the electrical reliability and manufacturing yield of a semiconductor integrated circuit device having an SOI structure.

An object of the present invention is to provide a substrate for a semiconductor integrated circuit device capable of improving the electrical reliability and manufacturing yield of a semiconductor integrated circuit device having an SOI structure, and a method for manufacturing the same.

It is an object of the present invention to provide a semiconductor integrated circuit device having an SOI structure with high electrical reliability and a method for manufacturing the same.

The above objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The typical ones of the inventions disclosed in the present application will be outlined below.

A gettering layer is provided on the bonding interface between the upper layer wafer (semiconductor element formation side substrate) of the SOI substrate using the wafer (substrate) bonding technique and the insulating layer.

Specifically, the semiconductor integrated circuit substrate includes a lower semiconductor supporting substrate, an insulating layer provided on the semiconductor supporting substrate, the insulating layer provided on the insulating layer, and a semiconductor element formed on the insulating layer. It has an upper semiconductor substrate (semiconductor thin film layer) to be formed, and a gettering layer provided at a bonding interface between the insulating layer and the upper semiconductor substrate (semiconductor thin film layer).

The method of manufacturing a substrate for a semiconductor integrated circuit includes: a first semiconductor substrate (lower layer substrate) having a substantially flat first main surface and a second main surface facing it; a substantially flat third main surface; Preparing a second semiconductor substrate (upper substrate) having a fourth main surface facing each other, forming an insulating layer on the first main surface of the first semiconductor substrate, and the second semiconductor After the step of forming a gettering layer having a substantially uniform thickness on the third main surface of the substrate and the step of forming the gettering layer, the first main surface and the second main surface of the first semiconductor substrate are formed. Bonding the semiconductor substrate to the third main surface.

The semiconductor integrated circuit device includes a lower semiconductor supporting substrate, an insulating layer provided on the semiconductor supporting substrate,
An upper semiconductor substrate (semiconductor thin film layer) provided on the insulating layer; and a gettering layer provided at a bonding interface between the insulating layer and the upper semiconductor substrate (semiconductor thin film layer).
And a semiconductor element having a PN junction provided on the main surface of the semiconductor thin film layer, the PN junction of the semiconductor element being provided at a distance from the gettering layer.

According to the method of manufacturing a semiconductor integrated circuit device, a first semiconductor substrate (lower layer substrate) having a substantially flat first main surface and a second main surface opposed thereto, and a substantially flat third main surface opposed thereto. A second semiconductor substrate (upper layer substrate) having a fourth main surface, a step of forming an insulating layer on the first main surface of the first semiconductor substrate, and the second semiconductor substrate. The step of forming a gettering layer having a substantially uniform thickness on the third main surface, and the step of forming the gettering layer, the first main surface of the first semiconductor substrate and the second semiconductor Joining the third main surface of the substrate, and etching the second semiconductor substrate to a predetermined thickness from the fourth main surface side of the second semiconductor substrate toward the third main surface side. To form a semiconductor thin film layer having a predetermined thickness And extent, and a step of forming a semiconductor device having a PN junction on the main surface of the semiconductor thin film layer.

The semiconductor integrated circuit device is provided with a semiconductor supporting substrate, an insulating layer provided on the semiconductor supporting substrate, a semiconductor thin film layer provided on the insulating layer, and a main surface of the semiconductor thin film layer. A plurality of semiconductor elements having a PN junction, a gettering layer provided at a junction interface between the insulating layer and the semiconductor thin film layer, and extending below the plurality of semiconductor elements; And a separation groove extending from the surface toward the semiconductor supporting substrate, reaching the insulating layer through the gettering layer, and separating the plurality of semiconductor elements from each other.

[0019]

According to the above means, the gettering layer and the element formation region (upper substrate or semiconductor thin film layer) of the substrate for a semiconductor integrated circuit device having an SOI structure are formed close to each other. Since there is no region between the region and the gettering layer that prevents the diffusion of heavy metal atoms, the heavy metal atoms that have penetrated into the element formation region during the semiconductor device manufacturing process easily reach the gettering layer and are gettered. Therefore, it is possible to prevent or reduce the contamination of the element forming region by the heavy metal atoms, and it is possible to improve the electrical reliability and the manufacturing yield of the semiconductor integrated circuit device.

In forming a substrate for a semiconductor integrated circuit device having an SOI structure, two independent semiconductor substrates (first semiconductor substrate and second semiconductor substrate) are used, and the two independent semiconductor substrates are used. Since the gettering layer is formed on the main surface of one of the two independent semiconductor substrates (second semiconductor substrate) before the substrates are bonded to each other with the insulating layer interposed therebetween, the gettering layer is formed into the SOI structure. The semiconductor integrated circuit device substrate can be easily and accurately formed in the vicinity of the lower portion of the element formation region.

Further, since the isolation groove that reaches the insulating layer through the gettering layer and separates the plurality of semiconductor elements from each other is formed, it is caused by a crystal defect or a crystal lattice strain existing in the gettering layer. Since a possible leak current can be prevented between the semiconductor elements, the electrical reliability of the semiconductor integrated circuit device having the SOI structure can be improved.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a partially enlarged cross section of a semiconductor integrated circuit substrate having an SOI structure according to the present invention. Reference numeral 1 is a lower silicon semiconductor wafer (substrate), which functions as a supporting substrate. is doing. A silicon oxide film 2, which is an insulating film, is formed on the lower layer silicon semiconductor wafer 1, and an upper layer silicon semiconductor thin film 3 is further formed thereon.

Here, the thickness of the lower layer silicon semiconductor wafer 1 is not particularly defined by the characteristics of the semiconductor device itself having the SOI structure, but is defined by the mounting height limitation such as packaging of the formed semiconductor device. To be done. Also,
The thickness of the silicon oxide film 2 is about several thousand Å.

The thickness of the upper silicon semiconductor thin film 3 is several μ.
It is about m to several tens of μm. On the lower side of the upper silicon semiconductor thin film 3, that is, on the side closer to the interface with the silicon oxide film 2, the concentration of crystal defects such as misfit dislocations, lattice defects, stacking faults, dislocation loops or dislocation networks becomes high. The gettering layer (gettering /
Site) 3a. On the other hand, above it is this S
This is a region provided for forming an element such as a transistor when forming a semiconductor device using an OI substrate, that is, an element active region 3b.

The element active region 3b has a thickness of several μm.
For example, it is about 2 to 3 μm. On the other hand, the thickness of the gettering site 3a may be such that it does not reach the element active region 3b located above the gettering site 3a.

Next, the manufacturing process of the semiconductor integrated circuit substrate having the SOI structure will be described with reference to FIGS.
A description will be given based on (D).

First, one surface of a semiconductor wafer to be the upper layer silicon semiconductor thin film 3 (see FIG. 1), for example, a silicon semiconductor wafer 3c is mirror-finished, and then a gettering site is applied from the mirror surface side by an extrinsic gettering method. 3a is formed. Gettering site 3
The a is formed by, for example, high-concentration phosphorus diffusion or ion implantation. The state up to this point is shown in FIG.

Next, the mirror surface of the silicon semiconductor wafer 3c is thermally oxidized to form a silicon oxide film 2 of about several thousand liters.
The state up to this point is shown in FIG.

After that, the silicon semiconductor wafer 3c is placed on the lower layer silicon semiconductor wafer 1 to serve as a supporting substrate and heat-treated to bond the two. The state up to this point is shown in FIG.

Finally, the silicon semiconductor wafer 3c is polished to a desired thickness, for example, several μm to several tens of μm to form a semiconductor thin film, that is, an upper silicon semiconductor thin film 3. The lower part of the upper silicon semiconductor thin film 3 is the gettering site 3a, and the upper part thereof is the device active region 3a.
b. Thus, the SOI substrate having the gettering site (3a) immediately below the element active region as shown in FIG. 2D is manufactured.

Here, the gettering sites 3a were formed first by high-concentration phosphorus diffusion or by ion implantation, but although not shown in the drawing, another example will be described. One surface of the silicon semiconductor wafer 3c is explained. After mirror finishing, a silicon nitride film is deposited on the mirror surface by the vapor growth method and heat-treated in a nitrogen gas atmosphere to generate misfit dislocations or the like due to thermal stress near the mirror surface of the silicon semiconductor wafer 3c. After that, the silicon nitride film is removed by using phosphoric acid. At this time, by controlling the gettering site forming conditions such as the film thickness of the silicon nitride film and heat treatment, the gettering site 3a is formed in a shallow region of several μm, for example, 1 to 2 μm from the mirror surface of the silicon semiconductor wafer 3c. Can be formed.

According to the SOI substrate of Example 1 described above, the following effects can be obtained.

That is, in the semiconductor device formed using the SOI substrate of this embodiment, the gettering site 3a is formed between the element active region 3b and the silicon oxide film 2, so that the semiconductor device is manufactured. Heavy metal atoms such as Fe, Cu and Pt that have penetrated into the element active region 3b diffuse into the upper silicon semiconductor thin film 3 and reach the gettering site 3a to be gettered. Therefore, the reliability and the manufacturing yield of the semiconductor device formed using the SOI substrate can be improved.

Before the SOI substrate is formed, the gettering site 3a is formed on the silicon semiconductor wafer 3c in advance, and the gettering site 3a is bonded to the gettering site 3a. The silicon oxide film 2 is not damaged during the formation of 3a. Therefore, the element active region 3b is formed immediately above the interface between the silicon oxide film 2 and the silicon semiconductor film 3c thereon without degrading the characteristics of the silicon oxide film 2.
The gettering site 3a can be formed in the lower part of the.

Although the mirror surface of the silicon semiconductor wafer 3c on which the gettering site 3a is formed is thermally oxidized to form the silicon oxide film 2 according to the first embodiment, the invention is not limited to this. The mirror surface of the lower layer silicon semiconductor wafer 1 as a supporting substrate may be thermally oxidized, or the mirror surfaces of both the wafers 3c and 1c may be thermally oxidized to form the silicon oxide film 2.

Further, according to another example of the first embodiment, after the silicon nitride film is removed by using phosphoric acid after the occurrence of misfit dislocations or the like in the step of forming the gettering site 3a, the SOI in the next step. Although the silicon oxide film 2 as the insulating film having the structure is formed, the silicon nitride film may be left and the silicon nitride film may be used as the insulating film having the SOI structure. By doing so, it is not necessary to remove the silicon nitride film and form the silicon oxide film 2, so that the throughput can be improved and the manufacturing cost can be reduced.

Further, according to the first embodiment, an example has been described as a method of forming the gettering site 3a by the extrinsic gettering method.
Another forming method, for example, a method of spraying fine particles of silicon oxide on the mirror surface of the wafer 3c to form a strained layer, or a process of implanting ions of inert atoms on the mirror surface of the wafer 3c and then performing heat treatment to form dislocation loops, etc. It may be generated by a method. In the method of implanting the ions of the inert atoms, in order to prevent the mirror surface of the silicon semiconductor wafer 3c from being contaminated by the atmosphere, ion implantation is performed after forming a thermal oxide film, and the thermal oxide film is used as an insulating film having an SOI structure. Also good.

In the above description, the invention made mainly by the present inventor is the field of application which is the background of SOI.
Although the semiconductor substrate having a structure has been described, the present invention is not limited thereto, and SOS (Si on sapphire or sp
It can also be applied to a semiconductor substrate having an inei) structure.

Example 2 FIG. 3 shows Example 2 of the present invention.
2 is a cross-sectional view of an essential part of a semiconductor integrated circuit substrate having an SOI structure. The feature of the second embodiment is that the gettering layer is formed of a polycrystalline silicon layer.

As shown in FIG. 3, a semiconductor integrated circuit substrate 10a having an SOI structure according to the second embodiment includes a semiconductor supporting substrate (first substrate) 10 made of single crystal silicon and silicon oxide provided thereon. An insulating layer 30 made of a film, a gettering layer 40 made of a polycrystalline silicon layer provided on the insulating layer 30, and a semiconductor thin film layer 20a made of single crystal silicon provided on the gettering layer 40.
It is formed by and. The silicon oxide film 30 has a thickness of about several thousand angstroms to several microns. Of course, it is possible to use another insulating film such as a silicon nitride film (SiN) instead of the silicon oxide film 30.

The thickness of the polycrystalline silicon layer 40 is made thin enough to getter the heavy metal atoms, and does not reduce the crystal strength and mass productivity. From the necessity, several hundred angstroms to several microns are suitable.

On the main surface of the semiconductor thin film layer 20a, a bipolar transistor having a normal PN junction, a MOS.
A field effect transistor such as a FET is formed, and the polycrystalline silicon layer 40 joins the insulating layer 30 and the semiconductor thin film layer 20a in order to getter heavy metal atoms that adversely affect the PN junction. It is provided at the interface.

Next, a method of manufacturing the semiconductor integrated circuit substrate 10a will be described with reference to FIGS. 4 (a) to 6 (b).
First, as shown in FIG. 4A, a first substrate (supporting substrate) 10 and a second substrate 20 each made of single crystal silicon having a thickness of about 600 μm are prepared. The substrates 10 and 20 are ordinary single crystal silicon wafers, and each of the substrates 10 and 20 is a pair of opposing flat faces (first and second main faces, third and fourth faces) that are substantially parallel to each other and are flat. Main surface). The conductivity type and impurity concentration of the substrates 10 and 20 can be arbitrarily selected according to need. next,
On the main surface (first main surface) of the substrate 10, for example, a thermal oxidation method or C
The buried oxide film of the formed SOI structure silicon oxide film 30 by VD (C hemical V aper D eposition ) process. On the other hand, on the main surface (third main surface) of the substrate 20, for example, LP
Forming a polycrystalline silicon film 40 by using the (L ow P ressure) -CVD method. At this time, what is important is to reduce the surface roughness of each film. In particular, since polycrystalline silicon tends to have a large surface roughness, deposition is performed at a low temperature (approximately 550 ° C. or lower), and immediately after the deposition. After the amorphous state, a heat treatment at about 600 ° C. or more is applied to obtain a polycrystal, or a method of depositing by a usual method and then polishing or the like to reduce the surface roughness is used.

Next, as shown in FIG. 4B, the oxide film 30 side of the two substrates 10 and 20 and the polycrystalline silicon layer 40.
Stick the sides together in a clean atmosphere. After that, heat treatment is performed at a high temperature to increase the adhesive strength. In order to obtain sufficient adhesive strength, it is usually desirable to perform heat treatment at a temperature of 1000 ° C. or higher.

In the manufacturing method shown in FIGS. 4 (a) and 4 (b),
Although an example in which the side of the silicon oxide film 30 and the side of the polycrystalline silicon layer 40 are bonded is shown, as shown in FIGS. 5A and 5B, the silicon oxide film 30 is formed only on the side of the substrate 10 which is a supporting substrate. It is also possible to use a method in which the film 30 and the polycrystalline silicon layer 40 are sequentially formed, and the polycrystalline silicon layer 40 and the single crystal silicon surface of the upper substrate 20 are bonded together. As shown in FIGS. 6A and 6B, the upper substrate 2
Polycrystalline silicon layer 40 and silicon oxide film 30 only on the 0 side
Are sequentially formed, and the silicon oxide film 30 side and the supporting substrate 1 are formed.
It is also possible to use a method of laminating 0 single crystal silicon surfaces.

After forming the SOI structure shown in FIGS. 4 (b), 5 (b) and 6 (b), the substrate 20 side is thinned by grinding or polishing as shown in FIG. Then, a thin film layer 20a which becomes an element forming region of about 1.5 μm is formed. In the case of this example, the thin film was formed by using the mechanical chemical polishing (selective polishing) method. Regarding the mechanical chemical polishing (selective polishing) method, for example, October 2, 1987
It is described in detail on page 200 to page 201 of "SOI formation technology" published by Sangyo Tosho Co., Ltd. The film thickness of the thin film layer 20a left on the oxide film 30 and the polycrystalline silicon layer 40 is not limited to the above film thickness, and can be arbitrarily selected according to the required characteristics of the semiconductor element to be formed. As described above, in the second embodiment, unlike the method of directly forming the gettering layer 3a in the upper semiconductor substrate as in the above-described first embodiment, the gettering layer is different from the semiconductor substrate that will be the element formation region. Since the independent thin film layer (polycrystalline silicon) is used, the thickness, position, etc. of the gettering layer (defect layer, dislocation layer) can be accurately determined in the SOI structure.

(Embodiment 3) FIG. 7 (a cross-sectional view of an essential part) and FIG.
(Principal plan view) shows a hybrid integrated circuit device (hereinafter, referred to as Bi-CMOS) in which a bipolar transistor and a CMOS according to a third embodiment of the present invention are integrated on the same substrate. The Bi-CMOS of the third embodiment is the same as the S of the second embodiment.
It is formed using the semiconductor integrated circuit substrate 10a having the OI structure. The main characteristic point of the third embodiment is the gettering layer 4
0 is separated by an isolation groove.

As shown in FIG. 7, Bi-C according to the third embodiment.
The MOS is formed on the main surface of the epitaxial layer 60 provided on the main surface of the semiconductor integrated circuit substrate 10a.
A vertical npn bipolar transistor Tr is provided in the region NPN, and a p-channel MOSFET Q is provided in the region PMOS.
An n-channel MOSFET Qn is formed in each of the p and region NMOSs.

The collector region of the npn bipolar transistor Tr has an n + type buried layer 50a and an n type well region 60.
It is composed of a and n + type regions (collector extraction layers) 110. The base regions are p + type regions (external base regions) 230 and p provided on the main surface of the n type well region 60a.
The mold region (intrinsic base region) 220 is formed. The emitter region is composed of the n + type region 260.

In the n + type semiconductor region 110 which is the collector region of the bipolar transistor Tr, the collector wiring 2
80c is connected. The wiring 280c is connected to the semiconductor region 110 through a connection hole OP3 formed in the interlayer insulating films 270 and 210. The wiring 280c is formed in the wiring forming step of the first layer, and is formed of, for example, an aluminum film or an aluminum alloy film containing an additive (Cu, Si). The base lead electrode 200 is connected to the p + type semiconductor region 230, which is the base region. The base lead-out electrode 200 is connected to the p + type semiconductor region 230 through a connection hole OP1 formed in the interlayer insulating films 270 and 210. Base drawing electrode 20
0 is a refractory metal silicide (WSi) on the polycrystalline silicon film.
₂ , MoSi ₂ , TaSi ₂ , TiSi ₂ ) films are laminated to form a composite film. This polycrystalline silicon film is introduced (or diffused) with a p-type impurity (B) for reducing the resistance value. Further, the base lead-out electrode 200 may be formed of a single layer of a polycrystalline silicon film (p-type).

N + type semiconductor region 26 which is an emitter region
An emitter wiring 280b is electrically connected to 0 through an emitter extraction electrode 250. The emitter extraction electrode 250 passes through a connection hole (not shown) defined by a sidewall spacer 240 formed on the side wall of the base extraction electrode 200, and the n + type semiconductor region 26 is formed.
It is connected to 0. The emitter extraction electrode 250 is formed of, for example, a polycrystalline silicon film into which an n-type impurity is introduced.

The emitter extraction wiring 280b is connected to the emitter extraction electrode 250 through a connection hole OP2 formed in the interlayer insulating film 270.

N-channel MOSFE constituting CMOS
TQn is formed on the main surface of the p-type well region 60b,
The well region 60b, the gate insulating film 120b, the gate electrode 130b, and a pair of n that are a source region or a drain region.
Type semiconductor region 150 and a pair of n + type semiconductor regions 180
It is composed of.

The well region 60b constitutes the channel forming region of the MOSFET Qn. The well region 60b has an impurity concentration of about 10 ¹⁶ to 10 ¹⁷ [atoms / Cm ² ], for example. This well region 60
A p + type buried layer 50b for reducing the resistance value is provided under the b.

The gate insulating film 120b is, for example, a silicon oxide film formed by oxidizing the main surface of the well region 60b, and is formed with a film thickness of about 200 [Å].

The gate electrode 130b is composed of a composite film in which a refractory metal silicide film is formed on a polycrystalline silicon film. The polycrystalline silicon film of the gate electrode 130b is of n-type with n-type impurities introduced (or diffused).

The low impurity concentration semiconductor region 150 is provided closer to the channel forming region than the high impurity concentration semiconductor region 180. This low impurity concentration semiconductor region 15
0, so-called LLD (L ightly D oped D rain ) the structure MO
Configure SFETQn. Low impurity concentration semiconductor region 1
50 is mainly a gate electrode or an insulating film 140b above it.
Is used as an impurity introduction mask, and n-type impurities (for example, P) are introduced by ion implantation.
The semiconductor region 150 having a low impurity concentration is formed on the gate electrode 130.
It is formed in self alignment with b.

The high-impurity-concentration semiconductor region 180 is formed by ion-implanting n-type impurities (for example, As) using the sidewall spacers 170 formed mainly on the sidewalls of the gate electrode 130b as an impurity introduction mask. Has been done. The high impurity concentration semiconductor region 180 is
Since the sidewall spacers 170 are configured to be self-aligned with the gate electrode 130b, the gate electrode 13
0b is self-aligned.

In the semiconductor region 180 which is the source region or the drain region of this MOSFET Qn, the interlayer insulating film 2 is formed.
The wirings 280f and 280g are connected through the connection holes OP6 and OP7 formed in 70 and 210, respectively. The wirings 280f and 280g are the collector wirings 280c,
It is formed of the same conductor film as the emitter wiring 280b.
The p-channel MOSFET Qp forming the CMOS is
The well region 60a, the gate insulating film 120a, the gate electrode 130a, formed on the main surface of the n--type well region 60a,
It is composed of a pair of p-type semiconductor regions 160 and a pair of p + -type semiconductor regions 190 which are source regions or drain regions.

The well region 60a constitutes the channel forming region of the MOSFET Qp. The well region 60a has, for example, 10 ¹⁵ to 10 ¹⁷ [atoms / Cm ² ].
It is composed of a certain impurity concentration. Well region 60a
An n + type buried layer 50a for reducing the resistance value thereof is provided in the lower part of the same as the well region 60b.

The gate insulating film 120a is formed of the above-mentioned MOSFE.
Similar to the gate insulating film 120b of TQn, the same manufacturing process is used.

The gate electrode 130a is the gate electrode 130.
It is composed of a composite film in which a refractory metal silicide film is laminated on the same conductor film as b, that is, a polycrystalline silicon film. The polycrystalline silicon film is p-type by introducing (or diffusing) a p-type impurity having a conductivity type different from the impurity introduced into the polycrystalline silicon film of the gate electrode 130b. Further, it may be n-type with n-type impurities introduced.

The semiconductor region 160 of low impurity concentration is LD
A MOSFET Qp having a D structure is constructed. The low impurity concentration semiconductor region 160 corresponds to the low impurity concentration semiconductor region 1
Like 50, it is formed in self-alignment with the gate electrode 130a. The high impurity concentration semiconductor region 190 is
It is configured to be self-aligned with the gate electrode 130a with the sidewall spacer 170 interposed.

In the semiconductor region 190 which is the source region or the drain region of this MOSFET Qp, the interlayer insulating film 2 is formed.
Wirings 280d and 280e are connected through connection holes OP4 and OP5 formed in 70 and 210, respectively.

Further, the MOSFET Qn and the MOSF
As shown in FIG. 8, the respective gate electrodes 130b and 130a of the ETQp extend up to the thick field insulating film 70 and are connected to the wiring (through wiring holes OP9 and OP8 formed in the interlayer insulating films 270 and 210). (Not shown) are respectively connected.

The npn bipolar transistor T described above
r, p channel MOSFET Qp and n channel MOS
Each of the FETs Qn is isolated by the field insulating layer 70 selectively provided on the main surface of the epitaxial layer 60 and the isolation groove 80 provided under the field insulating layer 70. The pattern of the field insulating layer 70 is shown by a thick solid line in FIG. The field insulating layer 70a is a base of the npn bipolar transistor Tr.
It is provided to separate the collector region 110 from the collector region. The isolation trench 80 extends from the main surface side of the epitaxial layer 60 toward the depth direction of the substrate 10a and reaches the insulating layer 30 through the buried layers 50a and 50b and the polycrystalline silicon layer 40 which is a gettering layer. There is. Separation groove 80
A thin insulating film 90 is provided on the inner surface of the, and polycrystalline silicon 100 is embedded therein to form a dielectric isolation structure. The pattern of the separation groove 80 is shown by the alternate long and short dash line in FIG. As described above, in the present embodiment, the gettering layer is also separated by the separation groove 80, so that it is possible to prevent the inconvenience that the leak current is generated between the elements in the defect layer included in the gettering layer, so that the SOI can be prevented.
It is possible to improve the electrical reliability of the semiconductor integrated circuit device having the structure. In addition, the gettering layer,
npn bipolar transistor Tr, p channel MOS
Since they are provided directly under the formation regions of the FET Qp and the n-channel MOSFET Qn, heavy metal atoms that adversely affect the PN junction such as the base junction are quickly captured, so that the electrical reliability of the semiconductor integrated circuit device having the SOI structure is improved. It is possible to improve the property.

Next, the Bi-CMO having the SOI structure described above.
An example of a method of manufacturing S will be briefly described with reference to FIGS. First, as shown in FIG. 9A, a semiconductor integrated circuit substrate 10a similar to that of the second embodiment is prepared. In this embodiment, the film thickness of the silicon thin film 20a of the semiconductor integrated circuit substrate 10a is set to 1 to 1.5 μm.
After that, the collector resistance of the npn bipolar transistor Tr, the p-channel MOSFET Qp and the n-channel MO
In order to reduce the well resistance of each SFET Qn, high-concentration n-type impurities (for example, antimony, phosphorus) and p-type impurities (for example, boron) are selectively introduced into the silicon thin film layer 20a, and n + type buried. The buried layer 50a and the p + type buried layer 50b are formed. The impurity of the n + type buried layer 50a is replaced by the polycrystalline silicon layer 40 which becomes a gettering layer.
To reach or not to reach the single crystal silicon thin film layer 2
It is possible to arbitrarily select whether to keep it within 0a. Further, the n + type buried layer 50a is required to have a sufficient impurity concentration and depth so that a depletion layer of an emitter or a base junction which will be formed later does not reach the polycrystalline silicon layer 40 serving as a gettering layer. In the case of the example, the impurity concentration of the n + buried layer 50a of the bipolar transistor is set to about 2 × 10 ¹⁵ atoms / Cm ² .

Next, as shown in FIG. 9B, an n-type epitaxial layer 60 is formed on the upper surface of the silicon thin film 20a. The epitaxial layer 60 has, for example, 1.0 μ
It is made of single crystal silicon with a thickness of 3.0 m and is 3.0 ohm cm.
Has a resistance value of degrees. After that, an n-type impurity (for example, phosphorus) and a p-type impurity (for example, boron) are selectively introduced into the epitaxial layer 60, respectively, and the n-type well region 6 is formed.
0a and p-type well region 60b are formed.

Next, as shown in FIG. 9C, a field insulating layer 70 is selectively formed on the main surface portion of the epitaxial layer 60. The field insulating layer 70 is formed by using an oxidation resistant mask such as a silicon nitride film for the npn bipolar transistor Tr, p channel MOSFET Qp and n channel MO.
It is formed by selectively forming on the epitaxial layer 60 in the formation region of the SFET Qn and thermally oxidizing the main surface of the epitaxial layer 60 exposed from the oxidation resistant mask. The field insulating layer 70 is formed by a steam oxidation method at about 100 ° C. to a film thickness of about 500 nm. The field insulating layer 70a is an np formed later.
It separates the base region of the n-bipolar transistor Tr from the collector extraction layer 110, and is formed in the same step as the field insulating layer 70. Next, using an etching mask such as a silicon oxide film or a photoresist (not shown), for example, RIE (Reactive Ion Etching)
The field insulating layer 7 is formed by anisotropic etching such as
A deep groove 80 reaching the buried silicon oxide film 30 from the surface of 0 is formed. Unlike the groove isolation process using a normal bulk wafer, the depth of the groove 80 is not limited to the epitaxial layer 60, the n + buried layer 50a, and the p + type buried layer 50b, but the polycrystalline silicon to be the gettering layer. It is necessary to divide the layer 40 and set the depth to reach the buried silicon oxide film 30. Next, a thin silicon oxide film 90 is formed on the side surface of the silicon exposed by the formation of the groove 80 by, for example, a thermal oxidation method to electrically isolate the silicon oxide film 90.
Then, the polycrystalline silicon 100 is embedded in the groove 80. The thin silicon oxide film 90 may be formed by a deposition type insulating film formed by a low pressure chemical vapor deposition (CVD) method. The polycrystalline silicon 100 is formed on the entire surface of the epitaxial layer 60 including the groove 80 by, for example, CVD (Chemical Vapor Depo).
After thickly depositing polycrystalline silicon by the sition method,
The groove 80 is formed by etching back the deposited polycrystalline silicon to the surface of the epitaxial layer 60.
Can be embedded within. Of course, all variations used in a normal groove isolation process such as a method of filling the inside of the groove 80 with a deposited silicon oxide film formed by the CVD method can be applied. Since the polycrystalline silicon layer 40 serving as a gettering layer is also divided into each region (NPN, PMOS, NMOS) by the formation of the groove 80, a leak current flows between the elements through the gettering layer. It can be prevented.

Next, as shown in FIG. 9D, the upper surface of the deposited polycrystalline silicon 90 is selectively thermally oxidized,
An insulating layer (not shown) integrated with the field insulating layer 70 is formed. Next, the well region 60a of the region NPN
An n + type collector extraction layer 110 is formed by selectively introducing phosphorus (p) with an impurity concentration of, for example, 10 ¹⁵ to 10 ¹⁶ atoms / Cm ² to the main surface of the P by an ion implantation method with energy of about 80 keV. To do.

Next, as shown in FIG. 9E, gate oxide films 120a and 120b are formed on the main surface portions of the n-type well region 60a and the p-type well region 60b, respectively. The gate oxide film is formed to have a film thickness of about 15 to 25 nm by thermally oxidizing the surfaces of the well regions 60a and 60b by a steam oxidation method at about 800 to 900 ° C., for example. Next, an insulating film made of a polycrystalline silicon layer, a tungsten silicide layer, and silicon oxide is sequentially deposited on the entire surface of the substrate including the gate oxide films 120a and 120b by, for example, a CVD method, and the deposited composite film is formed. Is patterned by anisotropic etching such as RIE to form the gate structures GP and GN of the MOSFET Qp and MOSFET Qn, respectively. The gate structure GP includes a gate insulating film 120a and a gate electrode (p
+ Type polycrystalline silicon layer and tungsten silicide layer)
It is composed of 130a and an insulating film 140a. The gate structure GN includes a gate insulating film 120b, a gate electrode (n + type polycrystalline silicon layer and tungsten silicide layer) 130b, and an insulating film 140b from the bottom. The p + -type and n + -type polycrystalline silicon layers of the gate structures GP and GN are formed by selectively introducing p-type and n-type impurities into the deposited polycrystalline silicon layer before patterning the composite film. Formed by. Next, the area NMO
At S, n-type impurities are selectively introduced into the main surface of the p-type well region to form the low-concentration source / drain region 150 of the MOSFET Qn. This n-type impurity is, for example, 1
Phosphorus (p) having an impurity concentration of about 10 ¹³ atoms / Cm ² is used and is introduced by an ion implantation method with an energy of about 50 KeV. The n-type impurities are self-aligned with the gate structure GN. Next, in the region PMOS, a p-type impurity is selectively introduced into the main surface of the n-type well region to reduce the concentration of the source / drain region 1 of the MOSFET Qp.
Form 60. This p-type impurity is, for example, 1 × 10 ¹³
Boron (B) having an impurity concentration of about atoms / Cm ² is used and is introduced by an ion implantation method with an energy of about 40 KeV. The p-type impurities are self-aligned with the gate structure GP.

Next, as shown in FIG. 9F, sidewall spacers 170 are formed on the respective side portions of the gate structures GP and GN. Sidewall spacer 17
0 is formed by depositing a silicon oxide film on the entire surface of the substrate and etching back by anisotropic etching such as RIE by an amount corresponding to the thickness of the deposited silicon oxide film. The silicon oxide film of the sidewall spacer 170 is formed by a CVD method using an inorganic silane gas and a nitric oxide gas as source gases. Sidewall spacer 1
The length of 70 in the gate length direction (channel length direction) is about 1
It is 50 nm.

By the anisotropic etching, the gate insulating film exposed from each of the gate structures GP and GN and the gate insulating film in the formation region of the bipolar transistor Tr are over-etched and removed. At this time, n which is the base of the removed gate insulating film
The silicon layers on the main surface portions of the type well region 60a and the p-type well region 60b are also overetched by a small amount. After forming the sidewall spacers 170, heat treatment is performed at about 800 ° C. in an inert gas (eg, argon gas) atmosphere. By the heat treatment, the silicon oxide film forming the sidewall spacers 170 is densified and the low-concentration source / drain regions 1 are formed.
50 and 160 are activated to recover the damage to the silicon layer due to the overetching.

Next, the bipolar transistors Tr and p
The formation region of the channel MOSFET Qp is covered with a mask (not shown) made of a photoresist film using a photolithography technique. Next, using the mask as an impurity introduction mask, an n-type impurity is introduced into the main surface portion of the p-type well region 60b. The n-type impurities are mainly the gate structure G.
It is introduced in self-alignment with the N and sidewall spacers 170. The n-type impurity is, for example, 10 ¹⁵ to 10
Arsenic (As) having an impurity concentration of about ¹⁶ atoms / cm ² is used and is introduced by an ion implantation method with an energy of about 70 to 90 KeV. By introducing the n-type impurity, the high-concentration source / drain region 180 of the N-channel MOSFET Qn is formed on the main surface of the p-type well region 60b. After that, the mask is removed.

Next, a mask (not shown) having an opening in the formation region of the P-channel MOSFET Qp is formed. The mask is made of a photoresist film formed by a photography technique. Then, using the mask as a mask for introducing impurities, the p-type impurity is used for the n-type well region 6.
It is introduced on the main surface of 0a. The p-type impurity is, for example, 10
Boron fluoride (BF ₂ ) having an impurity concentration of about ¹⁵ to 10 ¹⁶ atoms / cm ² is used and is introduced by an ion implantation method with energy of about 70 to 90 KeV. By introducing this P-type impurity, the high-concentration source / drain region 190 of the P-channel MOSFET Qp is formed. After this, the mask is
Remove.

Next, heat treatment is applied to each of the n-type impurities and the p-type impurities in the high-concentration source / drain regions of the MOSFETs Qn and Qp to recover the damage due to the ion implantation and activate the impurities. The heat treatment is performed at a high temperature of about 850 ° C., for example.
Do about 10 minutes. This high concentration source / drain region 18
By the process of forming 0 and 190, the N-channel MOSFET Qn and the P-channel MOSFET Qp shown in FIG.
Each of is substantially completed.

Next, as shown in FIG.
An electrode 200 for extracting the base of the transistor La is formed. To form the electrode 200 for extracting the base, first, a polycrystalline silicon layer having a film thickness of, for example, about 200 nm is deposited on the entire surface of the substrate by a CVD method, and then a p-type impurity is highly doped in the polycrystalline silicon layer. Introduce to concentration. The p-type impurity is
For example, boron (B) having an impurity concentration of about 10 ¹⁵ to 10 ¹⁶ atoms / cm ² is used and is introduced by an ion implantation method with energy of about 10 to 15 [keV]. Then, the polycrystalline silicon layer having the p-type impurity introduced therein is patterned by anisotropic etching such as RIE. This patterning defines the outer edge of the base extraction electrode 200, and in this state, the region where the intrinsic base 220 is to be formed remains unopened. Next, an interlayer insulating film 210 is formed on the entire surface of the substrate including the patterned polycrystalline silicon layer. The interlayer insulating film 21
0 is formed by a silicon oxide film deposited by the CVD method. Then, a photoresist mask (not shown) for substantially patterning the electrode 200 for extracting the base of the bipolar transistor Tr is formed. The mask is a mask pattern in which the regions where the intrinsic base region and the emitter region of the bipolar transistor Tr are to be formed are opened. Then, the interlayer insulating film 210 and the patterned polycrystalline silicon layer are sequentially and selectively etched using the mask as an etching mask. For the etching, anisotropic etching such as RIE is used. By this etching, the base lead-out electrode 200 is patterned so as to surround the emitter and the intrinsic base region of the bipolar transistor Tr. Then, the mask is removed. Next, a p-type impurity for forming the intrinsic base region 220 is introduced into the main surface portion of the n-type well region 60a. The p-type impurity is boron (B) having an impurity concentration of, for example, about 10 ¹³ to 10 ¹⁴ [atoms / cm ² ] and is introduced by an ion implantation method with relatively low energy. The p-type impurity is the base extraction electrode 2
00 self-aligned.

Next, as shown in FIG. 9H, a sidewall spacer 2 made of an insulating film (silicon oxide film) is formed on the side portion of the patterned base lead-out electrode 200.
40 is formed. The spacer 240 can be formed in the same manner as the sidewall spacer 170 of the MOSFETs Qn and Qp having the LDD structure.

After that, the sidewall spacer 24 is formed.
A polycrystalline silicon layer is formed on the entire surface of the substrate including the opening defined by 0. The polycrystalline silicon layer is
For example, it is formed by the CVD method and has a film thickness of about 150 nm. Next, an n-type impurity is introduced into the polycrystalline silicon layer. The n-type impurity is, for example, 10 ¹⁶ atoms.
Arsenic (As) with high impurity concentration of about / cm ² is used,
It is introduced by the ion implantation method. By introducing this n-type impurity, the polycrystalline silicon layer becomes n + type and becomes a conductor. Next, the polycrystalline silicon layer 15 in the region NPN
A photoresist mask (not shown) is selectively formed thereon. The mask pattern is a pattern for forming an electrode for extracting an emitter of the bipolar transistor Tr.
Next, using the mask as an etching mask, the polycrystalline silicon layer introduced with the n-type impurities is selectively removed by etching. For the etching, anisotropic etching such as RIE is used. By the etching, the emitter extraction electrode of the bipolar transistor Tr is processed into a desired shape. Then, the substrate is heat-treated to introduce the n-type impurities introduced into the n + type polycrystalline silicon layer serving as the emitter leading electrode and the p + type polycrystalline silicon layer serving as the base leading electrode 200. Each of the p-type impurities is drive-in diffused into the main surface portion of the n-type well region 60a. By this drive-in diffusion, the emitter region 260 of the bipolar transistor Tr formed of the n + type semiconductor region and the external base region 230 formed of the p + type semiconductor region are formed, respectively. Also,
The p-type impurities of the intrinsic base region, which are previously introduced into the main surface portion of the n-type well region 60a, are also activated by the heat treatment. The outer base region 230 and the intrinsic base region 220 may be the sidewall spacers 240.
It is electrically connected below and is integrally formed. Through the heat treatment process, the bipolar transistor Tr is substantially completed.

Next, as shown in FIG. 7, an interlayer insulating film 270 is formed on the entire surface of the substrate including the elements of the bipolar transistor Tr and the MOSFETs Qn and Qp. Interlayer insulating film 270 is, for example, a silicon oxide film, BPSG (B oron- P h
osphorus- S ilicate G lass) 2 are sequentially laminated each of the film
It is composed of layers. Further, the lower silicon oxide film is a CV whose source gas is silane gas and nitric oxide gas.
Deposit by method D. The lower silicon oxide film is the upper BP
In order to prevent impurities (each of P and B) from leaking from the SG film, the film is formed to have a film thickness of, for example, about 100 nm. The upper BPSG film is deposited by, for example, the CVD method. The upper BPSG film is formed with a film thickness of, for example, about 300 to 500 [nm]. The BPSG film is subjected to a densification process and a reflow process in a nitrogen gas atmosphere at a temperature of about 900 to 1000 [° C.]. By this reflow, the surface of the upper BPSG film forming the interlayer insulating film 270 is flattened.

Next, the interlayer insulating films 270 and 210 are formed by using ordinary photolithography and etching techniques.
Of the connection holes OP3 reaching the collector extraction region 110 of the bipolar transistor Tr3, and the connection holes OP2, OP1 reaching the emitter extraction electrode 250 and the base extraction electrode 200 of the bipolar transistor Tr. P-channel MOSFET
Connection hole OP reaching source / drain region 190 of Qp
4, OP5 and connection holes OP6 and OP7 reaching the source / drain regions 180 of the N-channel MOSFET Qn are formed, respectively. After forming the connection holes, the base extraction electrode 200 and the emitter extraction electrode 25 are passed through the connection holes.
0, the collector extraction region 110, and the wiring layer (electrode) 2 connected to each of the source / drain regions 180 and 190
Form 80a-280g. The wiring layers 280a-2
Each of 80 g is formed by patterning a tungsten layer deposited by, for example, a CVD method by a normal photolithography and etching technique. Although not shown in FIG. 7, the wiring layer is formed of the interlayer insulating film 2
P-channel MOSFET Qp and N-channel MOS are provided through connection holes OP8 and OP9 provided in 70 and 210.
It is also connected to the gate electrodes 130a and 130b of the FET Qn. Then, although not shown, the wiring layer (electrode) 28
An insulating film such as a silicon oxide film is formed on the entire surface of the substrate including 0a to 280g, and a second layer wiring (for example, an aluminum alloy wiring) is further formed by ordinary photolithography and etching techniques. , Electrically connecting the respective semiconductor elements. By performing the above steps, the Bi-CMOS having the SOI structure of the present invention is almost completed. (Embodiment 4) FIG. 10 shows S which is Embodiment 4 of the present invention.
FIG. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit device having an OI structure. The figure shows an example in which a CMOS transistor is formed on the SOI substrate 11a.

The SOI substrate 11a includes the semiconductor supporting substrate 10 made of single crystal silicon and the semiconductor supporting substrate 1
0, a polycrystalline silicon layer 40 serving as a gettering layer, a silicon oxide film 30 serving as a buried insulating film further provided thereon, and an element formation region provided on the silicon oxide film 30. Single crystal silicon layer 20a
It consists of and.

The feature of the fourth embodiment is that the polycrystalline silicon layer 40 serving as the gettering layer is located below the silicon oxide layer 30 serving as the insulating layer (in other words, on the semiconductor supporting substrate 10 side).
Is to be provided. Upper single crystal silicon layer 20a
Of the p-channel MOSFET Qp and the n-channel MOSFET Qn forming a CMOS transistor are provided on the main surface of the gate electrode via the gate insulating films 310a and 310b made of a silicon oxide film. Source / drain regions 320 and 330 of the p-channel MOSFET Qp and the n-channel MOSFET Qn are formed on the main surface of the upper single crystal silicon layer 20a at both ends of the p-channel MOSFET Qp and the n-channel MOSFET Qn, respectively. Also, the p-channel MOSFETs Qp and n
The bottom surface of each of the channel MOSFETs Qn is S
The field insulating film 290 reaching the silicon oxide film 30 of the OI substrate 11a is isolated.

The thickness of the polycrystalline silicon film 40 is preferably about several thousand angstroms to several μm as in the second embodiment. Here, the point to be noted is that the silicon oxide film 30 is used.
Is sufficiently thin so that the heavy metal element that has entered the upper single-crystal silicon layer 20a, which is the element formation region, diffuses in the buried oxide film 30 and reaches the polycrystalline silicon layer 40. There is a need. The present inventor has studied in detail the diffusion coefficient of typical impurity atoms in bulk Si and silicon oxide. The results are shown in Tables 1 and 2. Table 1 shows the diffusion coefficient of each impurity atom at 1000 ° C., and Table 2 shows the diffusion coefficient of each impurity atom at 900 ° C. As is apparent from Tables 1 and 2, the diffusion coefficient of silicon oxide of each impurity atom is much slower than that in Si. This means that when the film thickness of silicon oxide is large, each impurity atom cannot reach the polycrystalline silicon that is the gettering layer. In particular, Fe,
This tendency is remarkable in heavy metal atoms such as Cu. In consideration of the above-mentioned examination result, in the third embodiment, the film thickness of the silicon oxide film 30 is approximately 1 μm or less, more preferably 0 or less, which is permeable to heavy metal atoms such as Fe and Cu, which are sources of heavy metal contamination. It was set to 0.5 μm or less. The diffusion coefficient of Cu in SiO ₂ in Tables 1 and 2 is the value at 450 ° C. (Notes 1 and 2).
As described above, the gettering layer can be provided on the supporting substrate side by forming the insulating layer of the semiconductor integrated circuit substrate having an SOI structure thin to a predetermined thickness.

[0086]

[Table 1]

[0087]

[Table 2]

Next, a method of manufacturing the CMOS transistor will be briefly described. The steps of forming the SOI substrate 11a are the same up to the bonding of the wafers (substrates) shown in the second embodiment, but the surface to be ground or polished to reduce the thickness of the wafer on the side where the element is formed. However, it differs from the second embodiment in that the wafer on the buried oxide film 30 side is shaved. By the grinding and polishing of the above wafer, 0.5 to 0.1
A silicon thin film layer 20a having a thickness of about μm is formed. afterwards,
A field oxide film 290 is formed on the main surface of the silicon thin film layer 20a by a normal LOCOS method. Then, as in the third embodiment, the gate oxide films 310a of the p-channel MOSFET Qp and the n-channel MOSFET Qn,
310b and gate electrodes 300a and 300b are formed, respectively. Then, an n-type impurity and a p-type impurity are selectively introduced into a predetermined region of the main surface of the silicon thin film layer 20a,
n-channel MOSFET Qn and p-channel MOSFE
Source / drain regions 330 and 320 of TQp are formed, respectively. In addition, reference numerals 340 and 350 denote an n-type well region and a p-type well region, respectively.
Each of 50 can be formed by the same method as in the third embodiment.

In the case of forming a semiconductor element such as MOSFET on the SOI substrate 11a, in the third embodiment, the depletion layer of the PN junction of the semiconductor element is the polycrystalline silicon film 40.
It was necessary to increase the concentration of the buried layers 50a and 50b to some extent in order to prevent the occurrence of junction leak when the temperature reaches 10 .mu.m. However, in the fourth embodiment, immediately below the single crystal silicon layer 20a for forming a semiconductor element, Since the oxide film 30 is used, such consideration is unnecessary. Therefore, it is suitable for realizing a thin film SOI structure as shown in FIG.

Of course, there is no problem in forming other devices such as the bipolar device shown in the third embodiment.
The material of the support substrate 10 is not limited to single crystal silicon, but in consideration of the high temperature heat treatment applied to the SOI substrate 11a at the device manufacturing stage, the semiconductor thin film 20a is not considered.
The same single crystal silicon is desirable. The reason is that when different materials such as polycrystalline silicon are used as the material of the support substrate 10, stress is generated in the SOI substrate 11a due to the difference in thermal expansion coefficient between them, and the semiconductor thin film 20a is distorted. Because there is a fear of.

(Embodiment 5) FIG. 11 is a sectional view showing the principal part of a semiconductor integrated circuit device having an SOI structure according to a fifth embodiment of the present invention. The figure shows an example in which a CMOS transistor is formed on the SOI substrate 12a.

The SOI substrate 12a is a semiconductor support substrate 1 made of single crystal silicon provided with a high concentration defect layer.
0 ', a silicon oxide film 30 serving as a buried insulating film provided thereon, and a single crystal silicon layer 20a serving as an element formation region provided on the silicon oxide film 30. A CMOS transistor similar to that of the above-described fourth embodiment is formed on the main surface of the single crystal silicon layer 20a.

The feature of the fifth embodiment is that instead of the polycrystalline silicon layer 40 serving as the gettering layer of the fourth embodiment,
This is because the semiconductor supporting substrate 10 ′ made of single crystal silicon provided with the high-concentration defect layer was used. An IG (Intrins-ic gettering: hereinafter, I
A crystal internal defect to be a layer) is formed,
The crystal defects extend to the surface of the semiconductor supporting substrate 10 ′, that is, the interface with the embedded insulating film 30.

In the conventional IG technique using a normal wafer, for example, when the initial oxygen concentration of the wafer is low, defects formed inside the crystal are few and a sufficient IG effect cannot be obtained, and when the initial oxygen concentration is too high, the wafer surface ( There is a problem in that a sufficient defect-free layer is not formed in the element formation region) and defects extend to the surface layer and cross the PN junction of the active element to cause junction leakage, which in turn reduces the yield. It was difficult to determine the oxygen concentration in the crystal and the heat treatment conditions. In particular, in the case of medium oxygen concentration, which is a practical region for performing IG, there is a problem that the amount of oxygen precipitation, that is, the amount of internal defects varies greatly even if the same heat treatment is performed. On the other hand, in the case of the fifth embodiment, even if the internal defect in the supporting substrate 10 ′ grows to the wafer surface, the embedded oxide film 30 exists, so that the defect grows further and becomes the element active region. It does not reach the upper silicon film 20a and cross the junction of the device. Therefore, it is possible to select the oxygen concentration and the heat treatment conditions in which the internal defects grow sufficiently.

The film thickness of the silicon oxide film 30 is the same as that of the fourth embodiment for the same purpose. The device formed in the upper silicon layer 20a, which is the element formation region, can be arbitrarily selected as in the fourth embodiment.

Next, an example of a method of manufacturing the SOI substrate 12a will be described. First, a single crystal silicon wafer serving as a semiconductor supporting substrate is used having a high oxygen concentration, and further heat treatment is performed at 700 ° C. to 800 ° C. for several hours to form precipitation nuclei of internal defects. Next, this wafer is thermally oxidized to form a buried oxide film 30.
To form. Internal defects can be formed from the precipitation nuclei previously formed during this thermal oxidation. Next, this wafer is bonded to a single crystal silicon wafer that will be an element active layer, and then heat treatment is performed at, for example, 1100 ° C. for about 1 hour to improve the bonding strength. If this heat treatment is performed in an oxidizing atmosphere, the internal defects described above will further grow and sufficient defects can be obtained in the IG. After that, the manufacturing method is the same as that of the fourth embodiment, and the single crystal silicon wafer on the element formation region side is thinned to a desired thickness to form an element.

In this embodiment, in order to simplify the process as much as possible, the heat treatment for forming the buried oxide film 30, the heat treatment for improving the bonding strength, and the heat treatment for growing the internal defects are used together. Alternatively, the heat treatment for IG may be performed after the SOI wafer is formed by a normal method, for example.

[0098]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a semiconductor thin film is formed on the insulating film,
The so-called S in which the element formation region is near the upper surface
In the semiconductor integrated circuit substrate having the OI structure, the element formation region and the gettering layer are formed close to each other, so that the heavy metal invading the element active region during the manufacture of the semiconductor device easily diffuses in the semiconductor thin film. The gettering layer is reached and gettered. Therefore, it is possible to improve the electrical reliability and the manufacturing yield of the semiconductor device formed using the semiconductor integrated circuit substrate having the SOI structure.

This gettering layer is formed on the upper surface of the buried oxide film,
That is, when formed using polycrystalline silicon or the like immediately below a semiconductor thin film having an element active region, a heavy metal atom is particularly easy because only a very thin semiconductor thin film exists between the element active region and the gettering layer. It is possible to reach the gettering layer and perform gettering.

Further, if the semiconductor thin film and the gettering layer are dielectrically separated from each other by isolation using a groove reaching the buried oxide film, the junction formed in the gettering layer can be activated without leakage. The elements can be separated.

When the gettering layer is formed immediately below the buried oxide film, that is, above the supporting substrate, the buried oxide film hinders the diffusion of heavy metal atoms to some extent, but the thickness of the buried oxide film is large. By setting to a predetermined numerical value, a gettering effect can be sufficiently obtained. In addition, since the gettering layer exists just below the buried oxide film, it is relatively easy compared to the case where the gettering layer is provided only on the back surface of the wafer or near the center of the inside of the wafer like the conventional EG method and IG method. The effect can be enhanced by reaching the gettering layer.

As a method of forming a gettering layer directly under the buried oxide film, there is a method of using a polycrystalline silicon layer as the gettering layer, a method of using internal defects extending to the surface of the supporting substrate, and the like. Also in this case, the element formed in the element active region has an advantage that any element can be formed without considering the gettering layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit substrate having an SOI structure according to a first embodiment of the present invention.

FIG. 2A is a sectional view of a key portion showing the method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 1 in step order.

2 (B) is a sectional view of a key portion showing the method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 1 in the order of steps.

2 (C) is a sectional view of a key portion showing the method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 1 in the order of steps.

2D is a sectional view of a key portion showing the method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 1 in the order of steps.

FIG. 3 is a cross-sectional view of a main part of a semiconductor integrated circuit substrate having an SOI structure according to a second embodiment of the present invention.

4A is a sectional view of a key portion showing the first method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 3, in step order.

4B is a sectional view of a key portion showing the first manufacturing method of the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 3 in step order.

5A is a sectional view of a key portion showing the second manufacturing method of the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 3 in step order.

5 (b) is a sectional view of a key portion showing the second manufacturing method of the substrate for semiconductor integrated circuit having the SOI structure shown in FIG. 3 in the order of steps.

6A is a sectional view of a key portion showing the third method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 3, in process order.

6 (b) is a sectional view of a key portion showing the third method of manufacturing the substrate for a semiconductor integrated circuit having the SOI structure shown in FIG. 3 in the order of steps.

FIG. 7 is a sectional view of an essential part of a semiconductor integrated circuit device having an SOI structure, which is Embodiment 3 of the present invention.

FIG. 8 is an SOI which is Embodiment 3 of the present invention corresponding to FIG.
FIG. 3 is a plan view of a main part of a semiconductor integrated circuit device having a structure.

9A is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (b) is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (c) is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (d) is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9E is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (f) is a sectional view of a key portion showing the manufacturing method of the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (g) is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

9 (h) is a sectional view of a key portion showing the method of manufacturing the semiconductor integrated circuit device having the SOI structure shown in FIGS. 7 and 8 in the order of steps.

FIG. 10 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having an SOI structure, which is Embodiment 4 of the present invention.

FIG. 11 is a cross-sectional view of essential parts of a semiconductor integrated circuit device having an SOI structure, which is Embodiment 5 of the present invention.

[Explanation of symbols]

1, 10, 10 '... Lower-layer silicon single crystal wafer serving as a semiconductor support substrate, 2, 30 ... Buried insulating film (silicon oxide film), 3a, 40 ... Gettering layer, 3, 20, 20a
... Upper layer silicon single crystal serving as an element forming layer, 3c, 10a
... SOI substrate, 50a ... High-concentration N + buried layer, 50b ... High-concentration P + buried layer, 60 ... Epitaxial layer, 60a ... N
Type well region, 60b ... P type well region, 70, 290
... field insulating film, 80 ... element isolation trench, 90 ... silicon oxide film, 100 ... polycrystalline silicon (embedding material), 11
0 ... N + collector extraction layer, 120a, 120b ... Gate oxide film, 130a, 130b ... Gate electrode, 140a,
140b ... Silicon oxide film, 150 ... Low concentration N-type semiconductor region, 160 ... Low concentration P-type semiconductor region, 170, 240
... Sidewall spacer, 180 ... High-concentration N-type semiconductor region, 190 ... High-concentration P-type semiconductor region, 200 ... Base extraction layer, 210, 270 ... Interlayer insulating film, 220 ... Authentic base region, 230 ... External base region, 250 ... Emitter extraction layer, 260 ... Emitter region, 280a ... Base electrode, 280b ... Emitter electrode, 280c ... Collector electrode, 280d, 280e ... Source / drain electrode, 28
0f, 280g ... Source / drain electrodes, NPN ... Bipolar transistor forming region, PMOS ... P channel M
OSFET formation region, NMOS ... n-channel MOSFE
T formation region, Qp ... p channel MOSFET, Qn ... n
Channel MOSFETs, Tr ... Bipolar transistors, OP1 to OP9 ... Through holes.

Claims (20)

[Claims] 1. A semiconductor integrated circuit having a semiconductor supporting substrate, an insulating layer provided on the semiconductor supporting substrate, and a semiconductor thin film layer provided on the insulating layer and on which a semiconductor element is to be formed. A substrate for a semiconductor integrated circuit, wherein a gettering layer is provided at a bonding interface between the insulating layer and the semiconductor thin film layer. 2. The substrate for a semiconductor integrated circuit according to claim 1, wherein the gettering layer is a polycrystalline silicon layer. 3. The substrate for a semiconductor integrated circuit according to claim 1, wherein the gettering layer substantially traps heavy metal atoms present in the semiconductor thin film layer. 4. A semiconductor having a single crystal silicon support substrate, an insulating layer provided on the support substrate, and a single crystal silicon thin film layer provided on the insulating layer and on which a semiconductor element is to be formed. A substrate for a semiconductor integrated circuit, wherein a gettering layer is provided at a bonding interface between the supporting substrate and the insulating layer in the substrate for an integrated circuit. 5. The substrate for a semiconductor integrated circuit according to claim 4, wherein the gettering layer is a polycrystalline silicon layer. 6. The semiconductor integrated circuit substrate according to claim 4, wherein the insulating layer has a thickness of 1 μm or less. 7. The gettering layer substantially traps heavy metal atoms present in the single crystal silicon thin film layer through the insulating layer.
A substrate for a semiconductor integrated circuit according to the item. 8. A semiconductor having a single crystal silicon support substrate, an insulating layer provided on the support substrate, and a single crystal silicon thin film layer provided on the insulating layer and on which a semiconductor element is to be formed. In the substrate for integrated circuit, a gettering layer made of a high-concentration defect layer is provided over almost the entire area of the support substrate, and the thickness of the insulating layer is 1 μm or less. 9. The gettering layer substantially traps heavy metal atoms present in the single crystal silicon thin film layer through the insulating layer.
A substrate for a semiconductor integrated circuit according to the item. 10. A semiconductor integrated circuit substrate according to claim 1, and a semiconductor element having a PN junction provided on the main surface of said semiconductor thin film layer, wherein the PN junction of said semiconductor element is said A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is provided with a gap from the gettering layer. 11. A semiconductor integrated circuit, comprising: the semiconductor integrated circuit substrate according to claim 4; and a semiconductor element having a PN junction provided on a main surface of the single crystal silicon thin film layer. Circuit device. 12. A semiconductor integrated circuit comprising: the semiconductor integrated circuit substrate according to claim 8; and a semiconductor element having a PN junction provided on the main surface of the single crystal silicon thin film layer. Circuit device. 13. A semiconductor supporting substrate, an insulating layer provided on the semiconductor supporting substrate, a semiconductor thin film layer provided on the insulating layer, and a PN junction provided on a main surface of the semiconductor thin film layer. A plurality of semiconductor elements, a gettering layer provided at a bonding interface between the insulating layer and the semiconductor thin film layer, and a semiconductor layer provided on the main surface of the semiconductor thin film layer and separating the plurality of semiconductor elements from each other. Has a separation groove,
The semiconductor integrated circuit device, wherein the isolation groove extends from the surface of the semiconductor thin film layer toward the semiconductor supporting substrate and reaches the insulating layer through the gettering layer. 14. The semiconductor integrated circuit device according to claim 13, wherein the gettering layer is a polycrystalline silicon layer. 15. The semiconductor integrated circuit device according to claim 14, wherein the gettering layer substantially traps heavy metal atoms present in the semiconductor thin film layer. 16. The semiconductor integrated circuit device according to claim 13, wherein the surface of the isolation trench is covered with an insulating film. 17. A semiconductor integrated circuit device, wherein each of the PN junctions of the plurality of semiconductor elements is provided at a distance from the gettering layer. 18. A second semiconductor having a first semiconductor substrate having a substantially flat first main surface and a second main surface facing it, and a second semiconductor having a substantially flat third main surface and a fourth main surface facing it. A step of preparing a substrate, a step of forming an insulating layer on the first main surface of the first semiconductor substrate, and a getter having a substantially uniform thickness on the third main surface of the second semiconductor substrate. A substrate for a semiconductor integrated circuit, comprising: a step of forming a ring layer; and a step of joining the first main surface of the first semiconductor substrate and the third main surface of the second semiconductor substrate. Manufacturing method. 19. The step of forming the gettering layer comprises:
19. The method for manufacturing a semiconductor integrated circuit substrate according to claim 18, further comprising the step of forming a polycrystalline silicon layer having a substantially uniform thickness on the third main surface of the second semiconductor substrate. Method. 20. A step of preparing a semiconductor integrated circuit substrate formed by the manufacturing method according to claim 18, and the fourth main surface side to the third main surface side of the second semiconductor substrate. Forming a semiconductor thin film layer having a predetermined thickness by etching the second semiconductor substrate to a predetermined thickness toward the surface, and forming a PN on the main surface of the semiconductor thin film layer.
And a step of forming a semiconductor element having a junction, the method for manufacturing a semiconductor integrated circuit device.