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JPH0661233A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0661233A
JPH0661233A JP4210382A JP21038292A JPH0661233A JP H0661233 A JPH0661233 A JP H0661233A JP 4210382 A JP4210382 A JP 4210382A JP 21038292 A JP21038292 A JP 21038292A JP H0661233 A JPH0661233 A JP H0661233A
Authority
JP
Japan
Prior art keywords
bump electrode
bump
electrode
width
photosensitive polyimide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP4210382A
Other languages
Japanese (ja)
Inventor
Tomiyasu Saito
富康 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4210382A priority Critical patent/JPH0661233A/en
Publication of JPH0661233A publication Critical patent/JPH0661233A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/1147Manufacturing methods using a lift-off mask
    • H01L2224/11474Multilayer masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902Multiple masking steps
    • H01L2224/11903Multiple masking steps using different masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H01L2224/11902Multiple masking steps
    • H01L2224/11906Multiple masking steps with modification of the same mask
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/119Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11912Methods of manufacturing bump connectors involving a specific sequence of method steps the bump being used as a mask for patterning other parts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】 (修正有) 【目的】 バンプ電極間のリークを生じないようにする
ことができ、しかもバンプ電極とILB電極のコンタク
ト不良を生じさせることなく確実にコンタクトすること
ができる半導体装置の製造方法を提供する。 【構成】 第2のマスクパターン9をマスクとし、第1
のバンプ電極7を鍍金電極とし、鍍金により第2の開口
部9a内を埋め込むように第1のバンプ電極7上に第1
のバンプ電極7幅よりも小さい幅の第2のバンプ電極10
を形成し、第1、第2のマスクパターン8,9を除去
し、全面に感光性ポリイミド11を形成した後、露光・現
像により第1のバンプ電極7間を埋め込み、かつ第2の
バンプ電極10間の該第1のバンプ電極7上に残るように
感光性ポリミイド11をパターニングし、次いで、感光性
ポリイミド11を熱処理することにより、第1のバンプ電
極7上面と第2のバンプ電極10上面間に感光性ポリイミ
ド11上面がくるように熱収縮させる。
(57) [Summary] (Modified) [Purpose] A semiconductor that can prevent leakage between bump electrodes and can surely make contact without causing defective contact between the bump electrode and the ILB electrode. A method for manufacturing a device is provided. [Structure] Using the second mask pattern 9 as a mask, the first
Of the first bump electrode 7 as a plating electrode, and the first bump electrode 7 is filled with the first bump electrode 7 so as to fill the second opening 9a.
The second bump electrode 10 having a width smaller than the width of the bump electrode 7 of
Is formed, the first and second mask patterns 8 and 9 are removed, and a photosensitive polyimide 11 is formed on the entire surface. Then, the first bump electrodes 7 are filled by exposure and development, and the second bump electrodes are formed. By patterning the photosensitive polyimide 11 so as to remain on the first bump electrode 7 between 10 and then heat treating the photosensitive polyimide 11, the upper surface of the first bump electrode 7 and the upper surface of the second bump electrode 10 are patterned. Heat shrink so that the upper surface of the photosensitive polyimide 11 lies between them.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置の製造方法
に係り、詳しくは、ダイシング工程とボンディング工程
を有する半導体装置の製造方法に適用することができ、
特に、バンプ電極間のリークを生じないようにすること
ができ、しかもバンプ電極とILB(Inner Lead Bondi
ng) 電極のコンタクト不良を生じさせることなく確実に
コンタクトすることができる半導体装置の製造方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it can be applied to a method of manufacturing a semiconductor device having a dicing step and a bonding step.
In particular, it is possible to prevent the leakage between the bump electrodes and to prevent the bump electrodes and the ILB (Inner Lead Bondi
ng) The present invention relates to a method for manufacturing a semiconductor device capable of surely making contact without causing electrode contact failure.

【0002】近年、半導体装置の製造方法においては、
素子微細化に伴い、微細加工されたウェーハを個々のチ
ップ毎に分割するダイシング工程と、チップ容器にチッ
プを固定し、容器のリード線端子とチップのバンプ電極
とを細線で接続するボンディング工程とが利用されてい
る。
In recent years, in the method of manufacturing a semiconductor device,
With the miniaturization of elements, a dicing step of dividing a microfabricated wafer into individual chips, and a bonding step of fixing the chips to a chip container and connecting the lead terminals of the container to the bump electrodes of the chips with a fine wire. Is used.

【0003】[0003]

【従来の技術】図5は従来の半導体装置の製造方法を説
明する図である。図5において、31はSi等の基板であ
り、32は基板31上に形成されたSiO2 等の絶縁膜であ
り、33は絶縁膜32上に形成されたAl等の配線層パター
ンである。次いで、34は配線層パターン33が露出された
開口部34aを有する絶縁膜であり、35〜37は開口部34a
内の配線層パターン33とコンタクトするように順次形成
された各々Ti膜、Pd膜、Au等のバンプ電極であ
る。そして、38はPd膜36が露出された開口部38aを有
するバンプ電極37形成用のレジストマスクであり、39は
接着剤39aと基材39bからなる接着テープである。な
お、Ti膜35は上層のバンプ電極37のAuと下層の配線
層パターン33のAlが拡散して反応するのを防止するバ
リア膜として形成しており、Pd膜36はAu鍍金してバ
ンプ電極37を形成する際の鍍金電極として形成してい
る。
2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional method of manufacturing a semiconductor device. In FIG. 5, 31 is a substrate such as Si, 32 is an insulating film such as SiO 2 formed on the substrate 31, and 33 is a wiring layer pattern such as Al formed on the insulating film 32. Next, 34 is an insulating film having an opening 34a in which the wiring layer pattern 33 is exposed, and 35 to 37 are openings 34a.
These are bump electrodes made of Ti film, Pd film, Au, etc., which are sequentially formed so as to make contact with the wiring layer pattern 33 therein. Further, 38 is a resist mask for forming the bump electrode 37 having an opening 38a where the Pd film 36 is exposed, and 39 is an adhesive tape composed of an adhesive 39a and a base material 39b. The Ti film 35 is formed as a barrier film for preventing Au of the upper bump electrode 37 and Al of the lower wiring layer pattern 33 from diffusing and reacting, and the Pd film 36 is plated with Au to form the bump electrode. It is formed as a plating electrode when forming 37.

【0004】次に、その半導体装置の製造方法について
説明する。まず、図5(a)に示すように、CVD法等
によりSi基板31上にSiO2 絶縁膜32を形成し、スパ
ッタ法等により絶縁膜32上にAlを堆積してAl膜を形
成した後、RIE等によりAl膜をエッチングして配線
層パターン33を形成する。次いで、CVD法等により全
面にSiO2 を堆積して絶縁膜34を形成し、RIE等に
より絶縁膜34をエッチングして配線層パターン33が露出
された開口部34aを形成した後、スパッタ法により開口
部34a内の配線層33とコンタクトを取るようにTi膜35
及びPd膜36を形成する。次いで、フォトリソグラフィ
ープロセスでバンプ電極に対応する領域以外の領域が残
るようにレジストパターニングを行ってPd膜36が露出
された開口部38aを有するレジストマスク38を形成した
後、このレジストマスク38を用い、Pd膜36を鍍金電極
とし、開口部38a内のPd膜36上にAu鍍金によりAu
バンプ電極37を形成する。
Next, a method of manufacturing the semiconductor device will be described. First, as shown in FIG. 5A, an SiO 2 insulating film 32 is formed on a Si substrate 31 by a CVD method or the like, and Al is deposited on the insulating film 32 by a sputtering method or the like to form an Al film. The Al film is etched by RIE or the like to form the wiring layer pattern 33. Next, SiO 2 is deposited on the entire surface by a CVD method or the like to form an insulating film 34, and the insulating film 34 is etched by RIE or the like to form an opening 34a in which the wiring layer pattern 33 is exposed. The Ti film 35 is formed so as to make contact with the wiring layer 33 in the opening 34a.
And a Pd film 36 is formed. Next, resist patterning is performed by a photolithography process so that a region other than the region corresponding to the bump electrode remains to form a resist mask 38 having an opening 38a in which the Pd film 36 is exposed, and then this resist mask 38 is used. , Pd film 36 is used as a plating electrode, and Au is plated on the Pd film 36 in the opening 38a by Au plating.
The bump electrode 37 is formed.

【0005】次に、図5(b)に示すように、レジスト
マスク38を除去した後、バンプ電極37をマスクとし、バ
ンプ電極37下のみにPd膜36及びTi膜35が残るように
Pd膜36及びTi膜35をエッチングして絶縁膜34を露出
させる。そして、図5(c)に示すように、ダイシング
処理用の接着テープ39をPd膜36上に張り付け、張り付
け状態でダイシング処理してチップ毎に分離した後、バ
ンプ電極37とILB電極40をILB処理してボンディン
グすることにより、図5(d)に示すような半導体装置
を得ることができる。
Next, as shown in FIG. 5B, after removing the resist mask 38, the Pd film 36 and the Ti film 35 are left only under the bump electrode 37 using the bump electrode 37 as a mask. 36 and the Ti film 35 are etched to expose the insulating film 34. Then, as shown in FIG. 5C, an adhesive tape 39 for dicing is attached to the Pd film 36, and the dicing process is performed in the attached state to separate the chips, and then the bump electrode 37 and the ILB electrode 40 are separated from each other by ILB. By processing and bonding, a semiconductor device as shown in FIG. 5D can be obtained.

【0006】しかしながら、この従来の半導体装置の製
造方法では、上記したように接着テープ39をバンプ電極
37上に張り付けた状態でダイシング処理をすると、図5
(d)に示す如く、ダイシング処理時の接着テープ39の
接着剤39の破片がバンプ電極37間の絶縁膜34上に落ちて
付着し易いとともに、この付着された接着剤39aにダイ
シング処理時のSi片等が付着し易い。具体的には、バ
ンプ電極37のオーバーハング形状となった部分に接着剤
39aが残る。このように、絶縁膜34上に付着された接着
テープ39にSi片が付着した状態で、ILB処理等をし
て動作させると、バンプ電極37間でSi片を介してリー
クしてしまうという問題があった。
However, in this conventional semiconductor device manufacturing method, the adhesive tape 39 is used as the bump electrode as described above.
When the dicing process is performed with the product stuck to 37,
As shown in (d), the fragments of the adhesive 39 of the adhesive tape 39 during the dicing process drop onto the insulating film 34 between the bump electrodes 37 and are easily attached to the adhesive 39a. Si pieces and the like tend to adhere. Specifically, an adhesive is applied to the overhanging portion of the bump electrode 37.
39a remains. As described above, when the Si tape is adhered to the adhesive film 39 on the insulating film 34 and the ILB process or the like is performed, the bump electrodes 37 leak through the Si tape. was there.

【0007】このため、従来では、バンプ電極37間に絶
縁膜を埋め込んでしまうことで上記問題を解決してい
る。この絶縁膜にはα線にも強い感光性ポリイミドが用
いられている。この感光性ポリイミドは容易に厚膜で形
成することができる利点を有する塗布法によるものであ
るが、塗布法を用いているのは、CVD法等の堆積法を
用いてSiO2 等を形成する方法では、厚膜(20μm程
度)のバンプ電極37間を埋め込む成長時間に非常に長時
間を要し、実用上好ましくないからである。以下、図面
を用いて具体的に説明する。
Therefore, conventionally, the above problem is solved by embedding an insulating film between the bump electrodes 37. For this insulating film, a photosensitive polyimide that is strong against α rays is used. This photosensitive polyimide is formed by a coating method which has the advantage that it can be easily formed into a thick film. The coating method is used to form SiO 2 or the like by using a deposition method such as a CVD method. This is because the method requires a very long growth time to fill the space between the bump electrodes 37 of thick film (about 20 μm), which is not preferable in practice. Hereinafter, a specific description will be given with reference to the drawings.

【0008】図6は従来の別の半導体装置の製造方法を
説明する図である。図6において、図5と同一符号は同
一または相当部分を示し、41は感光性ポリイミドであ
る。次に、その半導体装置の製造方法について説明す
る。ここでは、絶縁膜32の形成からPd膜36及びTi膜
35のエッチングまでの工程は図5の場合と同様であるの
で省略する。
FIG. 6 is a diagram for explaining another conventional method of manufacturing a semiconductor device. 6, the same reference numerals as those in FIG. 5 indicate the same or corresponding portions, and 41 is a photosensitive polyimide. Next, a method of manufacturing the semiconductor device will be described. Here, from the formation of the insulating film 32 to the Pd film 36 and the Ti film.
The steps up to etching 35 are the same as in FIG.

【0009】まず、図6(a)に示すように、全面に感
光性ポリイミド41を塗布し、図6(b)に示すように、
露光・現像によりバンプ電極37間を完全に埋め込み、か
つバンプ電極37上にまで残るように感光性ポリイミド41
をバターニングする。ここではバンプ電極37間に位置合
わせマスクで正確に位置合わせして感光性ポリイミド41
を形成するのは現状のプロセスでは微細化される程非常
に難しく、位置合わせ余裕を考慮すると、上記の如くど
うしても感光性ポリイミド41上にまで形成しなければな
らない。また、バンプ電極37間に仮に形成できたとして
も、バンプ電極37上面より下部にくるように、あるいは
バンプ電極37上面と合うように形成したのでは、ILB
処理時のリークの問題を解消することができない。これ
からも、感光性ポリイミド41はバンプ電極37上にまで形
成しなければならない。
First, as shown in FIG. 6 (a), photosensitive polyimide 41 is applied to the entire surface, and as shown in FIG. 6 (b),
Photosensitive polyimide 41 so that the space between bump electrodes 37 is completely filled by exposure and development, and remains on bump electrodes 37.
To pattern. In this case, the photosensitive polyimide 41 is accurately aligned with the alignment mask between the bump electrodes 37.
It is very difficult to form the film in the current process as it is miniaturized, and in consideration of the alignment margin, it is necessary to form even on the photosensitive polyimide 41 as described above. Even if the bump electrodes 37 can be formed, if they are formed so as to be below the upper surface of the bump electrode 37 or so as to be aligned with the upper surface of the bump electrode 37, the ILB
The problem of leak at the time of processing cannot be solved. From now on, the photosensitive polyimide 41 must be formed even on the bump electrodes 37.

【0010】次に、図6(c)に示す如く感光性ポリイ
ミド41をキュア処理する。この時、感光性ポリイミド41
は熱収縮し、図に示す中心部が凹部となり、角部が凸部
となる。そして、図6(c)に示すように、ダイシング
処理用の接着テープ39を感光性ポリイミド41上に張り付
け、張り付けた状態でダイシング処理してチップ毎に分
離した後、バンプ電極37とILB電極40をILB処理し
てボンディングすることにより、図6(d)に示すよう
な半導体装置を得ることができる。
Next, the photosensitive polyimide 41 is cured as shown in FIG. 6 (c). At this time, the photosensitive polyimide 41
Heat-shrinks, the central part shown in the figure becomes a concave part, and the corner part becomes a convex part. Then, as shown in FIG. 6 (c), an adhesive tape 39 for dicing is adhered onto the photosensitive polyimide 41, and the dicing process is performed in the adhered state to separate each chip, and then the bump electrode 37 and the ILB electrode 40 are separated. By performing an ILB process and bonding, a semiconductor device as shown in FIG. 6D can be obtained.

【0011】この従来の半導体装置の製造方法では、バ
ンプ電極37間を絶縁性の感光性ポリイミド41で埋め込ん
でいるため、前述したようなバンプ電極37間でのリーク
の問題を解消することができるという利点を有する。
In this conventional method for manufacturing a semiconductor device, since the bump electrodes 37 are filled with the insulating photosensitive polyimide 41, the problem of the leak between the bump electrodes 37 as described above can be solved. Has the advantage.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、上記し
た図6に示す従来の半導体装置の製造方法では、接着テ
ープ39を、バンプ電極37上にまで形成された感光性ポリ
イミド41に張り付けてダイシング処理していたため、接
着剤39aの破片が感光性ポリイミド41間の露出している
バンプ電極37上に付着し易くなり、バンプ電極37上に接
着剤39aの破片が付着した状態でILB処理すると、バ
ンプ電極37とILB電極40のコンタクト不良が生じ易い
という問題があった。このため、感光性ポリイミド41と
バンプ電極37上面よりも低く形成すればよいと考えられ
るが、前述した如く、現状のプロセスでは微細化される
程、バンプ電極37間に正確に感光性ポリイミド41を形成
するのは非常に難しいうえ、仮に形成できたとしても、
バンプ電極37間でのリークの問題が生じてしまう。
However, in the conventional method for manufacturing a semiconductor device shown in FIG. 6 described above, the adhesive tape 39 is attached to the photosensitive polyimide 41 formed even on the bump electrodes 37 and the dicing process is performed. Therefore, the fragments of the adhesive 39a tend to adhere to the exposed bump electrodes 37 between the photosensitive polyimides 41, and if the ILB processing is performed with the fragments of the adhesive 39a adhered on the bump electrodes 37, the bump electrodes 37 There is a problem that a contact failure between 37 and the ILB electrode 40 is likely to occur. For this reason, it is considered that the photosensitive polyimide 41 and the bump electrodes 37 may be formed lower than the upper surfaces thereof. It is very difficult to form, and even if it could be formed,
This causes a problem of leakage between the bump electrodes 37.

【0013】また、感光性ポリイミド41はキュア処理す
ると熱収縮するが中心部が凹部となり、角部が凸部とな
るうえ、その生じ方は雰囲気の影響の受け方で一様でな
い。このため、感光性ポリイミド41間の開口部内に入る
ように幅の小さいILB電極40を用いて仮に設置する
と、どうしても感光性ポリイミド41上面(特に角部の凸
部)がILB電極40上面より出っ張った部分が生じるこ
とになる。そして、ILBはILB電極40部分よりも幅
の広い構成部分を含んでいるため、この幅の広い構成部
分が前述の感光性ポリイミド41の出っ張った部分に当た
ってしまい、その結果、図7に示すように、折角幅の小
さいILB電極40を用いてもILB電極40を感光性ポリ
イミド41間のバンプ電極37上に設置できなくなってしま
うという問題があった。
When the photosensitive polyimide 41 is cured, it undergoes heat shrinkage, but its central portion becomes a concave portion and its corner portions become a convex portion, and the occurrence thereof is not uniform due to the influence of the atmosphere. Therefore, if the ILB electrode 40 having a small width is used so as to enter the openings between the photosensitive polyimides 41, the upper surface of the photosensitive polyimide 41 (especially the convex portion of the corner) is inevitably protruded from the upper surface of the ILB electrode 40. Part will be generated. Since the ILB includes a component portion wider than the ILB electrode 40 portion, this wider component portion hits the protruding portion of the photosensitive polyimide 41, and as a result, as shown in FIG. However, there is a problem in that the ILB electrode 40 cannot be placed on the bump electrode 37 between the photosensitive polyimides 41 even if the ILB electrode 40 having a small bending width is used.

【0014】このため、感光性ポリイミド41上面がバン
プ電極37上にこないようにバンプ電極37上面より下にす
るようにすればよいと考えられるが、前述の如く問題が
生じてしまう。そこで本発明は、バンプ電極間のリーク
を生じないようにすることができ、しかもバンプ電極と
ILB電極のコンタクト不良を生じさせることなく確実
にコンタクトすることができる半導体装置の製造方法を
提供することを目的としている。
Therefore, it is conceivable that the upper surface of the photosensitive polyimide 41 should be below the upper surface of the bump electrode 37 so that the upper surface of the photosensitive polyimide 41 does not come onto the bump electrode 37. However, the problem occurs as described above. Therefore, the present invention provides a method for manufacturing a semiconductor device which can prevent leakage between bump electrodes and can surely make contact without causing contact failure between the bump electrode and the ILB electrode. It is an object.

【0015】[0015]

【課題を解決するための手段】本発明による半導体装置
の製造方法は上記目的達成のため、下地の膜上に導電性
領域と絶縁性領域を形成する工程と、次いで、該絶縁性
領域上のバンプ電極が形成される領域以外の領域に該導
電性領域が露出された第1の開口部を有する第1のマス
クパターンを形成する工程と、次いで、該第1のマスク
パターンをマスクとし、該導電性領域を鍍金電極とし、
鍍金により該第1の開口部内を埋め込むように該導電性
領域上に第1のバンプ電極を形成する工程と、次いで、
該第1のマスクパターン上から該第1のバンプ電極上に
かけて該第1のマスクパターン幅よりも広い幅で、かつ
該第1のバンプ電極が露出された第2の開口部を有する
第2のマスクパターンを形成する工程と、次いで、該第
2のマスクパターンをマスクとし、該第1のバンプ電極
を鍍金電極とし、鍍金により該第2の開口部内を埋め込
むように該第1のバンプ電極上に該第1のバンプ電極幅
よりも小さい幅の第2のバンプ電極を形成する工程と、
次いで、該第1、第2のマスクパターンを除去する工程
と、次いで、全面に感光性ポリイミドを形成する工程
と、次いで、露光・現像により該第1のバンプ電極間を
埋め込み、かつ該第2のバンプ電極間の該第2のバンプ
電極上に残るように該感光性ポリミイドをパターニング
する工程と、次いで、該感光性ポリイミドを熱処理する
ことにより、該第1のバンプ電極上面と該第2のバンプ
電極上面間に該感光性ポリイミド上面がくるように熱収
縮させる工程とを含むものである。
In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming a conductive region and an insulating region on a base film, and then a step of forming the conductive region on the insulating region. Forming a first mask pattern having a first opening in which the conductive region is exposed in a region other than the region where the bump electrode is formed, and then using the first mask pattern as a mask, The conductive area is used as a plating electrode,
A step of forming a first bump electrode on the conductive region by plating so as to fill the inside of the first opening, and then,
A second opening having a width wider than the first mask pattern width from above the first mask pattern to above the first bump electrode and having a second opening through which the first bump electrode is exposed. A step of forming a mask pattern, and then, using the second mask pattern as a mask, the first bump electrode as a plating electrode, and plating the second bump pattern on the first bump electrode so as to fill the inside of the second opening. A step of forming a second bump electrode having a width smaller than the first bump electrode width,
Next, a step of removing the first and second mask patterns, a step of forming a photosensitive polyimide on the entire surface, and a step of filling the space between the first bump electrodes by exposure and development and a step of forming the second bump electrode. Patterning the photosensitive polyimide so that it remains on the second bump electrodes between the bump electrodes, and then heat-treating the photosensitive polyimide to form an upper surface of the first bump electrodes and the second bump electrodes. And heat shrinking so that the upper surface of the photosensitive polyimide lies between the upper surfaces of the bump electrodes.

【0016】本発明による半導体装置の製造方法は上記
目的達成のため、下地の膜上に導電性領域と絶縁性領域
を形成する工程と、次いで、全面に第1の感光性有機膜
と該第1の感光性有機膜と光感度の異なる第2の感光性
有機膜を順次形成する工程と、次いで、露光・現像によ
り、該絶縁性領域上のバンプ電極が形成される領域以外
の領域に第1の感光性有機膜パターン及び該第1の感光
性有機膜パターン幅よりも小さい幅の第2の感光性有機
膜パターンを形成するとともに、該第1の感光性有機膜
パターン間に該導電性領域が露出される第1の開口部及
び該第2の感光性有機膜パターン間に第1の開口部幅よ
りも小さい幅の第2の開口部を形成する工程と、次い
で、該第1,第2の感光性有機膜パターンをマスクと
し、該導電性領域を鍍金電極とし、鍍金により該第1,
第2の開口部内を埋め込むように該導電性領域上に上部
が下部よりも幅の小さいバンプ電極を形成する工程と、
次いで、該第1,第2の感光性有機膜パターンを除去す
る工程と、次いで、全面に感光性ポリイミドを形成する
工程と、次いで、露光・現像により該バンプ電極幅の大
きい下部間を埋め込み、かつ該バンプ電極幅の小さい上
部間に残るように該感光性ポリイミドをパターニングす
る工程と、次いで、該感光性ポリイミドを熱処理するこ
とにより、該バンプ電極幅の小さい上部上面と該バンプ
電極幅の大きい下部上面間に該感光性ポリイミド上面が
くるように該感光性ポリイミドを熱収縮させる工程とを
含ものである。
In order to achieve the above object, the method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a conductive region and an insulating region on a base film, and then forming a first photosensitive organic film and the first photosensitive organic film on the entire surface. A step of sequentially forming a second photosensitive organic film having a different photosensitivity from that of the first photosensitive organic film, and then exposing and developing the second photosensitive organic film in a region other than a region where the bump electrode is formed on the insulating region. One photosensitive organic film pattern and a second photosensitive organic film pattern having a width smaller than the width of the first photosensitive organic film pattern are formed, and the conductive property is provided between the first photosensitive organic film patterns. A step of forming a second opening having a width smaller than the width of the first opening between the first opening and the second photosensitive organic film pattern where the region is exposed; Using the second photosensitive organic film pattern as a mask, the conductive region is plated. An electrode, first by plating,
Forming a bump electrode having an upper portion having a width smaller than that of the lower portion on the conductive region so as to fill the second opening;
Next, a step of removing the first and second photosensitive organic film patterns, a step of forming a photosensitive polyimide on the entire surface, and a step of filling the space between the lower portions of the bump electrodes having a large width by exposure and development, And, the step of patterning the photosensitive polyimide so that it remains between the upper portions of the small bump electrode width, and then by subjecting the photosensitive polyimide to heat treatment, the upper upper surface of the smaller bump electrode width and the larger upper portion of the bump electrode width. And heat-shrinking the photosensitive polyimide so that the upper surface of the photosensitive polyimide lies between the upper surfaces of the lower portions.

【0017】[0017]

【作用】本発明では、後述する実施例1の図1,2に示
す如く、バンプ電極7上にバンプ電極7幅よりも小さい
幅のバンプ電極10を形成し、全面に塗布された感光性ポ
リイミド11を露光・現像によりバンプ電極7間を埋め込
み、かつバンプ電極10間のバンプ電極7上にまで残るよ
うにパターニングした後、感光性ポリイミド11をキュア
してバンプ電極7上面とバンプ電極10上面間に感光性ポ
リイミド11上面がくるように熱収縮させている。このよ
うに、感光性ポリイミド11上面がバンプ電極10上面より
下側にくるようにしたため、ダイシング処理用接着テー
プ12をバンプ電極10に張り付けてダイシング処理するこ
とができる。なお、ポリイミドがバンプ電極10より上で
あったとしてもダイシング処理用接着テープを張りつけ
てダイシング処理することができる。このため、感光性
ポリイミド11をバンプ電極10上にまで形成して伴う、ダ
イシング処理時に生じるバンプ電極10上への接着テープ
12の破片の付着を生じないようにすることができる。し
かも、ILB電極13幅が感光性ポリイミド11間の幅より
も広くても、感光性ポリイミド11上面がバンプ電極10上
面よりも下側にあるため、バンプ電極10とILB電極13
を確実にコンタクトさせることができる。なお、ここで
バンプ電極10に張り付けた接着テープ12は、UVテープ
であるのでUV照射することにより完全に剥離すること
ができる。
In the present invention, as shown in FIGS. 1 and 2 of Example 1 described later, a bump electrode 10 having a width smaller than the width of the bump electrode 7 is formed on the bump electrode 7, and the photosensitive polyimide applied on the entire surface. After patterning 11 between the bump electrodes 7 by exposure and development and leaving the bump electrodes 10 between the bump electrodes 7, the photosensitive polyimide 11 is cured to allow a space between the bump electrode 7 upper surface and the bump electrode 10 upper surface. It is heat-shrinked so that the upper surface of the photosensitive polyimide 11 comes to the top. Since the upper surface of the photosensitive polyimide 11 is located below the upper surface of the bump electrode 10 in this manner, the dicing processing adhesive tape 12 can be attached to the bump electrode 10 for dicing processing. Even if the polyimide is above the bump electrode 10, the dicing process can be performed by sticking the adhesive tape for dicing process. Therefore, the adhesive tape on the bump electrode 10 generated during the dicing process accompanying the formation of the photosensitive polyimide 11 even on the bump electrode 10.
It is possible to prevent the adhesion of 12 pieces. Moreover, even if the width of the ILB electrode 13 is wider than the width between the photosensitive polyimides 11, since the upper surface of the photosensitive polyimide 11 is lower than the upper surface of the bump electrode 10, the bump electrode 10 and the ILB electrode 13 are
Can be reliably contacted. Since the adhesive tape 12 attached to the bump electrode 10 is a UV tape, it can be completely peeled off by UV irradiation.

【0018】また、バンプ電極ICは膜厚が20μmと厚
膜に容易に形成することができるため、感光性ポリイミ
ド11の塗布厚、熱処理条件等を適宜調整することにより
感光性ポリイミド11上面はバンプ電極10上面とバンプ電
極7上面間にくるように容易に形成することができる。
そして、感光性ポリイミド11はバンプ電極10間で正確に
位置合わせする必要もなく、しかもバンプ電極7間で正
確に位置合わせする必要もない。要はバンプ電極7間を
完全に埋め込み、かつバンプ電極7上にまで残るように
形成すればよいので、バンプ電極7幅より大きく、かつ
バンプ電極10間の幅よりも小さい範囲内で位置合わせ余
裕を考慮して行えばよい。このため、感光性ポリイミド
11はバンプ電極10と離間してバンプ電極7上に形成され
るため、従来問題であったダイシング処理でのバンプ電
極7間でのリークを生じないようにすることができるう
え、感光性ポリイミド11上に接着テープ12の接着剤12a
の破片が付着しても上記の如く感光性ポリイミド11とバ
ンプ電極10は離間しているため、バンプ電極10間でリー
クすることもない。
Since the bump electrode IC can be easily formed as a thick film having a thickness of 20 μm, the upper surface of the photosensitive polyimide 11 is bumped by appropriately adjusting the coating thickness of the photosensitive polyimide 11, heat treatment conditions and the like. It can be easily formed so as to be located between the upper surface of the electrode 10 and the upper surface of the bump electrode 7.
Further, the photosensitive polyimide 11 does not need to be accurately aligned between the bump electrodes 10, and also need not be accurately aligned between the bump electrodes 7. The point is that the gaps between the bump electrodes 7 need to be completely embedded, and the bump electrodes 7 need to be formed so as to remain on the bump electrodes 7. Should be taken into consideration. Therefore, the photosensitive polyimide
Since 11 is formed on the bump electrode 7 so as to be separated from the bump electrode 10, it is possible to prevent the leak between the bump electrodes 7 in the dicing process, which has been a problem in the past, and the photosensitive polyimide 11 Adhesive 12a on top of adhesive tape 12
Even if the debris adheres, the photosensitive polyimide 11 and the bump electrode 10 are separated from each other as described above, so that no leak occurs between the bump electrodes 10.

【0019】[0019]

【実施例】(実施例1)以下、本発明を図面に基づいて
説明する。図1,2は本発明の実施例1に則した半導体
装置の製造方法を説明する図である。図1,2におい
て、1はSi等の基板であり、2は基板1上に形成され
たSiO2 等の絶縁膜であり、3は絶縁膜2上に形成さ
れたAl等の配線層パターンである。次いで、4は配線
層パターン3が露出された開口部4aを有する絶縁膜で
あり、5〜7は開口部4a内の配線層パターン3とコン
タクトするように順次形成された各々Ti膜、Pd膜、
Au等のバンプ電極であり、8はPd膜6が露出された
開口部8aを有するバンプ電極7形成用のレジストマス
クである。次いで、9はレジストマスク8上からバンプ
電極7上にかけてレジストマスク8幅よりも広い幅で、
かつバンプ電極7が露出された開口部9aを有するレジ
ストマスクであり、10はバンプ電極7上に形成されたバ
ンプ電極7幅よりも小さい幅のバンプ電極であり、11は
バンプ電極7間を埋め込み、かつバンプ電極10間のバン
プ電極7上にまで形成され、しかもその上面がバンプ電
極7上面とバンプ電極10上面間にくるように形成された
感光性ポリイミドである。そして、12は接着剤12aと基
材12bからなるダイシング用の接着テープであり、13は
バンプ電極7,10とコンタクトさせるためのILB電極
である。なお、Ti膜5は上面のバンプ電極7,10のA
uと下層の配線層パターン33のAlが拡散して反応する
のを防止するバリア膜として形成しており、Pd膜6は
Au鍍金してバンプ電極7を形成する際の鍍金電極とし
て形成している。
(Embodiment 1) The present invention will be described below with reference to the drawings. 1 and 2 are views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In FIGS. 1 and 2, 1 is a substrate such as Si, 2 is an insulating film such as SiO 2 formed on the substrate 1, and 3 is a wiring layer pattern such as Al formed on the insulating film 2. is there. Next, 4 is an insulating film having an opening 4a in which the wiring layer pattern 3 is exposed, and 5 to 7 are a Ti film and a Pd film, which are sequentially formed so as to contact the wiring layer pattern 3 in the opening 4a. ,
Reference numeral 8 denotes a bump electrode made of Au or the like, and reference numeral 8 denotes a resist mask for forming the bump electrode 7 having an opening 8a where the Pd film 6 is exposed. Next, 9 is a width wider than the resist mask 8 width from above the resist mask 8 to above the bump electrode 7,
The bump electrode 7 is a resist mask having an opening 9a exposed, 10 is a bump electrode having a width smaller than the width of the bump electrode 7 formed on the bump electrode 7, and 11 is embedded between the bump electrodes 7. The photosensitive polyimide is formed between the bump electrodes 10 up to the bump electrodes 7, and the upper surface thereof is located between the upper surfaces of the bump electrodes 7 and the bump electrodes 10. Further, 12 is an adhesive tape for dicing which is composed of the adhesive 12a and the base material 12b, and 13 is an ILB electrode for contacting the bump electrodes 7 and 10. In addition, the Ti film 5 is the A of the bump electrodes 7 and 10 on the upper surface.
It is formed as a barrier film for preventing u and Al of the lower wiring layer pattern 33 from diffusing and reacting, and the Pd film 6 is formed as a plating electrode when the bump electrode 7 is formed by Au plating. There is.

【0020】次に、その半導体装置の製造方法について
説明する。まず、図1(a)に示すように、CVD法等
により基板1上にSiO2 を堆積して膜厚1.0μmの絶
縁膜2を形成し、スパッタ法等により絶縁膜2上にAl
を堆積して膜厚1.5μmのAl膜を形成した後、RIE
等によりAl膜をエッチングして配線層パターン3を形
成する。次いで、CVD法等により全面にSiO2を堆
積して膜厚1.0μmの絶縁膜4を形成し、RIE等によ
り絶縁膜4をエッチングして配線層パターン3が露出さ
れた開口部4aを形成した後、スパッタ法により開口部
4a内の配線層パターン3とコンタクトを取るように膜
厚500ÅのTi膜5及び膜厚500ÅのPd膜6を形成す
る。次いで、全面にレジストを塗布し、露光・現像によ
りバンプ電極が形成される領域以外の領域が残るように
レジストパターニングを行ってPd膜6が露出された開
口部8aを有するレジストマスク8を形成した後、この
レジストマスク8を用い、開口部8a内のPd膜6を鍍
金電極とし、開口部8a内のPd膜6上にAu鍍金によ
り幅50μmで膜厚20μmのAuバンプ電極7を形成す
る。
Next, a method of manufacturing the semiconductor device will be described. First, as shown in FIG. 1A, SiO 2 is deposited on a substrate 1 by a CVD method or the like to form an insulating film 2 having a film thickness of 1.0 μm, and an Al film is formed on the insulating film 2 by a sputtering method or the like.
Is deposited to form an Al film having a thickness of 1.5 μm, and then RIE is performed.
The Al film is etched by the above method to form the wiring layer pattern 3. Next, SiO 2 is deposited on the entire surface by a CVD method or the like to form an insulating film 4 having a film thickness of 1.0 μm, and the insulating film 4 is etched by RIE or the like to form an opening 4a in which the wiring layer pattern 3 is exposed. After that, a Ti film 5 with a film thickness of 500Å and a Pd film 6 with a film thickness of 500Å are formed by sputtering so as to make contact with the wiring layer pattern 3 in the opening 4a. Next, a resist is applied on the entire surface, and resist patterning is performed by exposure and development so that a region other than the region where the bump electrode is formed remains, thereby forming a resist mask 8 having an opening 8a in which the Pd film 6 is exposed. Then, using this resist mask 8, the Pd film 6 in the opening 8a is used as a plating electrode, and an Au bump electrode 7 having a width of 50 μm and a thickness of 20 μm is formed on the Pd film 6 in the opening 8a by Au plating.

【0021】次に、図1(b)に示すように、全面にレ
ジストを塗布し、露光・現像によりレジストパターニン
グを行って、レジストマスク8上からバンプ電極7上に
かけてレジストマスク8幅よりも広い幅で、かつバンプ
電極7が露出された開口部9aを有するレジストマスク
9を形成する。次いで、レジストマスク9をマスクと
し、バンプ電極7を鍍金電極とし、Au鍍金により開口
部9a内を埋め込むようにバンプ電極7上にバンプ電極
7幅よりも小さい幅の、幅40μmで膜厚5μmのAuバ
ンプ電極10を形成する。
Next, as shown in FIG. 1B, a resist is applied to the entire surface, resist patterning is performed by exposure and development, and the width from the resist mask 8 to the bump electrode 7 is wider than the resist mask 8 width. A resist mask 9 having a width and an opening 9a where the bump electrode 7 is exposed is formed. Next, the resist mask 9 is used as a mask, the bump electrode 7 is used as a plating electrode, and the opening 9a is filled with Au plating on the bump electrode 7 so as to have a width smaller than the width of the bump electrode 7 and a thickness of 5 μm. The Au bump electrode 10 is formed.

【0022】次に、図1(c)に示すように、O2 アッ
シング等によりレジストマスク8,9を除去した後、バ
ンプ電極7,10をマスクし、RIE等によりPd膜6及
びTi膜5をエッチングして絶縁膜4を露出させる。こ
の時、バンプ電極7下のみにPd膜6及びTi膜5が残
る。次に、図1(d)に示すように、全面に感光性ポリ
イミド11を塗布した後、図2(e)に示すように、露光
・現像により感光性ポリイミド11をバンプ電極7間を埋
め込み、かつバンプ電極10間のバンプ電極7上に残るよ
うにパターニングする。
Next, as shown in FIG. 1C, after removing the resist masks 8 and 9 by O 2 ashing or the like, the bump electrodes 7 and 10 are masked and the Pd film 6 and the Ti film 5 are formed by RIE or the like. To expose the insulating film 4. At this time, the Pd film 6 and the Ti film 5 remain only under the bump electrode 7. Next, as shown in FIG. 1D, after applying the photosensitive polyimide 11 on the entire surface, as shown in FIG. 2E, the photosensitive polyimide 11 is embedded between the bump electrodes 7 by exposure and development. In addition, patterning is performed so as to remain on the bump electrodes 7 between the bump electrodes 10.

【0023】次に、図2(f)に示すように、感光性ポ
リイミド11を350℃、120分キュアすることにより、バン
プ電極7上面とバンプ電極10上面間に感光性ポリイミド
11上面がくるように熱収縮させる。そして、図2(g)
に示すようにダイシング処理用の接着テープ12をバンプ
電極10上に張り付け、接着テープ12を張り付けた状態で
ダイシング処理してチップ毎に分離した後、バンプ電極
10とILB電極13をILB処理してボンディングするこ
とにより、図2(h)に示すようにな半導体装置を得る
ことができる。
Next, as shown in FIG. 2 (f), the photosensitive polyimide 11 is cured at 350 ° C. for 120 minutes, whereby the photosensitive polyimide 11 is cured between the upper surface of the bump electrode 7 and the upper surface of the bump electrode 10.
11 Heat shrink so that the top surface comes up. And FIG. 2 (g)
Adhesive tape 12 for dicing processing is attached on the bump electrodes 10 as shown in FIG. 1, and after the adhesive tape 12 is attached, dicing processing is performed to separate the chips into bump electrodes.
The semiconductor device as shown in FIG. 2H can be obtained by subjecting the ILB electrode 13 and the ILB electrode 13 to ILB treatment and bonding.

【0024】このように、本実施例では、バンプ電極7
上にバンプ電極7幅よりも小さい幅のバンプ電極10を形
成し、全面に塗布された感光性ポリイミド11を露光・現
像によりバンプ電極7間を埋め込み、かつバンプ電極10
間のバンプ電極7上に残るようにパターニングした後、
感光性ポリイミド11をキュアしてバンプ電極7上面とバ
ンプ電極10上面間に感光性ポリイミド11上面がくるよう
に熱収縮させている。このように、感光性ポリイミド11
上面がバンプ電極10上面より下側にくるようにしたた
め、ダイシング処理用の接着テープ12をバンプ電極10に
張り付けてダイシング処理することができる。このた
め、感光性ポリイミド11をバンプ電極10上にまで形成し
て伴う、ダイシング処理時に生じるバンプ電極10上への
接着剤12aの破片の付着を生じないようにすることがで
きる。しかも、ILB電極13幅が感光性ポリイミド11間
の幅よりも広くても、感光性ポリイミド11上面がバンプ
電極10上面よりも下側にあるため、バンプ電極10とIL
B電極13を確実にコンタクトさせることができる。
As described above, in this embodiment, the bump electrode 7
The bump electrode 10 having a width smaller than the width of the bump electrode 7 is formed on the bump electrode 7, and the photosensitive polyimide 11 applied on the entire surface is exposed and developed to fill the space between the bump electrodes 7 and
After patterning so as to remain on the bump electrodes 7 between
The photosensitive polyimide 11 is cured and heat-shrinked so that the upper surface of the photosensitive polyimide 11 is located between the upper surfaces of the bump electrodes 7 and the bump electrodes 10. In this way, the photosensitive polyimide 11
Since the upper surface is located below the upper surface of the bump electrode 10, the adhesive tape 12 for dicing processing can be attached to the bump electrode 10 for dicing processing. For this reason, it is possible to prevent the debris of the adhesive 12a from adhering to the bump electrodes 10 during the dicing process, which is caused by forming the photosensitive polyimide 11 even on the bump electrodes 10. Moreover, even if the width of the ILB electrode 13 is wider than the width between the photosensitive polyimides 11, since the upper surface of the photosensitive polyimide 11 is lower than the upper surface of the bump electrode 10, the bump electrode 10 and the IL
The B electrode 13 can be surely contacted.

【0025】また、本実施例では、バンプ電極10は膜厚
が5μmと厚膜に容易に形成することができるため、感
光性ポリイミド11の塗布厚、熱処理条件等を適宜調整す
ることにより、感光性ポリイミド11上面はバンプ電極10
上面とバンプ電極7上面間にくるように容易に形成する
ことができる。そして、感光性ポリイミド11はバンプ電
極10間で正確に位置合わせする必要もなく、しかもバン
プ電極7間で正確に位置合わせする必要もない。要はバ
ンプ電極7間を完全に埋め込み、かつバンプ電極7上に
残るように形成すればよいので、バンプ電極7幅より大
きく、かつバンプ電極10間の幅よりも小さい範囲内で位
置合わせ余裕を考慮して行えばよい。このため、感光性
ポリイミド11はバンプ電極10と離間してバンプ電極7上
に形成されるため、従来問題であったダイシング処理で
のバンプ電極7間でのリークを生じないようにすること
ができるうえ、感光性ポリイミド11上に接着テープ12の
接着剤12aの破片が付着しても上記の如く感光性ポリイ
ミド11とバンプ電極10は離間しているため、バンプ電極
10間でリークすることもない。 (実施例2)図3,4は本発明の実施例2に則した半導
体装置の製造方法を説明する図である。図3,4におい
て、15はSi等の基板であり、16は基板15上に形成され
たSiO2 等の絶縁膜であり、17は絶縁膜16上に形成さ
れたAl等の配線層パターンである。次いで、18は配線
層パターン17が露出された開口部18aを有する絶縁膜で
あり、18〜20は絶縁膜18内の配線層パターン17とコンタ
クトするように順次形成された各々Ti膜、Pd膜、A
u等のバンプ電極であり、21は高感度のポジ型の感光性
レジストであり、22は感光性レジスト21上に形成された
感光性レジスト21よりも低感度のポジ型の感光性レジス
トである。次いで、21aは感光性レジスト21がパターニ
ングされ形成されたPd膜20が露出された開口部21bを
有するレジストパターンであり、22aはレジスト22がパ
ターニングされ形成されたレジストパターン21a幅より
も小さい幅の開口部22bを有するレジストパターンであ
り、23は上部が下部よりも幅の小さいバンプ電極であ
る。24はバンプ電極23幅の大きい下部間を埋め込み、か
つバンプ電極23幅の小さい上部間のバンプ電極23幅の大
きい下部上面上にまで形成され、しかもその上面がバン
プ電極23の幅の大きい下部上面とバンプ電極23幅の小さ
い上部上面間にくるように形成された感光性ポリイミド
である。そして、25は接着剤25aと基材25bからなるダ
イシング用の接着テープであり、26はバンプ電極23とコ
ンタクトさせるためのILB電極である。なお、Ti膜
19は上層のバンプ電極23のAuと下層の配線層パターン
17のAlが拡散して反応するのを防止するバリア膜とし
て形成しており、Pd膜20はAu鍍金してバンプ電極23
を形成する際の鍍金電極として形成している。
Further, in this embodiment, since the bump electrode 10 can be easily formed as a thick film having a thickness of 5 μm, it is possible to adjust the coating thickness of the photosensitive polyimide 11, heat treatment conditions, etc. Conductive polyimide 11 Top surface is bump electrode 10
It can be easily formed so as to be located between the upper surface and the upper surface of the bump electrode 7. Further, the photosensitive polyimide 11 does not need to be accurately aligned between the bump electrodes 10, and also need not be accurately aligned between the bump electrodes 7. The point is that the bump electrodes 7 can be completely embedded and formed so as to remain on the bump electrodes 7. Therefore, a positioning margin can be provided within a range that is larger than the width of the bump electrodes 7 and smaller than the width between the bump electrodes 10. You should consider it. Therefore, since the photosensitive polyimide 11 is formed on the bump electrodes 7 so as to be separated from the bump electrodes 10, it is possible to prevent the leakage between the bump electrodes 7 in the dicing process which has been a conventional problem. In addition, even if a piece of the adhesive 12a of the adhesive tape 12 adheres to the photosensitive polyimide 11, since the photosensitive polyimide 11 and the bump electrode 10 are separated from each other as described above, the bump electrode
It will not leak between 10 minutes. (Embodiment 2) FIGS. 3 and 4 are views for explaining a method of manufacturing a semiconductor device according to Embodiment 2 of the present invention. In FIGS. 3 and 4, 15 is a substrate such as Si, 16 is an insulating film such as SiO 2 formed on the substrate 15, and 17 is a wiring layer pattern such as Al formed on the insulating film 16. is there. Next, 18 is an insulating film having an opening 18a in which the wiring layer pattern 17 is exposed, and 18 to 20 are Ti film and Pd film respectively formed so as to contact with the wiring layer pattern 17 in the insulating film 18. , A
u is a bump electrode such as u, 21 is a high-sensitivity positive photosensitive resist, and 22 is a lower-sensitive positive photosensitive resist than the photosensitive resist 21 formed on the photosensitive resist 21. . Next, 21a is a resist pattern having an opening 21b in which the Pd film 20 formed by patterning the photosensitive resist 21 is exposed, and 22a has a width smaller than the width of the resist pattern 21a formed by patterning the resist 22. Reference numeral 23 is a resist pattern having an opening 22b, and 23 is a bump electrode whose upper portion has a width smaller than that of the lower portion. The bump electrodes 23 are embedded between the lower portions of the bump electrodes 23 having a large width, and are formed up to the upper surface of the lower portions of the bump electrodes 23 having a large width between the upper portions of the bump electrodes 23 having a small width. And the bump electrode 23 is a photosensitive polyimide formed so as to be located between the upper surface of the small width. Further, 25 is an adhesive tape for dicing, which is composed of the adhesive 25a and the base material 25b, and 26 is an ILB electrode for contacting with the bump electrode 23. The Ti film
19 is Au of the bump electrode 23 of the upper layer and the wiring layer pattern of the lower layer
17 is formed as a barrier film for preventing Al from diffusing and reacting, and the Pd film 20 is plated with Au to form the bump electrode 23.
It is formed as a plating electrode when forming.

【0026】次に、その半導体装置の製造方法について
説明する。まず、図3(a)に示すように、CVD法等
によりSi基板15上にSiO2 を堆積して膜厚1.0μm
の絶縁膜16を形成し、スパッタ法等により絶縁膜16上に
Alを堆積して膜厚1.3μmのAl膜を形成した後、R
IE等によりAl膜をエッチングして配線層パターン17
を形成する。次いで、CVD法等により全面にSiO2
を堆積して膜厚1.0μmの絶縁膜18を形成し、RIE等
により絶縁膜18をエッチングして配線パターン17が露出
された開口部18aを形成した後、スパッタ法により開口
部18a内の配線層パターン17とコンタクトを取るように
膜厚500ÅのTi膜19及び膜厚500ÅのPd膜20を形成す
る。次いで、全面にポジ型で高感度のレジスト21を塗布
した後、レジスト21上にポジ型でレジスト21よりも低感
度のレジスト22を形成する。
Next, a method of manufacturing the semiconductor device will be described. First, as shown in FIG. 3A, SiO 2 is deposited on the Si substrate 15 by the CVD method or the like to obtain a film thickness of 1.0 μm.
Is formed on the insulating film 16 by a sputtering method or the like to form an Al film having a thickness of 1.3 μm.
Wiring layer pattern 17 by etching the Al film by IE or the like
To form. Then, SiO 2 is formed on the entire surface by CVD or the like.
Is deposited to form an insulating film 18 having a film thickness of 1.0 μm, the insulating film 18 is etched by RIE or the like to form an opening 18a in which the wiring pattern 17 is exposed, and then the wiring in the opening 18a is formed by a sputtering method. A Ti film 19 having a film thickness of 500Å and a Pd film 20 having a film thickness of 500Å are formed so as to make contact with the layer pattern 17. Next, after a positive resist 21 having a high sensitivity is applied on the entire surface, a positive resist 22 having a lower sensitivity than the resist 21 is formed on the resist 21.

【0027】次に、図3(b)に示すように、露光・現
像によりレジスト21,22をパターニングしてバンプ電
極が形成される領域以外の領域に幅50μmのレジストパ
ターン21a及びレジストパターン21a幅よりも小さい幅
の幅40μmのレジストパターン22aを形成する。この
時、レジストパターン21a間にPd膜20が露出される開
口部21b及びレジストパターン22a間に開口部21b幅よ
りも小さい幅の開口部22bを形成する。
Next, as shown in FIG. 3B, the resists 21 and 22 are patterned by exposure and development to form a resist pattern 21a having a width of 50 μm and a resist pattern 21a width in a region other than a region where bump electrodes are formed. A resist pattern 22a having a width smaller than that of 40 μm is formed. At this time, the opening 21b exposing the Pd film 20 between the resist patterns 21a and the opening 22b having a width smaller than the width of the opening 21b is formed between the resist patterns 22a.

【0028】次いで、レジストパターン21a,22aをマ
スクとし、Pd膜20を鍍金電極とし、鍍金により開口部
21b,22b内を埋め込むようにPd膜20上に上部(幅40
μm)が下部(幅50μm)よりも幅の小さいバンプ電極
23を形成する。この時、バンプ電極23の幅の大きい下部
の膜厚は15μmであり、幅の小さい上部の膜厚は5μm
である。
Next, the resist patterns 21a and 22a are used as masks, the Pd film 20 is used as a plating electrode, and an opening is formed by plating.
An upper portion (width 40 mm) is formed on the Pd film 20 so as to fill the insides of 21b and 22b.
bump electrode whose width (μm) is smaller than the lower part (width 50 μm)
Form 23. At this time, the film thickness of the lower portion of the bump electrode 23 having a large width is 15 μm, and the film thickness of the upper portion having a small width is 5 μm.
Is.

【0029】次に、図3(c)に示すように、O2 アッ
シング等によりレジストパターン21a, 22aを除去した
後、バンプ電極23をマスクとし、RIE等によりPd膜
20及びTi膜19をエッチングして絶縁膜18を露出させ
る。この時、バンプ電極23下のみにPd膜20及びTi膜
19が残る。次に、図3(d)に示すよう、全面に感光性
ポリイミド24を塗布した後、図4(c)に示すように、
露光・現像によりバンプ電極23幅の大きい下部間を埋め
込み、かつバンプ電極23幅の小さい上部間の幅の小さい
上部上に残るように感光性ポリイミド24をパターニング
する。
Next, as shown in FIG. 3C, after removing the resist patterns 21a and 22a by O 2 ashing or the like, the Pd film is formed by RIE or the like using the bump electrode 23 as a mask.
20 and the Ti film 19 are etched to expose the insulating film 18. At this time, the Pd film 20 and the Ti film are provided only under the bump electrode 23.
19 remains. Next, as shown in FIG. 3D, after applying the photosensitive polyimide 24 on the entire surface, as shown in FIG.
The photosensitive polyimide 24 is patterned by exposure and development so that the lower part of the bump electrode 23 having a large width is filled and the upper part of the bump electrode 23 having a small width is left on the upper part having a small width.

【0030】次に、図4(f)に示すように、感光性ポ
リイミド24を350℃、120分キュアすることにより、バン
プ電極23の幅の小さい上部上面とバンプ電極23幅の大き
い下部上面間に感光性ポリイミド24上面がくるように熱
収縮させる。そして、図4(g)に示すように、ダイシ
ング処理用の接着テープ25をバンプ電極23上に張り付
け、接着テープ25を張り付けた状態でダイシング処理し
てチップ毎に分離した後、バンプ電極23とILB電極26
をILB処理してボンディングすることにより、図4
(h)に示すような半導体装置を得ることができる。
Next, as shown in FIG. 4 (f), the photosensitive polyimide 24 is cured at 350 ° C. for 120 minutes so that a space between the upper upper surface of the bump electrode 23 having a smaller width and the lower upper surface of the bump electrode 23 having a large width is obtained. Heat-shrink so that the upper surface of the photosensitive polyimide 24 comes. Then, as shown in FIG. 4 (g), an adhesive tape 25 for dicing is attached to the bump electrodes 23, and the adhesive tape 25 is attached to the bump electrodes 23 after dicing to separate the chips into chips. ILB electrode 26
By performing the ILB treatment on and bonding
A semiconductor device as shown in (h) can be obtained.

【0031】このように、本実施例では、バンプ電極23
の上部が下部の幅よりも小さい幅になるように形成し、
全面に塗布された感光性ポリイミド24を露光・現像によ
りバンプ電極23幅の大きい下部間を埋め込み、かつバン
プ電極23幅の小さい上部間のバンプ電極23幅の大きい下
部上に残るようにパターニングした後、感光性ポリイミ
ド24をキュアしてバンプ電極23幅の大きい下部上面とバ
ンプ電極23幅の小さい上部上面間に感光性ポリイミド24
上面がくるように熱収縮させている。このように、感光
性ポリイミド24上面がバンプ電極23幅の小さい上部上面
より下側にくるようにしたため、ダイシング処理用接着
テープ25をバンプ電極23幅の小さい上部に張り付けてダ
イシング処理することができる。このため、感光性ポリ
イミド24をバンプ電極23幅の小さい上部上にまで形成し
て伴う、ダイシング処理時に生じるバンプ電極23幅の小
さい上部上への接着剤25aの破片の付着を生じないよう
にすることができる。しかも、ILB電極26幅が感光性
ポリイミド24間の幅よりも広くても、感光性ポリイミド
24上面がバンプ電極23幅の小さい上部上面よりも下側に
あるため、バンプ電極23幅の小さい上部とILB電極26
を確実にコンタクトさせることかできる。
Thus, in this embodiment, the bump electrode 23
The width of the upper part is smaller than the width of the lower part,
After patterning the photosensitive polyimide 24 coated on the entire surface by exposing and developing so as to fill the space between the lower portions of the bump electrode 23 having a large width and to leave the upper portion of the bump electrode 23 having a small width on the lower portion of the bump electrode 23 having a large width. , The photosensitive polyimide 24 is cured, and the photosensitive polyimide 24 is interposed between the lower upper surface of the bump electrode 23 having a larger width and the upper upper surface of the bump electrode 23 having a smaller width.
Heat shrink so that the top surface comes. Since the upper surface of the photosensitive polyimide 24 is located below the upper surface of the bump electrode 23 having a small width in this manner, the dicing processing adhesive tape 25 can be attached to the bump electrode 23 having a small width to perform the dicing processing. . Therefore, the photosensitive polyimide 24 is formed even on the upper portion of the bump electrode 23 having a smaller width, so that the adhesion of the fragments of the adhesive 25a on the upper portion of the bump electrode 23 having a smaller width that occurs during the dicing process is prevented. be able to. Moreover, even if the width of the ILB electrode 26 is wider than the width between the photosensitive polyimides 24,
Since the upper surface of the bump electrode 23 is lower than the upper surface of the bump electrode 23 having a small width, the bump electrode 23 has a small width and the ILB electrode 26.
Can be surely contacted.

【0032】また、本実施例では、バンプ電極23幅の小
さい上部は膜厚5μmと厚膜に容易に形成することがで
きるため、感光性ポリイミド24の塗布厚、熱処理条件等
を適宜調整することにより、感光性ポリイミド24上面は
バンプ電極23幅の小さい上部上面とバンプ電極23幅の大
きい下部上面間にくるように容易に形成することができ
る。そして、感光性ポリイミド24はバンプ電極23幅の小
さい上部間で正確に位置合わせする必要もなく、しか
も、バンプ電極23幅の大きい下部間で正確に位置合わせ
する必要もない。要はバンプ電極23幅の大きい下部間を
完全に埋め込み、かつバンプ電極23幅の小さい上部上に
残るように形成すればよいので、バンプ電極23幅の小さ
い上部幅より大きく、かつバンプ電極23幅の大きい下部
間の幅よりも小さい範囲内で位置合わせ余裕を考慮して
行えばよい。このため、感光性ポリイミド24はバンプ電
極23幅の小さい上部と離間してバンプ電極23幅の大きい
上部上に形成されるため、従来問題であったダイシング
処理でのバンプ電極幅の大きい下部間でのリークを生じ
ないようにすることができるうえ、感光性ポリイミド24
上に接着テープ25の接着剤25aの破片が付着しても上記
の如く感光性ポリイミド24とバンプ電極23幅の小さい上
部は離間しているため、バンプ電極23の幅の小さい上部
間でリークすることもない。
Further, in this embodiment, since the upper portion of the bump electrode 23 having a small width can be easily formed as a thick film having a thickness of 5 μm, the coating thickness of the photosensitive polyimide 24, the heat treatment conditions, etc. should be adjusted appropriately. Thus, the upper surface of the photosensitive polyimide 24 can be easily formed so as to be located between the upper upper surface having the smaller width of the bump electrode 23 and the lower upper surface having the larger width of the bump electrode 23. Further, the photosensitive polyimide 24 does not need to be accurately aligned between the upper portions having a small width of the bump electrodes 23, and further, need not be accurately aligned between the lower portions having a large width of the bump electrodes 23. The point is that the space between the lower portions of the bump electrode 23 having a large width can be completely filled and the bump electrode 23 can be formed so as to remain on the upper portion of the small width of the bump electrode 23. The alignment margin may be taken into consideration within a range smaller than the width between the lower portions having a large width. Therefore, since the photosensitive polyimide 24 is formed on the upper portion of the bump electrode 23 having a larger width apart from the upper portion of the bump electrode 23 having a smaller width, the photosensitive polyimide 24 is formed between the lower portion of the bump electrode 23 having a large width in the conventional dicing process. In addition to preventing the leak of the photosensitive polyimide 24
Even if a piece of the adhesive 25a of the adhesive tape 25 adheres to the upper portion of the bump electrode 23, since the photosensitive polyimide 24 and the upper portion of the bump electrode 23 having a smaller width are separated from each other as described above, leakage occurs between the upper portions of the bump electrode 23 having a smaller width. Nothing.

【0033】なお、実施例2ではレジスト21,22にポジ
型レジストを用い、レジスト21には高感度なものを用
い、レジスト22には低感度のものを用いる場合について
説明したが、本発明はこれに限定されるものではなく、
レジスト21,22はネガ型レジストを用いてもよく、この
場合、レジスト21には低感度のものを用い、レジスト22
には高感度のものを用いればよい。
In the second embodiment, positive resists are used as the resists 21 and 22, a highly sensitive resist 21 is used, and a low sensitive resist 22 is used. However, the present invention is not limited to this. It is not limited to this,
Negative type resists may be used as the resists 21 and 22, and in this case, the resist 21 having low sensitivity is used.
A high-sensitivity one may be used.

【0034】[0034]

【発明の効果】本発明によれば、バンプ電極間のリーク
を生じないようにすることができ、しかもバンプ電極は
ILB電極のコンタクト不良を生じさせることなく確実
にコンタクトすることができるという効果がある。
According to the present invention, it is possible to prevent leakage between the bump electrodes and to reliably contact the bump electrodes without causing contact failure of the ILB electrodes. is there.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例1に則した半導体装置の製造方
法を説明する図である。
FIG. 1 is a diagram illustrating a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の実施例1に則した半導体装置の製造方
法を説明する図である。
FIG. 2 is a diagram illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

【図3】本発明の実施例2に則した半導体装置の製造方
法を説明する図である。
FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to the second embodiment of the present invention.

【図4】本発明の実施例2に則した半導体装置の製造方
法を説明する図である。
FIG. 4 is a diagram illustrating a method of manufacturing a semiconductor device according to the second embodiment of the present invention.

【図5】従来例の半導体装置の製造方法を説明する図で
ある。
FIG. 5 is a diagram illustrating a method for manufacturing a conventional semiconductor device.

【図6】従来例の別の半導体装置の製造方法を説明する
図である。
FIG. 6 is a diagram illustrating another conventional method for manufacturing a semiconductor device.

【図7】図6に示す従来の半導体装置の製造方法の課題
を説明する図である。
FIG. 7 is a diagram illustrating a problem of the conventional method for manufacturing the semiconductor device shown in FIG.

【符号の説明】[Explanation of symbols]

1,15 基板 2,4,16,18 絶縁膜 3 配線層パターン 4a,8a,9a レジストパターン 5,19 Ti膜 6,20 Pd膜 7,10,23 バンプ電極 8,9,21,22 レジストマスク 11,24 感光性ポリイミド 12,25 接着テープ 12a,25a 接着剤 12b,25b 基材 13,26 ILB電極 18a,21b,22b 開口部 21a,22a レジストパターン 1,15 substrate 2,4,16,18 insulating film 3 wiring layer pattern 4a, 8a, 9a resist pattern 5,19 Ti film 6,20 Pd film 7,10,23 bump electrode 8,9,21,22 resist mask 11,24 Photosensitive polyimide 12,25 Adhesive tape 12a, 25a Adhesive 12b, 25b Base material 13,26 ILB electrodes 18a, 21b, 22b Openings 21a, 22a Resist pattern

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 下地の膜(2)上に導電性領域(3,
5,6)と絶縁性領域(4)を形成する工程と、 次いで、該絶縁性領域(4)上のバンプ電極が形成され
る領域以外の領域に該導電性領域(6)が露出された第
1の開口部(8a)を有する第1のマスクパターン
(8)を形成する工程と、 次いで、該第1のマスクパターン(8)をマスクとし、
該導電性領域(6)を鍍金電極とし、鍍金により該第1
の開口部(8a)内を埋め込むように該導電性領域
(6)上に第1のバンプ電極(7)を形成する工程と、 次いで、該第1のマスクパターン(8)上から該第1の
バンプ電極(7)上にかけて該第1のマスクパターン
(8)幅よりも広い幅で、かつ該第1のバンプ電極
(7)が露出された第2の開口部(9a)を有する第2
のマスクパターン(9)を形成する工程と、 次いで、該第2のマスクパターン(9)をマスクとし、
該第1のバンプ電極(7)を鍍金電極とし、鍍金により
該第2の開口部(9a)内を埋め込むように該第1のバ
ンプ電極(7)上に該第1のバンプ電極(7)幅よりも
小さい幅の第2のバンプ電極(10)を形成する工程と、 次いで、該第1、第2のマスクパターン(8,9)を除
去する工程と、 次いで、全面に感光性ポリイミド(11)を形成する工程
と、 次いで、露光・現像により該第1のバンプ電極(7)間
を埋め込み、かつ該第2のバンプ電極(10)間の該第2
のバンプ電極(7)上に残るように該感光性ポリミイド
(11)をパターニングする工程と、 次いで、該感光性ポリイミド(11)を熱処理することに
より、該第1のバンプ電極(7)上面と該第2のバンプ
電極(10)上面間に該感光性ポリイミド(11)上面がく
るように熱収縮させる工程とを含むことを特徴とする半
導体装置の製造方法。
1. A conductive region (3, 3) formed on a base film (2).
5, 6) and a step of forming an insulating region (4), and then the conductive region (6) is exposed in a region other than the region where the bump electrode is formed on the insulating region (4). Forming a first mask pattern (8) having a first opening (8a), and then using the first mask pattern (8) as a mask,
The conductive region (6) is used as a plating electrode, and the first electrode is formed by plating.
Forming a first bump electrode (7) on the conductive region (6) so as to fill the opening (8a) of the first mask pattern (8). A second opening (9a) having a width wider than the width of the first mask pattern (8) over the bump electrode (7) and exposing the first bump electrode (7).
And a step of forming a mask pattern (9) of
The first bump electrode (7) is used as a plating electrode, and the first bump electrode (7) is formed on the first bump electrode (7) so as to fill the inside of the second opening (9a) by plating. A step of forming the second bump electrode (10) having a width smaller than the width, a step of removing the first and second mask patterns (8, 9), and a photosensitive polyimide ( 11) is formed, and then the first bump electrodes (7) are filled with the second bump electrodes (10) by exposing and developing.
Patterning the photosensitive polyimide (11) so that the photosensitive polyimide (11) is left on the bump electrode (7), and then heat-treating the photosensitive polyimide (11) to form an upper surface of the first bump electrode (7). And a step of heat-shrinking so that the upper surface of the photosensitive polyimide (11) is located between the upper surfaces of the second bump electrodes (10).
【請求項2】 下地の膜(16)上に導電性領域(17,1
9,20)と絶縁性領域(18)を形成する工程と、 次いで、全面に第1の感光性有機膜(21)と該第1の感
光性有機膜(21)と光感度の異なる第2の感光性有機膜
(21)を順次形成する工程と、 次いで、露光・現像により、該絶縁性領域(18)上のバ
ンプ電極が形成される領域以外の領域に第1の感光性有
機膜パターン(21a)及び該第1の感光性有機膜パター
ン(21a)幅よりも小さい幅の第2の感光性有機膜パタ
ーン(22a)を形成するとともに、該第1の感光性有機
膜パターン(21a)間に該導電性領域(20)が露出され
る第1の開口部(21b)及び該第2の感光性有機膜パタ
ーン(22a)間に第1の開口部(21b)幅よりも小さい
幅の第2の開口部(22b)を形成する工程と、 次いで、該第1,第2の感光性有機膜パターン(21a,
22a)をマスクとし、該導電性領域(20)を鍍金電極と
し、鍍金により該第1,第2の開口部(21b,22b)内
を埋め込むように該導電性領域(20)上に上部が下部よ
りも幅の小さいバンプ電極(23)を形成する工程と、 次いで、該第1,第2の感光性有機膜パターン(21a,
22a)を除去する工程と、 次いで、全面に感光性ポリイミド(24)を形成する工程
と、 次いで、露光・現像により該バンプ電極(23)幅の大き
い下部間を埋め込み、かつ該バンプ電極(23)幅の小さ
い上部間に残るように該感光性ポリイミド(24)をパタ
ーニングする工程と、 次いで、該感光性ポリイミド(24)を熱処理することに
より、該バンプ電極(23)幅の小さい上部上面と該バン
プ電極(23)幅の大きい下部上面間に該感光性ポリイミ
ド(24)上面がくるように該感光性ポリイミド(24)を
熱収縮させる工程とを含むことを特徴とする半導体装置
の製造方法。
2. A conductive region (17, 1) formed on the underlying film (16).
9, 20) and an insulating region (18) are formed, and then a first photosensitive organic film (21) and a second photosensitive organic film (21) having a different photosensitivity over the entire surface. Forming a photosensitive organic film (21) in sequence, and then exposing and developing the first photosensitive organic film pattern in a region other than the region where the bump electrode is formed on the insulating region (18). (21a) and a second photosensitive organic film pattern (22a) having a width smaller than the width of the first photosensitive organic film pattern (21a), and at the same time, the first photosensitive organic film pattern (21a) A width smaller than the width of the first opening (21b) is provided between the first opening (21b) and the second photosensitive organic film pattern (22a) where the conductive region (20) is exposed. A step of forming a second opening (22b), and then the first and second photosensitive organic film patterns (21a,
22a) is used as a mask, the conductive region (20) is used as a plating electrode, and an upper part is formed on the conductive region (20) so as to fill the inside of the first and second openings (21b, 22b) by plating. A step of forming bump electrodes (23) having a width smaller than that of the lower part, and then the first and second photosensitive organic film patterns (21a,
22a), then a step of forming a photosensitive polyimide (24) on the entire surface, and then, by exposing and developing, filling the lower part of the bump electrode (23) having a large width and ) A step of patterning the photosensitive polyimide (24) so that it remains between the upper portions having a small width, and then, by subjecting the photosensitive polyimide (24) to a heat treatment, an upper upper surface having a small width of the bump electrodes (23). And a step of heat-shrinking the photosensitive polyimide (24) so that the upper surface of the photosensitive polyimide (24) is located between the lower upper surfaces of the bump electrodes (23) having a large width. .
JP4210382A 1992-08-06 1992-08-06 Manufacture of semiconductor device Withdrawn JPH0661233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4210382A JPH0661233A (en) 1992-08-06 1992-08-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4210382A JPH0661233A (en) 1992-08-06 1992-08-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0661233A true JPH0661233A (en) 1994-03-04

Family

ID=16588419

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4210382A Withdrawn JPH0661233A (en) 1992-08-06 1992-08-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0661233A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176858A (en) * 1997-12-08 1999-07-02 Rohm Co Ltd Manufacture of semiconductor chip and continuity connection method for the semiconductor chip
KR20010062889A (en) * 1999-12-21 2001-07-09 박종섭 Tape carrier package and manufacture method thereof
JP2002134545A (en) * 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd Semiconductor integrated circuit chip, board and their manufacturing method
KR100793423B1 (en) * 2004-08-30 2008-01-11 엘지전자 주식회사 Manufacturing method of printed circuit board
JP2012069761A (en) * 2010-09-24 2012-04-05 Shinko Electric Ind Co Ltd Semiconductor element, semiconductor element mounting body, and manufacturing method of semiconductor element

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11176858A (en) * 1997-12-08 1999-07-02 Rohm Co Ltd Manufacture of semiconductor chip and continuity connection method for the semiconductor chip
KR20010062889A (en) * 1999-12-21 2001-07-09 박종섭 Tape carrier package and manufacture method thereof
JP2002134545A (en) * 2000-10-26 2002-05-10 Oki Electric Ind Co Ltd Semiconductor integrated circuit chip, board and their manufacturing method
KR100793423B1 (en) * 2004-08-30 2008-01-11 엘지전자 주식회사 Manufacturing method of printed circuit board
JP2012069761A (en) * 2010-09-24 2012-04-05 Shinko Electric Ind Co Ltd Semiconductor element, semiconductor element mounting body, and manufacturing method of semiconductor element

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