JPH0654488B2 - Processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor suitable for constituting a single processor or a multi-processor.

[Conventional technology]

Conventionally, multi-processor systems have been disclosed in
As disclosed in Japanese Patent Laid-Open No. 59-208666, it comprises one CPU and memory, another processor element and a bus switch which operates as a master / slave. Such a single CP
Multi consisting of processor element by U
In the processor system, there is no problem as far as dedicated task processing with less disturbance, but as the processing contents required for the system such as intelligent control processing become sophisticated, database and system status management, database and sensor information A knowledge processing system configuration based on SQL, multiple interrupt processing, multi-job function, etc. are required to support back ground processing system, and real-time multi-tasking, multi-job support high-class language on a high-class operating system. It is general to describe and execute the processing by.

[Problems to be solved by the invention]

In the above-mentioned conventional multi-processor system, real-time control processing, which is the main factor for speeding up, is also positioned as one of the tasks supported by multi-tasking, so task switches, overheads, and disturbances in parallel processing schedules, etc. Is it currently impossible to perform fine-grained dense parallel processing? Therefore, a supervisor system often uses a system such as a super minicomputer to separate the intelligent processing system from the control processing system by parallel processing, but the communication between the parallel processing system and the intelligent processing system tends to be sparse. The operating system overhead is required to manage the local internal status of the control system, which does not take advantage of such characteristics as decentralization of intelligent processing and decentralization of system management, resulting in a substantial reduction in price / performance ratio. There is a problem that it is difficult to increase the processing performance of the intelligent processing system and improve the communication throughput between the two systems according to the expansion of the processing performance. Therefore, especially when the control loop of the control processing system is speeded up, relatively large amount of data needs to be exchanged at high speed between the intelligent processing system and the control processing system, and the above problem is serious in the hardware configuration. Therefore, the price / performance ratio will be significantly reduced.

An object of the present invention is to provide a processor capable of efficiently improving the substantial processing performance of a multi-processor system or a single processor system suitable for general-purpose processing in a well-balanced manner.

[Means for solving problems]

The above-mentioned object of the present invention is a processor for constituting a single processor or a multi-processor,
Two CPUs each having a local memory in a base processor element that constitutes the processor
And a dual port RAM (DPR) accessible from the CPUs of those hooks, and a common bus switch circuit that connects one of the CPUs to a common bus that can be used by the two CPUs. It

[Action]

The processor of the present invention provides a hardware architecture for operating two CPUs provided in the base processor element as if they were one processor. In addition, paying attention to the high independence of the control processing system and the intelligent processing system based on the database and the sensor information, the control processing system is assigned to the main processing system of the main CPU so that the control calculation is performed with other base processor elements. Tightly coupled parallel processing is used to execute interrupt processing, system management, knowledge processing, etc.
A process having a strong background element is assigned to the background processing system of the main CPU and the background CPU as an intelligent processing system to backup the control processing system of the main CPU. As a result, task, switch, overhead, and interrupt factors that disturb the parallel processing can be removed as much as possible, and two highly independent processing systems can be operated in parallel with high efficiency. In addition to substantially improving the processing performance of the base processor element by a factor of two, even in a multi-processor system in which a plurality of base processor elements are combined, the total processing performance of the conventional double,
It is possible to realize a balanced processing performance expansion of the control processing system and the intelligent processing system in response to the expansion of the base processor element.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a processor of the present invention. In this figure, the internal configuration of a base processor element (BPE) 1 that constitutes a multi-processor system is two CPUs 15 and 16 (CPU θ and CPU 1 )
And a dual port RAM (DPR) 17 as a dedicated communication mechanism between the two CPUs 15 and 16, and one of the CPUs between the two CPUs for communicating with another base processor element (BPE). In order to connect to the BPE local bus 12 which is a common bus of the CPU 15, a common bus switch 24 composed of a multiplex bus buffer 23 which is switch-controlled by the common bus switch control circuit 22 without inconsistency is provided. 1
Between 6 and the base processor element (BP
It adopts a structure for performing communication processing between E). In addition, the two CPUs 15 and 16 each have a local memory 1
It has 8, 20 and local I / Os 19, 21 and the like, and is usually operable independently. Also, a dual port RAM (DPR) 1 that supports communication between CPUs
The seventh feature is that it has communication interrupt lines 32 and 33 to the CPUs 15 and 16 of each other, and a communication function between the CPUs 15 and 16 having a small overhead is provided. The local memory 6 and the local I / O 7 of the base processor element are connected to the local bus 12 of the base processor element 1, and a common bus line with other base processor elements is formed. Moreover, the system bus 14 to which the system shared memory 9 and the system shared I / O 10 are connected
A system bus switch 8 is provided for connecting to the. The system bus switch 8 performs bus arbitration processing regarding access to the system bus 14 through the arbitration line 13, and the system bus 1 is consistent.
4 can be used to perform parallel processing between the base processor elements by performing communication processing with other base processor elements.

FIG. 5 is a hardware block diagram of the dual port RAM (DPR) 17, in which the dual port RAM (DPR) 17 has two CPUs 15,
It can be regarded as a shared memory shared between 16 and 2
Dual port RAM (DP
Arbiter 60 that arbitrates access to R) by using access request signals and access permission signals of each processor indicated by reference numerals 77 to 80, and enable signal 7 from arbiter 60.
Bus switches 61 and 62 for switching the buses 64 and 65 from the CPU to the internal bus 66 in accordance with 5, 76 and the memory enable signal 81 and the interrupt control signal 73 by decoding the address and control lines of the internal bus 66. Decoder 67 for generating 74 and decoder 6 for setting and resetting interrupt signals 32 and 33 to each CPU
7 are comprised of flip-flops 68, 69 and the like which are operated by interrupt control signals 73, 74. The interrupt function for inter-CPU communication of the characteristic dual port RAM (DPR) is a register that generates an interrupt to the CPU θ at a specific address of the dual port RAM (DPR) and the CPU.
1 are each provided with a register for generating an interrupt, and at the same time, they are defined as instruction registers for the CPUs of the other, and instructions are sent and received and an interrupt is generated at the same time. CPU
Taking the case where 1 transmits an instruction to the CPU θ as an example, first, the CPU 1 sets the instruction attribute which the CPU 1 wants the CPU θ to execute in its own register or the like and sets it in the dual port RAM (D
When the instruction register to the CPU θ on the PR is stored, the decoder 67 indicates that the instruction register to the CPU θ has been accessed.
By knowing by monitoring and decoding the internal bus 67 of the AM (DPR), an instruction register access signal pulse to the CPU θ is transmitted using the access signal 73 to latch the value of the signal 70 to the flip prop 68. In addition,
In the initial state, Q is HI and LO is LO by the RESET signal 72.
Since it is set to 0, the above operation outputs LO to HI and HI to Q, and the interrupt signal 30 to the CPU θ which is LO active becomes active to CPU θ.

Next, the CPU θ that receives the interrupt again executes C in order to obtain the instruction to be executed in its interrupt service routine.
When the instructed instruction is found by referring to the instruction register to PUθ, the decoder 67 similarly monitors the access status, and the instruction register / access signal pulse to CPUθ is flipped using the access signal 73. Output to the flop 68, latch the HI 70 and output HI to Q. That is, the interrupt generation line 32 to the CPU θ is made inactive. By the above-mentioned sequence, it is possible to simultaneously execute a series of operations from generation of an interrupt to acceptance and operations related to software instruction exchange with a minimum overhead.

Returning to FIG. 1, the bass processor element (BP
E) Select either one of the CPU θ in 1 or the bus 28 or 29 of the CPU 1 and perform bus switching control (bus switch) for outputting as the BPE local bus 12 that can be regarded as a shared bus between the CPU θ and the CPU 1. The common bus switch 24 is composed of the shared bus switch control circuit 22 and the multiplex bus buffer 23 controlled by the shared bus switch control circuit 22 as described above. The bus switch control is simply performed by using the NOR circuits 83 and N shown in FIG. 4 when the CPU θ is the master and the CPU 1 is the slave.
This is performed by a shared bus switch logic provided with an AND circuit 84. The characteristic bus switch control sequence will be described together with the time chart of FIG.
First, the acquisition rights of the local buses 28 and 29 of the two CPUs are always on the respective CPUs side, and are not infringed by the Deheiss on other buses (,). The shared bus (BPE local bus 12) access request of the CPU θ is always active as shown in, and the shared bus access request of the CPU 1 is always active as shown in. That is, except when the CPU 1 acquires the shared bus, the CPU θ side always acquires the shared bus. In the example shown in FIG. 2, the CPU 1 outputs the shared bus access request 87 at a, and when the CPU θ receives the instruction and finishes the instruction processing being executed at that time, the shared bus right can be relinquished. The halt acknowledge 82 is output to deactivate the CPU θ shared bus access permission signal 85 (driven by the gate 83) at a and abandon the shared bus as shown at a. Further, at a, the CPU θ itself enters the halt state, and at the same time, at a, the shared bus access permission signal 86 (driven by the gate 84) of the CPU 1 becomes active, and the bus switch buffer 23 is activated as shown at a. The CPU1 side is selected and the right to use the shared bus is transferred to the CPU1. When it is time for the CPU 1 to finish using the shared bus and abandon the shared bus, the CPU 1 shared bus access request 87 is made inactive as shown in b. Immediately after that, at b, the CPU θ shared bus access permission signal 85 becomes active and the bus switch
After the CPU θ side of the buffer 23 is selected and the right to use the shared bus is transferred to the CPU θ, the CPU θ halt
The acknowledge is released, and the CPU θ shifts from the halt state to the production state at b. And are CPU θ and C
The actual operating state of each PU1 is shown. Since the master (CPU θ) and slave (CPU 1) operations described above are performed, the CPU θ performs bus switching while the right to use the shared bus is transferred to the CPU 1 (a-b), and the electrical and timing of the bus. For a short time (bb) during which the characteristics are adjusted without contradiction, a total time halt state occurs and no operation occurs. That is, in terms of the production right, the CPU 1 operates as a master. A mode is provided for transferring the right to use the shared bus to the CPU θ for each data transfer so that the halt time becomes too long and the operation of the CPU θ is not interrupted. However, as described below, C
When PUθ is used as a main CPU and CPU1 is used as a back ground CPU for intelligent processing to support CPUθ, and a multi-processor configuration is adopted, a base processor element (BPE) unit function distribution structure By adopting the distributed knowledge base form of MPU, most necessary data can be obtained near oneself, and most of the data communication is performed by the dual port RAM (DP).
R) can be used. Therefore, the base
The rate at which knowledge information is exchanged between the processor elements (BPE) is sufficiently smaller than the rate at which the CPU θ exchanges information with other base processor elements (BPE) due to the tightly coupled parallel processing. It can be considered that the CPU θ has a negligible processing power loss.
When the role of the CPU 1 is fixed to perform back-up and system management of the CPU θ,
It is more effective for the CPU 1 to have the operation control right of 1. from the viewpoint of management and the like, and it can be said that the shared bus control of the present invention is suitable for the local distributed processing as described above.

Next, the general operation of the processor of the present invention described above will be described in detail with reference to FIG.

In FIG. 3, the CPU θ performs the main control calculation, and the CPU 1
Is assumed to perform intelligent processing and system management based on a knowledge base (distributed type) or sensor information to back up the CPU θ in the background, and to perform local distributed processing. Also, if a multi-processor configuration is adopted, each base processor element (BP
E) is another base processor element (BPE)
At the same time, it is assumed that the main performs tightly coupled parallel processing and the background performs loosely coupled parallel processing. Reference numeral 35 indicates a processing flow of the CPU 1 along the time axis, and 3
Similarly, reference numerals 6, 37 and 38 show the processing flow of the CPU θ. The shared resources include a dual port RAM (DPR) which is a local shared memory between the CPU θ and the CPU 1 in the base processor element (BPE),
In the case of a multi-processor configuration, there are system shared resources on the system bus 14 accessible by all base processor elements (BPEs). 47,4
8, 54 and 59 indicate communication between the CPU θ and DPR, 4
Reference numerals 6, 53, 56 and 58 indicate communication between the CPU 1 and the DPR. Similarly, 57 indicates the communication between the CPU θ and the system shared resource, and 51 indicates the communication between the CPU 1 and the system shared resource.
It is regarded as an access from the base processor element (BPE). 50 is a dual port RAM
An interrupt to the CPU θ using the interrupt function on (DPR) is shown, and 55 is also an interrupt to the CPU 1. 49 is a shared bus access request signal from the CPU 1 to the CPU θ and a corresponding shared bus from the CPU θ.
The state of handshake with the access permission signal is shown, and 52 shows how the shared bus once acquired by the CPU 1 is abandoned and its usage right is transferred to the CPU θ again. Reference numerals 88 and 89 denote access to system shared resources from other BPEs. Reference numerals 90 and 91 indicate that local sensor information, which is external information, is taken in during the processing of the CPU 1 as a part of the knowledge. Similarly, reference numerals 92 and 93 indicate shared sensors shared by other BPEs. It is shown that the information is taken in by the CPU θ and the CPU 1. Regarding the processing contents of the CPU θ and the CPU 1, the CPU θ is the main processing system, and together with the CPU θ of the other base processor element (BPE), controls a part of the intelligent mechanical system, for example, the arm part of the humanoid robot. It is assumed that a large number of necessary control calculation tasks are shared so that the degree of parallelism is improved and high-efficiency tightly coupled parallel processing 36b and 38b are executed, and the processing is requested to an auxiliary processor such as a calculation processor. Free time, free time that occurs during synchronization processing with other base processor elements (BPE), and CPU1 as a background processing system when processing is requested by an interrupt from another base processor element BPE or CPU1 and shared resources. Jointly conducts intelligence processing, system management, etc. shown in 36a and 38a. , Constituting the intelligent processing system with the processing 35 of the CPU 1. The intelligent processing system executed by this base processor element (BPE) holds a part of the arm part, for example, a group of information about the muscle part as a data base,
The local sensor information, which is deeply related to it, is taken in as perceptual information, and the intelligence processing about the muscle part is executed based on the local function distributed database constructed by them, and is executed by the main processing system. The entire control calculation is supposed to be backed up.

In the system based on the above assumption, the processing flows of the CPU θ and the CPU 1 shown in FIG. 3 will be briefly followed. First, the CPU θ and the CPU 1 are executing the processes 36 and 35 shown in FIG. 3, respectively.
At a time point 39 when communication with PU θ is required, a communication message is written in the dual port RAM (DPR), and the operation 46 of writing the communication content as an instruction in the instruction register to the CPU θ is performed. Correspondingly, an interrupt 50 to the CPU θ occurs, the dual port RAM (DPR) is accessed in the background processing system of the CPU θ, and communication 47 of necessary information is performed. At the time of 40, CPU θ
However, shared data between CPUs that do not need to be handshaked is written to the dual port RAM (DPR) or read from the dual port RAM (DPR) in a spillover manner. Various sensor information is also taken in as a part of the knowledge by the sensor side being the subject and being sequentially processed by an interrupt, or being referred to in the program as necessary. Next, CPU1 is another bass processor
In order to communicate with the element (BPE), it becomes necessary to communicate with the system shared resource, and at 49, the right to use the common bus (BPE local bus) 12 is acquired, and at 41, communication 51 with the system shared memory is obtained. When completed, at 52, the right to use the common bus is transferred to the CPU θ again. During that time, the CPU θ is kept in the halt state 37, and when the halt state is released by 52, the process 38 which is a continuation of the process 36.
To continue. After that, at the time of 42, the CPU 1 and the dual-port RAM communicate (DPR) with the shared data between the CPUs, and at the time of 43, the CPU θ changes from the CPU θ to the CPU.
Communication of handshake data with an instruction to 1 is executed in the same manner as 39. In 44, communication 57 between the CPU θ and the system shared resource is performed. The communication content is communication related to intelligent processing in the background processing 38a and communication of tightly coupled parallel processing data related to control calculation in the main processing 38b. Done, CPU1
It does not affect the processing and operation of. 45 is a CPU
θ and the dual port RAM (DPR) of the CPU 1 show that the run-off communication is being performed at substantially the same time.
By the control, communication processing is executed without any hindrance to the processing and operation of each other.

When the processor of the present invention realizes the intelligent processing system and the control processing system backed up by the local distributed database as described above, most of the intelligent processing is performed by the base processor element via the dual port RAM (DPR). It may be executed between the CPUs in the (BPE), and sometimes the processing results and other base processors
Since it is sufficient to access the system shared resource in order to exchange the intelligent processing result by the element (BPE),
It is possible to realize the best communication throughput between the communication nodes in the system, and to double the processing performance because the control processing system and the intelligent processing system can operate almost completely independently and in parallel. Is possible. Further, by adding BPEs, the processing performance of the intelligent processing system and the processing performance of the control processing system increase in proportion to each other, and it is possible to always provide the processing performance in which both are balanced.

According to an embodiment of the present invention, a processor element (base processor element: B) that is the basis of a multi-processor system or a single processor system.
PE) is composed of two CPUs, which can be commonly used by both CPUs that look like a single CPU when observed from the outside by dual port RAM (DPR) with interrupt function and master / slave operation. It connects with a common bus, separates a highly independent main processing system and a background processing system, and separates them into two CPUs, and the local information exchange between the two CPUs is a dual port RAM (DPR). Common bus (BPE local bus) for communication with other base processor elements (BPE) in the case of multi-processor configuration.
The performance of the BPE is substantially doubled by performing through the system shared resource on the system bus.
Further, when a processor of the present invention is used to configure a multi-processor system, the database of the background processing system is functionally distributed and has each BPE unit, so that in the background processing system, most of the processors are in the processor. It does not have to be closed by local communication and frequently communicate with other processors, which optimizes the communication throughput between communication nodes, which has a great impact on the tightly coupled parallel processing executed in the main. Instead, both the main processing system and the background processing system can naturally perform highly efficient parallel processing. Further, by adding the processor of the present invention, it is possible to always improve the processing capacity in a balanced manner in both the main processing and the background processing system.

〔The invention's effect〕

As described above, according to the present invention, the substantial processing performance of a multi-processor system or a single processor system suitable for general-purpose processing can be efficiently improved in a well-balanced manner.

[Brief description of drawings]

FIG. 1 is a diagram showing an internal structure of a base processor element in a processor of the present invention and a part of a multi-processor system according to the internal structure, and FIG. 2 is two CPs in the base processor element constituting the present invention.
FIG. 4 is a diagram showing a common bus (BPE local) switch sequence between Us, FIG. 3 is a diagram showing a flow of processing between two CPUs in the base processor element, and FIG. 4 is a shared bus constituting the present invention. .Basic logic diagram of switch,
FIG. 5 is a logic block diagram of the dual port RAM which constitutes the present invention. 1 ... Base processor element (BPE), 8 ...
System bus switch, 14 ... System bus, 1
5 ... CPUθ (master), 16 ... CPU1 (slave), 17 ... DPR logic, 24 ... Common bus switch, 32 ... Instruction interrupt line to CPUθ, 33 ... CP
Instruction interrupt line to U1, 73 ... Flip-flop for generating interrupt to CPUθ, 74 ... Flip-flop for generating interrupt to CPU1, 85 ... CPUθ common bus access permission signal, 86 ... CPU1 common bus access permission signal.

Claims (7)

[Claims] 1. First information supplied from a common bus,
In a processor for processing second information related to the first information, a first CPU for processing the first information supplied through the common bus and a second information for processing the second information supplied through the common bus. Second CPU to do
And, in response to a request from the first CPU or the second CPU, stores information processed by the first CPU or the second CPU, and stores the stored information in the first CPU or the second CPU.
Dual port RAM for outputting to the CPU of the
Switch means for switching the CPU or the second CPU to the common bus, and connects the first CPU or the second CPU to the common bus in response to a signal from the first CPU or the second CPU. To do
A processor comprising: a control unit that controls the switch unit. 2. The control means, in response to an instruction from the first CPU or the second CPU, controls the switch means so that the first CPU or the second CPU is always in contact with the common bus. The processor according to claim 1, wherein: 3. The control means, in response to an instruction from the first CPU or the second CPU, controls the switch means so as to switch and connect a common bus which is always in contact with one CPU to the other CPU. The processor according to claim 1, wherein: 4. The first CPU or the second CPU
The processor according to claim 1, further comprising means for monitoring the operation of the second CPU or the first CPU. 5. The first CPU constitutes a control processing system which is a main processing, and the second CPU is the first CPU.
The processor according to claim 1, wherein an intelligent processing system is configured to perform processing for backing up the control calculation in (3) and intelligent processing based on a database or sensor information. 6. The first CPU, the second CPU, the dual port RAM, the switch means and the control means are integrated into a single chip.
The processor according to the paragraph. 7. The invention as set forth in claim 6, wherein a plurality of said one-chip processors are connected to a common bus.
The processor according to the paragraph.