JPH0653509A - Insulated gate field effect semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE:To provide a novel structure for insulated gate field effect semiconductor device and simple fabrication process therefor. CONSTITUTION:In the structure of TFT, an anode oxide film 10 is formed of the same material as a gate electrode 8 around the gate electrode 8, an electrode 7 connected with the source, drain region 3 contacts the top face and side face of the source, drain region, and the electrode 7 connected with the source, drain extends above an oxide deposited around the gate electrode. Fabrication process of TFT requires only two masks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and is particularly applicable to a liquid crystal electro-optical device, a perfect contact type image sensor device and the like.

[0002]

2. Description of the Related Art Conventionally known insulating gate type field effect semiconductor devices are widely used in various fields. This semiconductor device is formed on a silicon substrate and is used as an IC or an LSI by functionally integrating a large number of semiconductor elements.

On the other hand, a thin film type insulating gate field effect semiconductor device (hereinafter referred to as TFT) formed by laminating thin films on a substrate other than a silicon substrate such as an insulating substrate is a liquid crystal electric It has begun to be actively used in a switching element portion of a pixel of an optical device, a driving circuit portion, a reading circuit portion of a contact image sensor, and the like.

Since this TFT is formed by laminating thin films on the insulating substrate by the vapor phase method as described above, it can be formed at a low production ambient temperature of about 500 ° C., which is inexpensive soda glass and borosilicate. Acid glass or the like can be used as the substrate.

As described above, a transistor can be easily manufactured on a large-area substrate because it can be manufactured on an inexpensive substrate and its maximum size is limited only to the size of an apparatus for forming a thin film by a vapor phase method. It has the advantage that it can be formed, and therefore, it is expected to be used for a liquid crystal electro-optical device having a matrix structure having a large number of pixels and a one-dimensional or two-dimensional image sensor, and it is partially realized.

A typical structure of this conventional TFT is schematically shown in FIG.

In FIG. 2, 1 is an insulating substrate made of glass, 2 is a thin film semiconductor made of an amorphous semiconductor, and 3 is a thin film semiconductor.
Is a source / drain region, 7 is a source / drain electrode, and 11 is a gate electrode.

In general, such a TFT is formed by first forming a semiconductor film on a substrate and then patterning the semiconductor region 2 in an island shape in a necessary portion using a first mask. Next, the gate insulating film 6 is formed, a gate electrode material is formed on the gate insulating film 6, and the gate electrode 11 and the gate insulating film 6 are patterned using the second mask. After that, the source and drain regions 3 are formed in the semiconductor region 2 in the self-alignment using the photoresist mask formed by the third mask and the gate electrode 11 as a mask. After that, the interlayer insulating film 4 is formed. Contact holes are formed in this interlayer insulating film using a fourth mask for electrode connection to the source / drain regions 3. After that, after the electrode material is formed, the electrode material is patterned by the fifth mask to form the electrode 7 to complete the TFT.

[0009]

As described above, the general TFT uses five masks, and the complementary TFT requires six masks. Naturally, when forming a complicated integrated circuit, more masks than this number are required. Using a large number of masks in this way requires complicated steps in the process of manufacturing a TFT element, and the number of mask alignments naturally increases. They are,
This causes a decrease in yield and productivity in manufacturing TFT elements. Furthermore, the size of electronic devices using TFT elements, the miniaturization of TFT elements themselves, and the miniaturization of patterns have been factors that further reduce these. Therefore TFT
In the fabrication process, a new T that reduces the number of masks required for TFT fabrication, a process that does not require complicated steps
The structure of FT was desired.

Therefore, the present invention relates to a novel structure and a simple manufacturing process of an insulating gate type field effect semiconductor device, and the number of masks is smaller than that of the conventional one.
The feature is that T can be produced.

[0011]

The TFT of the present invention is provided with an anodic oxide film around the gate electrode of the material forming the gate electrode, and the electrodes connected to the source and drain regions are the upper surfaces of the source and drain regions. And an electrode connected to the source and drain and extending over the oxide film provided around the gate electrode. Type semiconductor device.

That is, as shown in the schematic sectional view of the TFT of the present invention shown in FIG. 1, an anodic oxide film 10 is provided at least around the gate electrode 8, and the source and drain are provided from the end face of this anodic oxide film. The upper surface and the side surface of the region 3 are slightly protruded, and the electrode 7 is connected to the source / drain regions at the protruding portion, so that the connection area is large. Further, the electrode 7 extends to above the anodic oxide film 10 and is patterned at this portion to be separated into individual electrodes.

FIG. 3 schematically shows a process of manufacturing the TFT having the structure as shown in FIG. In the drawings described in the present specification, the schematic dimensions are shown for the sake of explanation, and the actual dimensions and shapes are slightly different. Hereinafter, an example of the manufacturing process of the TFT of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, a semiconductor layer 2 is formed on a glass substrate, for example, a crystallized glass 1 having heat resistance. As the silicon semiconductor layer, a wide variety of semiconductors such as an amorphous semiconductor and a polycrystalline semiconductor can be used. Further, as a forming method, a plasma CVD method, a sputtering method, a thermal CV method may be used depending on the type of semiconductor to be adopted.
The D method or the like can be selected. Here, the following steps will be described using a polycrystalline silicon semiconductor as an example.

Next, a silicon oxide film 6 to be a gate insulating film is formed on this semiconductor layer 2. Further, on this, aluminum is formed as an electrode material to be a gate electrode, here, as an electrode material. After that, the gate electrode 8 is patterned using the first mask. After that, the periphery of the gate electrode 8 is anodized in an electrolytic solution for anodic oxidation, so that the non-porous aluminum oxide 10 is at least around the gate electrode in the vicinity of the channel region.
To form.

As the solution used for this anodic oxidation, a strong acid solution such as sulfuric acid, nitric acid, phosphoric acid or the like, tartaric acid, a mixed acid obtained by mixing citric acid with ethylene glycol, propylene glycol or the like can be used. Also, if necessary,
It is also possible to mix a salt or alkaline solution in order to adjust the pH of this solution.

First, with respect to 1% of a 3% tartaric acid aqueous solution, 9
This substrate was dipped in an AGW electrolytic solution containing propylene glycol at a ratio of 1., an aluminum gate electrode was connected to an anode of a power source, and platinum was used as a cathode to apply a DC power.

The conditions for anodic oxidation are as follows. First, a current density of 3 mA / cm ² was applied for 20 minutes in a constant current mode, and then a constant voltage mode was applied for 5 minutes. Formed. When the insulating property of this aluminum oxide was examined using a sample produced under the same conditions as this oxidation treatment, an aluminum oxide film having a characteristic of 10 ¹⁵ Ω and a withstand voltage of 3 × 10 ⁶ V / cm. Met.

Further, when the surface of this sample was observed with a scanning electron microscope, the surface was magnified up to about 10,000 times and irregularities on the surface could be observed, but minute holes could not be observed.
It was a good insulating film.

Next, a silicon oxide film 12 is formed on this upper surface by a plasma CVD method, and from this state, an anisotropic etching process is carried out in a direction substantially perpendicular to the substrate, as shown in FIG.
As shown in (D), the silicon oxide 13 is left on the side wall of the convex portion formed by the gate electrode and the anodic oxide film. Next, with the remaining silicon oxide 13 and the convex gate electrode 8 and the anodic oxide film 10 as a mask, the semiconductor layer 2 thereunder is removed by etching by self-alignment. The state at this time is shown in FIG. The state of the upper surface at this time is shown in FIG.
Shown in. A cross section of AA 'in FIG. 4 is shown in FIG.

Next, from this state, the silicon oxide film 13 and the gate insulating film are selectively etched and removed using the gate electrode 8 and its anodic oxide film 10 as masks, and then, FIG. ), A part of the semiconductor layer 2 is exposed from the end of the gate electrode.

Next, the exposed portion is doped with impurities so as to form the source and drain regions. As shown in FIG. 3F, the gate anodic oxide film 10 is formed.
Is used as a mask, and phosphorus ions are ion-implanted from the upper surface of the substrate. In this way, the source / drain region 3 is formed. After that, for activation of the region, laser is irradiated to this portion, and the source and drain regions are activated by laser annealing. In addition to this, a thermal annealing process or the like can be adopted as the activation process.

Next, aluminum to be source and drain electrodes is formed on the upper surface, and the source and drain electrodes are etched into a predetermined pattern by using a second mask to divide the source and drain electrodes. . This state is shown in FIG. Finally, by using the source and drain electrodes 7 and the anodic oxide film 10 of the gate electrode as a mask, the semiconductor layer 2 which surrounds the periphery is removed by etching, and the TFT as shown in FIGS. 3 (G) and 4 (D) is formed. To complete. As described above, according to the present invention, it becomes possible to manufacture a TFT with only two masks. When the TFT has a complementary structure, it can be achieved by adding one or two masks.

The external connection to the gate electrode is performed by forming an anodic oxide film so that a part of the gate electrode does not come into contact with the anodizing electrolyte during the anodizing process, or by forming the last unnecessary semiconductor. After etching the layers, the source and drain electrodes and the anodic oxide film are selectively etched to remove the anodic oxide film exposed to the outside, whereby connection can be established. Of course, it is also possible to form a contact hole in a specific anodic oxide film for connection using the third mask.

In the above description, the manufacturing process of the TFT described above is an example, and it is not limited to the manufacturing process shown in this description. For example, the doping process of impurities in the source and drain regions is performed as described above. In the description, as shown in FIG. 3F, it is performed after the patterning of the semiconductor layer 2. However, in the state of FIG. 3B, it is possible to perform the ion implantation process using the anodic oxide film 10 of the gate as a mask. .

In the step after the semiconductor layer 2 is formed and before the gate electrode is formed, a photomask is newly used,
When the semiconductor layer is patterned in an island shape only in the vicinity of the TFT region, as shown in FIG. 5, the semiconductor layer 2 does not exist below the lead wiring portion of the gate electrode, and only the substrate or the insulating film on the substrate exists. , It is possible not to configure the gate electrode wiring and the capacitor in this portion. With this configuration, a TFT capable of responding at a higher speed can be manufactured by using three masks. This state is shown in FIG.
FIG. 5A shows a top view thereof, and FIG. 5B shows a BB ′ cross section of the top view.

[0027]

[Embodiment 1] In this embodiment, an example in which the TFT of the present invention is applied to an active matrix type liquid crystal electro-optical device having a circuit configuration as shown in FIG. 6 is shown. As is apparent from FIG. 6, the active element of this embodiment has a complementary structure, and the PTFT is applied to one pixel electrode.
And NTFT are provided. FIG. 8 shows an actual arrangement configuration of electrodes and the like corresponding to this circuit configuration. In order to simplify the description, only the part corresponding to 2 × 2 is shown.

First, a method of manufacturing a substrate for a liquid crystal electro-optical device used in this embodiment will be described with reference to FIGS. Figure 7
In (A), a silicon oxide film as a blocking layer 51 is formed on a glass 50, such as quartz glass, which can withstand a heat treatment at 700 ° C. or less, for example, about 600 ° C.
It is made to a thickness of 0Å. The process conditions were an atmosphere of 100% oxygen, a film forming temperature of 15 ° C., an output of 400 to 800 W, and a pressure of 0.5 Pa. The film formation rate using quartz or single crystal silicon for the target was 30 to 100 Å / min.

A silicon film 52 was formed thereon by LPCVD (Low Pressure Vapor Phase) method, sputtering method or plasma CVD method. When forming by a reduced pressure vapor phase method, it is 450 to 550 ° C., which is 100 to 200 ° C. lower than the crystallization temperature, for example, 53.
Disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) was added to C at 0 ° C.
The film was supplied to the VD apparatus to form a film. The reactor pressure is 30 to 3
It was set to 00 Pa. The film forming rate was 50 to 250 Å / min. In order to control the threshold voltage (Vth) of the PTFT and the NTFT to be approximately the same, boron may be added during film formation using diborane at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁸ cm ^-3. .

When the sputtering method is used, the back pressure before the sputtering is set to 1 × 10 ^-5 Pa or less, the single crystal silicon is used as the target, and the argon is mixed with hydrogen in an amount of 20 to 80%. For example, argon is 20% and hydrogen is 80%.
The film forming temperature was 150 ° C., the frequency was 13.56 MHz, the sputter output was 400 to 800 W, and the pressure was 0.5 Pa.

When a silicon film is formed by the plasma CVD method, the temperature is, for example, 300 ° C., and monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ) is used. These were introduced into a PCVD apparatus, and high-frequency power of 13.56 MHz was applied to form a film.

The coating formed by these methods is
5 × 10 oxygen^{twenty one}cm^-3The following is preferable. This acid
When the elemental concentration is high, it is difficult to crystallize and the thermal annealing temperature is
Higher or longer thermal anneal times must be provided.
If it is too small, the backlight will turn off the light.
The current will increase. Therefore 4 × 10¹⁹~ 4 x 10 ^{twenty one}
cm^-3And the range. 4 × 10 for hydrogen²⁰cm^-3And silicon 4
× 10^{twenty two}cm^-3Was 1 atom%. Also,
To promote crystallization of the source and drain
Therefore, the oxygen concentration is 7 × 10¹⁹cm^-3Below, preferably 1 × 10¹⁹
cm^-3The following is to form the channel of the TFT that makes up the pixel
5 × 10 oxygen only in the region by ion implantation²⁰~ 5 x 10
^{twenty one}cm^-3You may add so that it may become. Then the peripheral circuit
This TFT does not emit light because it does not emit light.
With less carrier and higher carrier mobility
Squeezing is effective in accumulating high frequency operation.
It

By the above method, a silicon film in an amorphous state is formed to a thickness of 500 to 3000 Å, for example 1500 Å, and then a heat treatment at a medium temperature in a non-oxide atmosphere at a temperature of 450 to 700 ° C. for 12 to 70 hours, For example, it was held at a temperature of 600 ° C. in a hydrogen atmosphere. Since the amorphous silicon oxide film is formed on the surface of the substrate below the silicon film, no specific nuclei are present in this heat treatment, and the whole is uniformly annealed. That is, it has an amorphous structure at the time of film formation, and hydrogen is simply mixed therein.

The annealing causes the silicon film to shift from an amorphous structure to a highly ordered state, and a part of the silicon film exhibits a crystalline state, and the mobility of carriers that can be obtained is hole mobility (μh) = 1.
0-200 cm ² / VSec, electron mobility (μe) = 15
˜300 cm ² / VSec is obtained.

In FIG. 7 (A), the silicon film is photoetched using a first photomask, and a region 30 for PTFT (channel width 20 μm) is shown on the left side of the drawing and NTFT.
A region 40 for the was prepared on the right side.

A silicon oxide film is formed thereon as a gate insulating film 53 to a thickness of 500 to 2000Å, for example 700Å. This is the same condition as the production of the silicon oxide film 51 as the blocking layer. Add a small amount of fluorine during this film formation,
You may fix sodium ion. Further, in this embodiment, a silicon nitride film 54 of 50 to 200 Å, for example 100 Å, is formed on the silicon oxide film as a blocking layer having a function of suppressing the reaction between the gate electrode formed on the upper surface and the gate insulating film.

After that, as a material for the gate electrode, aluminum 30 is formed on the upper side by a known sputtering method.
The thickness is from 00Å to 1.5 μm, for example, 1 μm. As the gate electrode material, molybdenum (Mo), tungsten (W), titanium (Ti), tantalum (Ta), an alloy in which silicon is mixed with these materials, a laminated wiring of silicon and a metal film, or the like is used in addition to aluminum. can do.

When a metal material is used as the gate electrode as in the present embodiment, particularly when a low resistance material such as aluminum is used, a gate delay (voltage propagating through the gate wiring) caused by a large area and high definition of the substrate is obtained. It is possible to suppress an increase in pulse delay and waveform distortion, and it is possible to easily increase the area of the substrate.

This was patterned with a second photomask to obtain FIG. 7 (B). Gate electrode 5 for PTFT
5, the gate electrode 56 for NTFT was formed. All of these gate electrodes are connected to the same gate wiring 57.

Next, the substrate was mixed with 1% of a 3% tartaric acid aqueous solution and propylene glycol was added at a ratio of 9 to AG.
It was dipped in a W electrolytic solution, an aluminum gate electrode was connected to an anode of a power source, and platinum was used as a cathode to apply a DC power. At this time, the gate electrodes are connected to each gate wiring, but the connection terminals are provided so that all the gate wirings are sandwiched and connected in the vicinity of the end portion of the substrate, and anodic oxidation is performed, as shown in FIG. 7C. Anodic oxide films 58 and 59 were formed around the gate electrode.

The anodization conditions were as follows: a constant current mode was applied for 20 minutes at a current density of 4 mA / cm ² , followed by a constant voltage mode for 15 minutes, and 2500 Å-thick aluminum oxide was applied around the gate electrode. Formed. It is better to form this anodic oxide film as thick as possible, and as thick as process conditions permit.

Next, as shown in FIG. 7D, after the nitride film 54 and the silicon oxide film 53 on the semiconductor are removed by etching, 1 to 5 × boron is added as impurities for PTFT to the entire surface of the substrate.
It was added by the ion implantation method at a dose amount of 10 ¹⁵ cm ^-2 .
The source 60 and the drain 61 of the PTFT are formed with the doping concentration of about 10 ¹⁹ cm ^-3 . In this embodiment, ion doping was performed after removing the insulating film on the surface,
If the conditions of ion implantation are changed, it is possible to dope through the insulating films 53 and 54 on the semiconductor film.

Next, as shown in FIG. 7E, the photoresist 6 is used.
1 is formed using a third photomask to cover the PTFT region, and then phosphorus is ionized at a dose amount of 1 to 5 × 10 ¹⁵ cm ^-2 to the source 62 drain 63 for NTFT. It was added by the injection method so that the dope concentration was about 10 ²⁰ cm ^-3 . In the ion doping process as described above, the ion implantation direction is inclined with respect to the substrate so that the impurities wrap around in the direction below the anodic oxide film around the gate electrode so that the ends of the source and drain regions are gated. It was set so as to roughly match the electrode walkway. This allows
For the electrode wiring where the anodic oxide film will be formed in a later step,
Since it has a sufficient insulating action, it is not necessary to form a new insulating film.

Next, heating and annealing were performed again at 600 ° C. for 10 to 50 hours to activate the impurity regions. P
The source 60 and the drain 61 of the TFT, the source 62 and the drain 63 of the NTFT are prepared as P ⁺ and N ⁺ by activating impurities. Channel forming regions 64 and 65 are formed below the gate electrodes 55 and 56. In this embodiment, thermal activation is used as the activation treatment, but other than this method, a method of irradiating the source and drain regions with laser light to perform activation treatment can also be employed. In this case, since the activation process is performed instantaneously, it is not necessary to consider the diffusion of the metal material used for the gate electrode, and the function of blocking on the gate insulating film adopted in this embodiment is used. It is also possible to omit the silicon nitride film 54.

Next, an insulating film was formed on this upper surface as a silicon oxide film by the above-mentioned sputtering method. The thickness of this film is as thick as possible, for example, 0.5 to 2.0 μm. In this embodiment, it is formed to a thickness of 1.2 μm, and then anisotropic etching is performed from the upper surface to form a gate electrode and an anodic oxide film. A residual region 66 is formed near the side wall of the formed convex portion. This is shown in FIG. 7 (F).

Next, using this convex portion and the residual region 66 as a mask, unnecessary portions of the semiconductor film 52 are removed by etching to remove the residual region 66 existing around the convex portion, and the convex portion is removed. The semiconductor film 52 to be the source and drain regions of each TFT was exposed to the outside. This state is shown in FIG.

Further, aluminum is formed on the whole by sputtering, and the leads 67, 68 and the contact portions 69, 70 are patterned by the fourth mask, and then the electrodes 67, 68, 69, 70 and the gate electrodes. 55 and 56 and the semiconductor film overlying the anodic oxide films 58 and 59 around them are removed by etching, and complete element isolation is performed to complete the TFT. With such a manufacturing method, a TFT having a complementary structure could be manufactured with four masks. This state is shown in FIG.

In this TFT, the periphery of the gate electrode is wrapped with an anodic oxide film, and the source and drain regions protrude from the gate electrode portion only at the electrode connection portion, but the other portions are all under the gate electrode. Also the source,
The drain electrode is a source / drain region, and has 2
The contacts are in place, ensuring a good ohmic connection.

In this way, the C / TFT can be manufactured without applying a temperature above 700 ° C. in all steps even though it is a self-aligned method. Therefore, it is not necessary to use an expensive substrate such as quartz as the substrate material, and the process is extremely suitable for the liquid crystal electro-optical device having a large pixel of the present invention.

In this embodiment, the thermal anneal is as shown in FIG.
(E) performed twice. However, the anneal of FIG. 7 (A) may be omitted depending on the desired characteristics, and both may be combined with the anneal of FIG. 7 (E) to reduce the manufacturing time. Further, although aluminum is used as the gate electrode in the present embodiment, since the silicon nitride film 54 is provided thereunder, the aluminum does not react with the gate insulating film below, and good interface characteristics are realized. I was able to.

Next, as shown in FIG. 7 (I), two TFTs have a complementary structure, and the output terminal thereof is connected to the electrode of one pixel of the liquid crystal device as a transparent electrode. -Tin oxide film) was formed. It was etched with a fifth photomask to form the pixel electrode 71. This ITO is room temperature to 1
The film was formed at 50 ° C., and was accomplished by oxygen at 200 to 400 ° C. or an anneal in the atmosphere. Thus PTFT
30, the NTFT 40, and the transparent conductive film electrode 71 were formed on the same glass substrate 50. The electric characteristics of the obtained TFT are PTFT, mobility is 20 (cm ² / Vs), and Vth is −
5.9 (V), NTFT has a mobility of 40 (cm ² / Vs),
Vth was 5.0 (V).

FIG. 8 shows how the electrodes and the like of this liquid crystal electro-optical device are arranged. The cross section taken along the line CC ′ of FIG. 8 corresponds to the cross section of the manufacturing process of FIG. 7. The PTFT 30 is provided at the intersection of the first signal line 72 and the third signal line 57, and the PTFT for another pixel is also provided at the intersection of the first signal line 72 and the third signal line 76 on the right side. Are similarly provided. On the other hand NTF
T is provided at the intersection of the second signal line 75 and the third signal line 57. In addition, another adjacent first signal line 74
At the intersection of the third signal line 57 with the PT for another pixel.
FT is provided. A matrix structure using such C / TFT is provided. The PTFT 30 is connected to the first signal line 72 by the electrode of the drain 61, and is connected to the gate 5
5 is connected to the signal line 57. The output end of the source 60 is connected to the pixel electrode 71 via a contact.

On the other hand, the NTFT 40 is connected to the second signal line 73 by the electrode of the source 62, and the gate 56 is connected to the signal line 57.
The output terminal of the drain 63 is connected to the PTF via the contact.
Like T, it is connected to the pixel electrode 71. In addition, another C connected to the same third signal line and provided next to it
As for / TFT, PTFT31 is connected to the first signal line 74 by NTFT
41 is connected to the second signal line 75. Thus, one pixel 80 is constituted by the pixel electrode 71 made of a transparent conductive film and the C / TFT between the pair of signal lines 72 and 73 (inside). By repeating such a structure horizontally and vertically, a 2 × 2 matrix can be made into a large pixel liquid crystal electro-optical device such as 640 × 480 or 1280 × 960. Note that the impurity regions of the TFT are called source and drain here for the purpose of explanation, and when actually driven, the function may be different from the name.

In this embodiment, the semiconductor film 52 is formed as the first film.
Using the photo mask of
The elements of each TFT are separated. As a result, the semiconductor film does not exist below the gate wiring other than the area of the TFT, and the portion of the gate wiring is the substrate or the insulating film on the substrate, and the capacitance on the gate input side should be formed in this portion. Therefore, high-speed response is possible.

A liquid crystal electro-optical device is manufactured using the substrate provided with the active element thus manufactured. First, a resin in which 50% by weight of a nematic liquid crystal was dispersed in an epoxy modified acrylic resin having ultraviolet curing characteristics was formed on this substrate by a screen method.

The mesh density of the screen used was 125 mesh per inch, and the emulsion thickness was 15 μm.
And The squeegee pressure was 1.5 kg / cm ² .

Then, after leveling for 10 minutes, 236 nm.
With a high-pressure mercury lamp with an emission wavelength centered on
Applying energy of 000mJ to cure the resin, 12
A light control layer having a thickness of μm was formed.

After that, by using the DC sputtering method, Mo
(Molybdenum) was formed into a 2500 Å film to form a second electrode.

Thereafter, a black epoxy resin is printed by using a screen method, and after calcination at 50 ° C. for 30 minutes,
Main baking was performed at 180 ° C. for 30 minutes to form a protective film of 50 μm.

A TAB-shaped drive IC was connected to the leads on the substrate to complete a reflective liquid crystal display device composed of only one substrate. In this embodiment, one set of complementary structure TFTs is provided for each pixel as an active element, but the invention is not particularly limited to this structure, and a plurality of sets of complementary structure TFTs may be provided. A set of complementary TFTs may be provided on a plurality of divided pixel electrodes.

In this way, the liquid crystal electro-optical device in which the active element is provided in the dispersion type liquid crystal is completed. Since the dispersion type liquid crystal of the present embodiment requires only one substrate, a light and thin liquid crystal electro-optical device can be realized at a low cost, a deflecting plate is not used, and an alignment film is not required. Since the liquid crystal electro-optical effect can be realized with only the substrate, a very bright liquid crystal electro-optical device could be realized.

[Embodiment 2] In this embodiment, the present invention is applied to a liquid crystal electro-optical device in which a modified transfer gate TFT having a complementary structure is provided for one pixel as shown in FIG. The manufacture of the TFT in this embodiment is basically the same as that of the first embodiment, and the process proceeds in substantially the same way as in FIG. However, since the modified transfer gate C / TFT is adopted in this embodiment, the arrangement is different from that in FIG. 7, and the actual arrangement is in the position shown in FIG.
Ts are arranged and connected.

As shown in FIG. 9, a common gate wiring 91
The gates of the PTFT 95 and the NTFT 96 are connected to each other by connecting the source and drain regions to the other signal line 93, and the other source and drain regions are also commonly connected to the pixel electrode. .

The steps similar to those in Example 1 are performed until step (G) in FIG. Next, a silicon nitride film 100 having a thickness of 500 to 2000 Å is formed on the upper surfaces of these. Next, this silicon nitride film 100 is anisotropically etched in the direction perpendicular to the substrate to leave this silicon nitride film on the side wall of the anodic oxide film 101 of the gate. At this time, it is not necessary that the silicon nitride film 100 is left uniformly on the side wall, and it is sufficient that it is left at least in the gate insulating film portion where the gate electrode 107 and the semiconductor are close to each other.
In the subsequent process, when the source and drain electrodes 102 are formed, the metal wiring 1 is formed near the edge of the gate insulating film 103.
02 and the source / drain regions 104 and 105 are prevented from being short-circuited.

Next, an interlayer insulating film and a silicon oxide film 1 are formed on this upper surface.
06 is formed at 1000 Å to 2 μm, and 6000 Å here. After forming a photoresist on the upper surface, light is exposed from the substrate to form a mask on the gate electrode 107 using the gate electrode as a mask, and an etching process is performed to form an interlayer insulating film 106 on the gate electrode.

After this, the steps of FIGS. 7H and 7I are advanced to complete a modified transfer gate TFT having the arrangement and structure shown in FIGS. 10A, 10B and 10C. . The interphase insulating film 106 is formed. FIG. 10 (B),
As is clear from (C), the interlayer insulating film 106 is always present on the gate electrode 107, and the lead portion of the gate wiring 107 and the lead portion of the source / drain wiring 102 as shown in FIG. A sufficient interlayer insulating function was exhibited at the intersection, and generation of wiring capacitance at this intersection could be suppressed.

As described above, in this embodiment, the first embodiment is used.
With the same number of masks, there is less capacitance near the wiring,
Less chance of short circuit near gate insulation film,
An active element substrate having a TFT having an element structure could be completed.

Using this substrate as a first substrate and a second substrate having a counter electrode and an alignment treatment layer formed on a counter substrate, STN type liquid crystal is injected between the substrates by a well-known bonding technique. As a result, an active matrix STN liquid crystal electro-optical device was completed.

Although all of the above examples have been applied to the liquid crystal electro-optical device, the present invention is not limited to this example, and it goes without saying that the present invention can be applied to other devices, three-dimensional integrated circuit elements and the like. Yes.

With the structure of the present invention, it becomes possible to manufacture a TFT element using a mask of a very small number as compared with the conventional one. When a semiconductor product is manufactured by applying the element of this structure, the manufacturing process can be simplified and the manufacturing yield can be improved with the decrease in the number of masks, and the semiconductor application device with a lower manufacturing cost can be provided. We were able to.

According to the present invention, a metal material is used as the gate electrode material, and an oxide film of this metal material by an anodic oxidation method is provided on the surface thereof, and three-dimensional wiring having a three-dimensional intersection is provided thereon. Is characterized by. Further, the gate electrode and the oxide film around the electrode are provided so that only the contact portions of the source / drain are exposed from the gate electrode to bring the feeding point closer to the channel, thereby lowering the frequency characteristics of the device and increasing the ON resistance. I was able to prevent it.

Further, in the present invention, when aluminum is used for the gate electrode, hydrogen in the gate oxide film can be reduced to H ₂ → H by the catalytic effect of aluminum during annealing in the element forming process, and further reduced. As a result, the interface state density (Q _SS ) can be reduced and the device characteristics can be improved as compared with the case where a silicon gate is used.

Further, since the source and drain regions of the TFT are self-aligned, and the contact portions of the electrodes for supplying power to the source and drain regions are also determined by self-alignment, the area of the element required for the TFT is reduced and the integration degree is reduced. Can be improved. Moreover, when used as an active element of a liquid crystal electro-optical device, the aperture ratio of the liquid crystal panel could be increased.

Further, a TFT having a characteristic structure is proposed by positively utilizing the anodic oxide film at the top of the gate electrode, and the number of masks for manufacturing this TFT is at least two, which is a very small number of masks. We were able to.

[Brief description of drawings]

FIG. 1 shows an example of a device structure of a TFT of the present invention.

FIG. 2 shows a device structure of a conventional TFT.

FIG. 3 shows a schematic cross-sectional view of the manufacturing process of the TFT of the present invention.

FIG. 4 shows a top view of a manufacturing process of a TFT of the present invention.

FIG. 5 shows another example of the TFT of the present invention.

FIG. 6 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 7 is a schematic sectional view of a manufacturing process when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 8 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 9 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 10 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

[Explanation of symbols]

 1 ... Substrate 2 ... Semiconductor layer 3 ... Source / drain region 6 ... Gate insulating film 7 ... Source / drain electrode 8 ... Gate electrode 10 ... Anodized film 13 ... Remaining region 55 ... Gate electrode 56 ... Gate electrode 60 ... Source 61 ... Drain 62 ... Source 63 ... Drain 66 ... Remaining region 71 ...・ Pixel electrode

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[Procedure amendment]

[Submission date] May 19, 1992

[Procedure 3]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 shows an example of a device structure of a TFT of the present invention.

FIG. 2 shows a device structure of a conventional TFT.

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the TFT of the present invention.

FIG. 4 is a schematic cross-sectional view of the manufacturing process of the TFT of the present invention.

FIG. 5 is a top view of the manufacturing process of the TFT of the present invention.

FIG. 6 is a top view of the manufacturing process of the TFT of the present invention.

FIG. 7 shows another example of the TFT of the present invention.

FIG. 8 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 9 is a schematic cross-sectional view of a manufacturing process when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 10 is a schematic cross-sectional view of a manufacturing process when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 11 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 12 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 13 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

[Explanation of reference numerals] 1 ... substrate 2 semiconductor layer 3 source / drain region 6 gate insulating film 7 source / drain electrode 8 gate Electrode 10 ... Anodic oxide film 13 ... Residual region 55 ... Gate electrode 56 ... Gate electrode 60 ... Source 61 ... Drain 62 ... Source 63 ... Drain 66 ... Remaining area 71 ... Pixel electrode

[Procedure amendment]

[Submission date] May 19, 1992

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

[Figure 10]

FIG. 11

[Fig. 12]

[Fig. 13] ─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 24, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 shows an example of a device structure of a TFT of the present invention.

FIG. 2 shows a device structure of a conventional TFT.

FIG. 3 is a schematic cross-sectional view of the manufacturing process of the TFT of the present invention.

FIG. 4 is a schematic cross-sectional view of the manufacturing process of the TFT of the present invention.

FIG. 5 is a top view of the manufacturing process of the TFT of the present invention.

FIG. 6 is a top view of the manufacturing process of the TFT of the present invention.

FIG. 7 shows another example of the TFT of the present invention.

FIG. 8 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 9 is a schematic cross-sectional view of a manufacturing process when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 10 is a schematic cross-sectional view of a manufacturing process when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 11 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 12 is a schematic diagram of a circuit when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

FIG. 13 is a schematic view showing a state of arrangement on a substrate when the TFT of the present invention is applied to a liquid crystal electro-optical device as a complementary type.

[Explanation of reference numerals] 1 ... substrate 2 semiconductor layer 3 source / drain region 6 gate insulating film 7 source / drain electrode 8 gate Electrode 10 ... Anodic oxide film 13 ... Residual region 55 ... Gate electrode 56 ... Gate electrode 60 ... Source 61 ... Drain 62 ... Source 63 ... Drain 66 ... Remaining area 71 ... Pixel electrode

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

[Figure 4]

[Figure 5]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

[Figure 10]

FIG. 11

[Fig. 13]

[Fig. 12]

Claims (8)

[Claims] 1. An insulated gate type field effect semiconductor device provided on a substrate, wherein an insulating film of a material forming a gate electrode is provided around the gate electrode, and electrodes connected to the source and drain regions are provided. The electrode is in contact with the upper surface and the side surface of the source / drain region, and the electrode connected to the source / drain extends over the insulating film provided around the gate electrode. Insulated gate type field effect semiconductor device. 2. An insulating gate type field effect semiconductor device provided on a substrate, wherein an aluminum anodic oxide film forming a gate electrode is provided around the gate electrode, and the aluminum is connected to the source and drain regions. The electrodes are in contact with the upper and side surfaces of the source and drain regions, and the semiconductor layer provided below the gate electrode is only the upper and side surfaces where the aluminum electrodes are connected to the end surfaces of the gate electrode and the anodic oxide film. Insulated gate type field effect semiconductor device characterized by being protruded. 3. A step of forming a semiconductor film on a substrate having an insulating surface, a step of forming a gate insulating film on the semiconductor film, and a step of forming a gate electrode on the gate insulating film and using a mask to form a gate. A step of processing the electrode into a predetermined pattern, a step of anodizing the gate electrode after the step to form an anodic oxide film at least around the gate electrode near the channel formation region, and a step of forming an anodic oxide film on the anodic oxide film. Forming a coating on the surface of the anodic oxide film and the gate electrode by anisotropic etching to leave the coating near the sidewall of the convex portion, and masking the remaining region and the convex portion. As a step of etching away the gate insulating film and the semiconductor film, and exposing the semiconductor film to the outside of the convex portion by etching away the remaining region. A step, and a source after contacting the exposed semiconductor film, forming a film for the electrode for the drain region, using a mask, patterning the film for the electrode and extending on the anodic oxide film source, A method of manufacturing an insulating gate type semiconductor device, comprising a step of forming a drain electrode as part of its manufacturing process. 4. A step of forming a semiconductor film on a substrate having an insulating surface, a step of patterning the semiconductor film in a predetermined region into an island shape using a mask, and a gate insulating film on the semiconductor film. A step of forming a gate electrode on the gate insulating film and processing the gate electrode into a predetermined pattern using a mask; and anodizing the gate electrode after the step to form at least a channel formation region. By the process of forming an anodic oxide film around the neighboring gate electrode and the anisotropic etching process of forming a film on the anodic oxide film, the sidewall of the convex portion formed by the anodic oxide film and the gate electrode is formed. A step of leaving the film in the vicinity thereof; a step of etching away the gate insulating film and the semiconductor film using the remaining area and the convex portion as a mask; Exposing the semiconductor film to the outside of the convex portion by removing by etching,
After forming an electrode film for the source and drain regions in contact with the exposed semiconductor film, the electrode film is patterned using a mask and divided into source and drain electrodes on the anodic oxide film. And a manufacturing process as part of the manufacturing process. 5. A step of doping the source and drain regions with an impurity after etching the semiconductor film so as to be exposed from the convex portion by using the convex portion and the remaining region as a mask. A method for manufacturing an insulating gate type field effect semiconductor device according to claim 3. 6. The method further comprises the step of doping the source and drain regions with an impurity after etching the semiconductor film so as to be exposed from the convex portion using the convex portion and the remaining region as a mask. The method for manufacturing an insulating gate type field effect semiconductor device according to claim 4. 7. The insulating gate according to claim 3, further comprising a step of doping an impurity into a region not covered with the anodic oxide film after the step of forming an anodic oxide film around the gate electrode. Type field effect semiconductor device manufacturing method. 8. The insulating gate according to claim 4, further comprising a step of doping an impurity into a region not covered with the anodic oxide film after the step of forming an anodic oxide film around the gate electrode. Type field effect semiconductor device manufacturing method.