JPH0652259A - Scan inserting method - Google Patents

Abstract

PURPOSE:To provide the scan inserting method which can generate function description language of a logic circuit having a scan by only logic of an ordinary circuit. CONSTITUTION:In a first step 102, a register (flip-flop) sentence in function description language is retrieved. In a second step 104, a truth value table of its retrieved register circuit is generated. In a third step 107, it is decided whether a holding signal exists or not based on the truth value table generated in a second step. In fourth steps 108, 109, a description part for outputting a signal from a combination circuit is converted so that a signal from the register circuit of the pre-stage is output at the time of shift, and a signal from the combination circuit is outputted as it is at the time other than shift.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scan insertion method, and more particularly, to a scan insertion method when performing logic design using a function description language.

[0002]

2. Description of the Related Art Generally, an LSI used in an information processing device uses a register (flip-flop) circuit for holding past inputs. However, L in recent years
Since the integration density of SI increases sharply from the number of pins, the circuit becomes large, and the logical depth becomes deep, a huge length of pattern is required to check the operation, and the creation of the pattern is a heavy burden. Has become. In addition, if the pattern is long, the operation of the entire circuit cannot be completely checked, and the fault detection rate (how many faults the signal line value is fixed to "0" or "1" in the created pattern is found. There is a problem that it does not rise.

In order to solve the problem, a path (scan) in which register (flip-flop) circuits are serially connected is provided in the LSI circuit in addition to the normal circuit, so that all the register (flip-flop) circuits are integrated. It can be regarded as one shift register. Then, when the selector added to the input part of each register (flip-flop) circuit is in the shift mode, the value can be directly set inside the circuit by using the shift operation, and the value inside the circuit can be directly observed. Has been. As a result, the register (flip-flop) circuit in the path has a similar fault detection rate as the external terminal.

FIG. 2 shows a simplified example of a circuit including a scan. In FIG. 2, the combinational circuit 201 is
The output is determined by the state of the input at that time and the combination of the internal gates. The sequential circuit 202 includes a memory circuit, the output of which receives the state of past inputs,
The output is determined by the state of the input at that time and the past, and here it is assumed to be a flip-flop circuit. Reference numeral 203 is a normal input terminal, 204 is a scan input terminal, and 205 is a switching input between the scan mode and the normal mode. Further, 206 is a scan clock (also usable as a normal clock), 207 is a scan output terminal,
Reference numeral 208 is a normal output terminal. Scan input terminal 20
The path output from 4 to the scan output terminal 207 via each register (flip-flop) circuit is a scan.

As described above, since the degree of integration has risen sharply, not only the pattern but also the logic circuit is heavily burdened. At present, there is a method of creating a function description language from a function specification and creating a logic circuit, which includes VHDL (VHSIC Hardware Description Langu).
age) and FDL (Function Description Language). Regarding the FDL, the reference name "FDL: AS
tructural Behavior Description Language "(1983 6
th International Symposium on Computer Hardware De
There is a scription Language page 137-152).

[0006]

In the conventional scan insertion method, when a logic circuit having a scan as shown in FIG. 2 is created by using a functional description language, the functional description language is manually created, so that the normal circuit is used. Since the description must be made in consideration of the logic of the above and the logic of the scan, there are disadvantages that the number of description errors is larger than that in the case of only the normal circuit, and that it takes man-hours.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a scan insertion method which solves the above drawbacks and can create a functional description language of a logic circuit having a scan only by the logic of a normal circuit.

[0008]

According to the scan insertion method of the present invention, a register (flip-flop) in a function description language is used.
A first step of searching a sentence; a second step of creating a truth table of the searched register circuit;
The third step of judging whether or not the hold signal is held based on the truth table created in the step of 1. and the description part for outputting the signal from the combination circuit is shifted from the register circuit of the previous stage when shifting. It is composed of a fourth step of outputting a signal and converting it so as to output a signal from the combination circuit as it is, except at the time of shifting.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.
FIG. 1 is a flow chart showing an embodiment of the present invention.
Reference numeral 101 is a function description language described without considering scanning. 102 is the first step of inputting the function description language 101 and searching for a register (flip-flop) statement. 104 is a second step of inputting the register (flip-flop) statement 103 retrieved in the first step 102 and creating a truth table 105.

Reference numeral 107 is a third step of judging whether or not there is a hold signal based on the truth table 105 created in the second step 104.

If there is a hold signal, the first data conversion processing 108 is executed, and the description portion for outputting the signal from the combinational circuit is maintained at the previous value in the hold mode and shifted in the modes other than the hold mode. In the mode, the signal from the previous register (flip-flop) is output. When the mode is other than the hold mode and the shift mode, the signal from the combinational circuit is converted so as to be output, and the process returns to the first step 102 to search for the next register (flip-flop) statement.

When there is no hold signal, the second data conversion processing 109 is executed, and the description portion for outputting the signal from the combinational circuit is changed to the signal from the previous register (flip-flop) circuit in the shift mode. Output. Further, in the case other than the shift mode, the first step 10 is performed in order to convert the signal from the combinational circuit so that the signal is output and to retrieve the next register (flip-flop) statement.
Return to 2. First and second data conversion processing 108, 10
9 functions as the fourth step.

After returning to the first step 102, if there is no register (flip-flop) statement which has not been converted, the function description language 110 in which the scan is inserted is output and the processing is ended.

Next, a simple example of implementing the present invention will be given, and a more specific description will be tried using FDL.

Of the sequential circuit 202 of FIG. 2, the flip-flop circuit AAA. BBB. FD without CCC scan
When described in L, it becomes as shown in Table 1 below.

[0016]

[Table 1]

First, the description sentences from "REG AAA" to "NOC;" which are the description sentences of the flip-flop circuit AAA are retrieved (first step 102 in FIG. 1). By inputting this, a truth table as shown in FIG. 3A is created (second in FIG. 1).
Step 104). It is judged from the truth table of FIG. 3A that there is no hold signal (the third step 10 of FIG. 1).
7) When the signal "INAAA" from the combinational circuit is in the shift mode, that is, when "SMC" in FIG. 2 is positive, the signal from the previous flip-flop circuit (in this case, "INA" in FIG.
SIN ") is output, and is converted so as to output the signal" INAAA "(FIG. 2) from the combinational circuit except in the shift mode (fourth step in FIG. 1).

Next, the next flip-flop circuit BBB is searched and similarly converted. When all the conversions are completed, the FDL shown in Table 2 below is output, and the flip-flop circuits AAA, BBB, CCC in FIG. 2 can be created without describing the scan logic.

[0019]

[Table 2]

Although FDL is used as an example in the above description, the same effect can be obtained with other function description languages without being limited to FDL, and the object of the present invention can be achieved.

[0021]

As described above, according to the scan insertion method of the present invention, it is sufficient to create a function description language having only the logic of a normal circuit, and the scan logic is not necessary, so that the description error of the function description language is reduced. It is also possible to obtain the effect that the number of steps can be reduced.

[Brief description of drawings]

FIG. 1 is a flow chart for explaining the operation of an embodiment of the present invention.

FIG. 2 is a diagram showing a simplified example of a circuit including a scan to which the present invention is applied.

FIG. 3 is a diagram showing an example of a truth table created by inputting a register statement in a function description language according to the present invention.

[Explanation of symbols]

 201 combinational circuit 202 register (flip-flop) circuit 203 normal circuit input terminal 204 scan input terminal 205 normal / shift mode switching input 206 scan clock (shared with normal clock) 207 scan output terminal 208 normal output Terminal

Claims (1)

[Claims] 1. A first step of retrieving a register (flip-flop) statement in a function description language, and a second step of creating a truth table of the retrieved register circuit.
Step, a third step of judging whether or not a hold signal is held based on the truth table created in the second step, and a description part for outputting a signal from the combinational circuit is shifted. And a fourth step of outputting the signal from the register circuit at the preceding stage and converting the signal so that it outputs the signal from the combination circuit as it is, except at the time of shifting.