JPH0651813A - A/d conversion unit - Google Patents

Abstract

PURPOSE:To use a sequencer for selecting eggs or fruits. CONSTITUTION:Data for selection are received from a programmable controller, several areas are set in all the conversion value areas corresponding to those data, and it is selected which group an arbitrary analog input belongs to. One part of the selection processing of eggs or fruits is performed by the A/D conversion unit in place of the sequencer. Thus, scan time is shortened by shortening the sequence program, and the selection of eggs or fruits can be performed by using the sequencer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D conversion unit used when analog data is taken in by a programmable controller (hereinafter referred to as a sequencer) which sequentially controls the operation of a load device.

[0002]

2. Description of the Related Art FIG. 8 shows the configuration of an A / D conversion unit used when analog data is taken in by a sequencer. This A / D conversion unit includes an A / D converter 3 for converting an analog input into a digital value, a program memory 6 for storing a processing program executed by the A / D conversion unit, and a program stored in the program memory 6. CPU for controlling the processing of the A / D conversion unit according to
5 and a shared memory 7 used for exchanging data with the CPU unit of the sequencer. The shared memory 7 includes a data bus 12, an address bus 13, and read / write control lines 14, 1.
A so-called I / O bus composed of 5 is connected to the CPU unit.

In this A / D conversion unit, the CPU 5 stores the A / D conversion value of the A / D converter 3 in the shared memory 7, and the A / D conversion value stored in this shared memory 7 is the CPU unit of the sequencer. Is read by A
A / D conversion data is given from the / D conversion unit to the CPU unit. This kind of A / D conversion unit is usually provided with a plurality of input sections 1 so that a plurality of kinds of analog data can be taken in. For example, a case where the input unit 1 has four channels (CH0 to CH3) will be described below. In the case of the A / D conversion unit shown in FIG. 8, the analog input from each input unit 1 is converted into one A / D conversion unit.
In order to enable the D converter 3 to convert it into digital data, a multiplexer 2 for switchingably inputting the analog input taken in by each input unit 1 to the A / D converter 3 is provided.

In such an A / D conversion unit, the analog data taken in by the input section 1 of each channel is
It is input to the A / D converter 3 via the multiplexer 2 and sequentially converted into digital data for each channel. Here, the switching control of the multiplexer 2 is performed by the CPU 5 via the latch circuit 9. The data A / D converted by the A / D converter 3 is temporarily stored in the latch circuit 4, and the CPU 5 writes this data in the shared memory 7. In this A / D conversion unit, the latch circuit 4,
An address decoder 8 is provided for writing control of the memory 9 and the memories 6 and 7.

In the conventional A / D conversion unit of this type,
In addition to the A / D conversion function described above, there is one having a function of obtaining an average value of analog inputs by the arithmetic processing of the CPU 5 and determining whether or not the analog inputs exceed arbitrary upper limit values and lower limit values. . However, this type of conventional A / D
The conversion unit only has a function of determining whether the analog input exceeds the upper limit value or falls below the lower limit value for each one point of the upper limit value and the lower limit value. In this case, the shared memory 7 stores the arithmetic processing result together with the A / D conversion value as shown in FIG. A flowchart showing the processing operation of the A / D conversion unit having such an arithmetic processing function is shown in FIG.

[0006]

By the way, this kind of sequencer is usually used for controlling industrial equipment. However, recently, it has been considered to use this kind of sequencer for sorting work performed before shipping eggs and fruits. In sorting eggs and fruits of this kind, they are divided into several groups according to size, weight, appearance superiority, etc. For example, regarding size, S
Sorting such as S, S, M, L, LL is performed.

When a sequencer is used for such a sorting operation, an analog input according to size, weight and appearance is input to an A / D conversion unit and converted into digital data, and the digital data is used to generate a CPU. It suffices to determine which group the unit belongs to. Here, in the CPU unit, some areas may be set in all the conversion value areas, and the selection may be performed so as to determine which group an arbitrary analog input belongs to.

However, if all the sorting processing is performed by the CPU unit in this way, one scan time of the CPU unit becomes long, and as a result, the sorting processing operation becomes slow. Therefore, it is conceivable to cause the A / D conversion unit to bear a part of the sorting process performed by the CPU unit. However, conventional A / D
In the case of a conversion unit, some areas are set in all conversion value areas, and since there is no function to determine which area an arbitrary analog input belongs to, a sequencer is used for sorting processing of eggs and fruits. Was not appropriate.

The present invention has been made in view of the above-mentioned points, and an object of the present invention is to provide an A / D conversion unit that enables a sequencer to be used for sorting processing of eggs and fruits. It is in.

[0010]

In order to achieve the above object, the present invention provides a programmable controller in an A / D conversion unit for providing A / D converted data to a programmable controller for sequentially controlling the operation of a load device. It is equipped with a selection processing means for receiving the data for selection from the above, setting some areas in all conversion value areas according to the data, and determining to which group an arbitrary analog input belongs.

When the A / D conversion unit takes in a plurality of types of analog inputs and performs A / D conversion, the above-mentioned selection processing means comprehensively operates according to the selection result for each type associated with one target. It is preferable to perform a sorting process.

[0012]

The present invention receives data for selection from the programmable controller as described above, sets some areas in all conversion value areas according to the data, and determines which group an arbitrary analog input belongs to. By providing a sorting processing means for discriminating between eggs and fruits, part of the sorting processing of eggs and fruits can be performed by the A / D conversion unit instead of the sequencer, and the scan time can be shortened by shortening the sequence program. It will be possible to perform the sorting work of the above using a sequencer.

Further, when the A / D conversion unit takes in a plurality of types of analog inputs and performs A / D conversion, the selection processing means comprehensively operates according to the selection result for each type associated with one target. If the sorting process is performed, the load on the sequencer side can be further reduced and a quick sorting operation can be performed.

[0014]

【Example】

(Embodiment 1) FIGS. 1 to 4 show an embodiment of the present invention.
The configuration of the A / D conversion unit of this embodiment is exactly the same as that of the conventional one. The feature of this embodiment is that some areas are set in the entire conversion value area and any analog input is used. The point is that the A / D conversion unit has a function of determining whether it belongs to a group.

By the way, in order to enable such a sorting process, it is necessary to provide data for performing the sorting process to the A / D conversion unit. In view of this, in this embodiment, the CPU unit of the sequencer supplies the A / D conversion unit with the data necessary for the sorting process in advance via the shared memory 7. Specifically, as shown in FIG. 3, some areas are set in all conversion value areas of each of the channels CH0 to CH3, and the upper limit value corresponding to each area (group) is written in the shared memory 7. is there.

In the A / D conversion unit of this embodiment, the following initial setting is performed with the upper limit value corresponding to each group written in the shared memory 7. That is, after the conventional initialization after the power is turned on, the upper limit value of each region in all channels is read from the shared memory 7, and the region table is created for each channel CH0 to CH3 based on the read upper limit value.

After this initial setting, first, the multiplexer 2
Set the channel of CH0 (channel 0) to A
The A / D converter 3 performs A / D conversion and stores it in the latch circuit 4. Then, the CPU 5 compares the digital conversion value stored in the latch circuit 4 with the area table of CH0 to determine which group the analog input of CH0 belongs to.

Now, assuming that the groups from the group shown in FIG. 2 to the three groups are selected, the upper limit value of the group for each channel is written in the shared memory 7 by the CPU unit of the sequencer as shown in FIG. The upper limit value of the group matches the full range point of the A / D converter 3. The selection result of which group the analog input belongs to is written in the shared memory 7 as group data in a form of being reflected in the corresponding bit as shown in FIG. Conversion data is also written in the shared memory 7 as shown in FIG.

Thereafter, if the same processing as CH1 → CH2 → CH3 is performed, the data for each of the channels CH0 to CH3 can be selected. In this way, part of the sorting process of eggs and fruits can be performed by the A / D conversion unit instead of the sequencer, and the sequencer side reads the group data stored in the shared memory 7 and uses the group data for sorting. It can be used as data and the sequence program can be shortened. Therefore, as a result, the scan time can be shortened, and the sequencer can be used for the selection work of eggs, fruits and the like. Moreover, the greater the number of analog inputs to be taken in, the more remarkable the effect of shortening the scan time can be.

(Embodiment 2) FIGS. 5 to 7 show another embodiment of the present invention. In the above-described embodiment, the data grouped for each channel (when the object to be selected is an egg or a fruit, the data input for each channel indicates the size, weight, and appearance) is given to the sequencer as it is. However, when selecting eggs and fruits, complex selection may be performed as a result of comprehensive determination of size, weight and appearance. An example suitable for such a case is shown below.

The basic configuration of the A / D conversion unit of this embodiment and the group discrimination processing for each channel are the same as those of the above embodiment. The feature of this embodiment is that the analog input of each channel CH0-CH3 is performed. Of all of the above, and the selection process is completed.
The point is that a composite (comprehensive) sorting process is performed at the time point when the sorting processes of 0 → CH1 → CH2 → CH3 are all completed).

At this time, a case where a composite selection is carried out in two channels of CH0 and CH1 will be described below. It should be noted that each of the channels CH0 and CH1 is divided into three groups. That is, as shown in FIG. 6, for each group to which a certain one channel belongs, which of the groups of the other channels it belongs to is discriminated, and a composite group ~ is discriminated. In this case,
It will be sorted into 9 composite groups. And
As in the case of the group data of the above-described embodiment, the determination result is written in the shared memory 7 as composite group data in a form of being reflected in the corresponding bit as shown in FIG.

After the completion of the processing of the above one cycle, the processing of the next cycle is performed. A flowchart summarizing the above processing is shown in FIG. Also in the case of this embodiment,
As in the case of the above embodiment, by performing a part of the egg / fruit selection process by the A / D conversion unit instead of the sequencer, the sequence program can be shortened and the scan time can be shortened. A sequencer can be used to sort fruits etc. Moreover, in the case of performing composite selection, the sequence program can be further shortened and the scan time can be shortened as compared with the above embodiment.

By the way, FIG. 11 shows the A / D conversion characteristic of the conventional A / D conversion unit of this type. For example, A / D
The resolution of the A / D converter 3 that determines the conversion resolution is 12 bits, and the analog input range is 1 to 5 V due to the hardware setting of the input unit 1, and the A / D is used when an offset value of 1.000 V is input. When the converted value is 0 and the full range value is 5.000V, the A / D converted value is 4000.
In this case, since the full range point of the A / D converter 3 is larger than the full range point of the analog input, the analog input becomes 5.0
If greater than 00V, the digital value is 4001
It can be detected that the input range is exceeded in the range of up to 4095.

However, the analog input range (input section 1)
Since the offset point of 1 and the offset point of the A / D converter 3 have the same value, when an input below the analog input range is made, it cannot be detected. Considering this in the actual use of the A / D conversion unit, the range over due to the abnormality of the analog input device can be detected, but the state below the range due to the disconnection of the input line from the analog input device or the abnormality of the analog input device can be detected. It will not be possible.

Therefore, in order to improve this point, FIG.
As shown in 2, the offset point of the analog input range (input unit 1) may be set higher than the offset point of the A / D converter 3. In the case of FIG. 12, the A / D conversion value is 47 when the offset value (1.000 V) of the analog input range is input due to the hardware setting of the input unit 1.
It is designed to be However, if the offset point of the analog input range (input section 1) is set higher than the offset point of the A / D converter 3 as described above, the full range point (5.0
(00V), the A / D converted value is 4047.
That is, in the case of FIG. 12, the analog input ranges 1 to 5
47 to 4047 of the 12-bit resolution of the A / D converter 3 is associated with V.

In this way, 0 to 47 digits are supported for inputs below the lower limit of 1.000 V of the analog input range, and 4048 to 4095 digits are supported for inputs above the upper limit of 5.000 V of the analog input range. A / D conversion of analog input can be performed. This point is A /
Consider the accuracy of the D conversion unit. The overall accuracy of the A / D conversion unit is usually ± 1.0% or less.
If the conversion resolution is 12 bits, the total accuracy is ±
If it is 1.0% or less, it is ± 40.95 digits or less. Therefore, since the analog input abnormality detection range = 47 digits> 40.95 digits, the analog input corresponding to the abnormality detection area of greater than 40.95 digits and less than or equal to 47 digits can be determined as an abnormality input.

For example, as shown in FIG. 13, the results of A / D conversion for a certain input are (47-40 = 7) to (4
In the case of 047 + 40 = 4087), the analog input is regarded as normal, and the value obtained by subtracting 47 from the converted data is set in the converted value area of the shared memory 7. Incidentally, 40 corresponds to a total accuracy of 40.95. Conversely, the result of A / D conversion for a certain input is less than 7, or 40
If it is larger than 87, it is considered that the analog input is abnormal. In this case, for example, a display element (16 in FIG. 8) that continuously displays the operating state of the A / D conversion unit.
The abnormal display may be performed by, for example, turning on flicker. Here, the abnormality display can be restored when the power is once shut off and then turned on again.

In the above case, the flicker of the display element is turned on to display the abnormality to the user. However, the sequencer may be notified of the abnormality. In this case, as shown in the flow chart of FIG. 14, when the result of A / D conversion for a certain input is smaller than 7 or larger than 4087, the shared memory as shown in FIG. A flag is set on the corresponding bit of the input abnormality flag area provided in FIG. 7 as shown in FIG. In the sequencer, the data in the input abnormality flag area may be read out, and when the abnormality occurs, the abnormality may be notified by, for example, a lamp or a buzzer. Note that FIG.
As shown in (b), it is preferable to indicate in each bit whether each bit is smaller than 7 or larger than 4087 for each channel.

[0030]

As described above, according to the present invention, in the A / D conversion unit for providing A / D converted data to the programmable controller for sequentially controlling the operation of the load device, the data for selection is received from the programmable controller. , Some conversion value areas are set according to the data, and the selection processing means for determining which group an arbitrary analog input belongs to is included in the selection processing of eggs and fruits. Can be performed by the A / D conversion unit instead of the sequencer, the scan time can be shortened by shortening the sequence program, and the sorting work of eggs and fruits can be performed by using the sequencer.

When the A / D conversion unit takes in a plurality of types of analog inputs and performs A / D conversion, the selection processing means comprehensively operates according to the selection result for each type associated with one target. If the sorting process is performed, the load on the sequencer side can be further reduced and a quick sorting operation can be performed.

[Brief description of drawings]

FIG. 1 is a flowchart showing a process of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a selection method as an example.

FIG. 3 is an explanatory diagram of data contents stored in a shared memory.

FIG. 4 is an explanatory diagram of a method of indicating a selection result with group data.

FIG. 5 is a flowchart showing a process of another embodiment.

FIG. 6 is an explanatory diagram of a method of selecting a composite group.

FIG. 7 is an explanatory diagram of a method of indicating a selection result with composite group data.

FIG. 8 is a circuit diagram of a conventional A / D conversion unit.

FIG. 9 is an explanatory diagram showing data contents stored in the shared memory of the above.

FIG. 10 is a flowchart showing the same processing as above.

FIG. 11 is an explanatory diagram showing A / D conversion characteristics of the same.

FIG. 12 is an explanatory diagram of an A / D conversion characteristic in the case where the above-described abnormality is improved so as to be surely detected.

FIG. 13 is a flowchart showing the processing of the A / D conversion unit in the case of improving so that abnormality detection can be reliably performed.

FIG. 14 is a flowchart showing the processing of the A / D conversion unit when the abnormality detection is improved so as to be performed reliably and the abnormality processing method is changed.

15A and 15B are explanatory views of data contents stored in a shared memory and a method of indicating an abnormal state by input abnormal flag data, respectively.

[Explanation of symbols]

 3 A / D converter 5 CPU 6 Program memory 7 Shared memory

Claims (2)

[Claims] 1. An A / D conversion unit that provides A / D converted data to a programmable controller that sequentially controls the operation of a load device, receives selection data from the programmable controller, and performs full conversion according to the data. A / C is characterized by comprising a selection processing means for setting several areas in the value area and determining to which group an arbitrary analog input belongs.
D conversion unit. 2. When the A / D conversion unit takes in a plurality of types of analog inputs and performs A / D conversion, the selection processing means comprehensively operates according to the selection result for each type associated with one target. The A / D conversion unit according to claim 1, wherein the A / D conversion unit is formed by performing various sorting processes.