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JPH0646662B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0646662B2
JPH0646662B2 JP58243801A JP24380183A JPH0646662B2 JP H0646662 B2 JPH0646662 B2 JP H0646662B2 JP 58243801 A JP58243801 A JP 58243801A JP 24380183 A JP24380183 A JP 24380183A JP H0646662 B2 JPH0646662 B2 JP H0646662B2
Authority
JP
Japan
Prior art keywords
region
protection circuit
reference numeral
internal circuit
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58243801A
Other languages
Japanese (ja)
Other versions
JPS60136374A (en
Inventor
秀俊 岩井
一道 光定
政道 石原
哲郎 松本
一幸 宮沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP58243801A priority Critical patent/JPH0646662B2/en
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to FR8419428A priority patent/FR2561042B1/en
Priority to KR1019840008171A priority patent/KR930001564B1/en
Priority to GB08432417A priority patent/GB2152284B/en
Priority to DE3446928A priority patent/DE3446928A1/en
Priority to IT24246/84A priority patent/IT1179545B/en
Publication of JPS60136374A publication Critical patent/JPS60136374A/en
Priority to GB08702881A priority patent/GB2186426B/en
Priority to HK417/90A priority patent/HK41790A/en
Priority to HK480/90A priority patent/HK48090A/en
Priority to JP2406691A priority patent/JPH0638498B2/en
Priority to US07/815,863 priority patent/US5276346A/en
Priority to KR1019920018776A priority patent/KR930006139B1/en
Priority to KR1019920018775A priority patent/KR930001563B1/en
Priority to US08/143,151 priority patent/US5436484A/en
Priority to US08/142,965 priority patent/US5436483A/en
Publication of JPH0646662B2 publication Critical patent/JPH0646662B2/en
Priority to US08/431,568 priority patent/US5534723A/en
Priority to US08/429,868 priority patent/US5610089A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/39—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench
    • H10B12/395—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor and the transistor being in a same trench the transistor being vertical

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
  • Protection Of Static Devices (AREA)
  • Amplifiers (AREA)

Description

【発明の詳細な説明】 ［技術分野］ 本発明は、静電保護回路と内部回路とを同一半導体基板
上に有し、内部回路にＭＩＳ(メタル インシュレータ
セミコンダクタ)素子を用いた半導体装置に関する。Description: TECHNICAL FIELD The present invention relates to a semiconductor device having an electrostatic protection circuit and an internal circuit on the same semiconductor substrate, and using a MIS (metal insulator semiconductor) element for the internal circuit.

［背景技術］ 半導体装置(ＩＣ)の高速化ならびに高集積化を目的とし
て半導体デバイスの小型化がはかられている。ＭＩＳ素
子（ＭＩＳＦＥＴ）の典型的な例であるＭＯＳ素子（Ｍ
ＯＳＦＥＴ）を例外ではない。ＭＯＳ素子の小型化のた
めに、そのゲート酸化膜が薄くなり、チャネル長が短く
なっている。このため、デバイス内部が相対的に高電界
となり、ホットキャリヤのゲート酸化膜への注入現象が
みられ、しきい電圧のシフトや相互コンダクタンスの劣
化が生じる。これを解決するために、第１図に示すよう
な２重拡散ドレイン構造が提案されている。第１図は典
型的なＮチャネルＭＯＳＦＥＴの断面構造を示す。符号
１はＰ型シリコン半導体基板、符号２は二酸化シリコン
（ＳｉＯ２）膜、符号３はゲート酸化膜、符号４はゲー
ト電極である。ドレイン近傍での高電界を緩和するため
にドレインならびにソースは、各々リン(Ｐ)によるＮ−
型層５とひ素(Ａｓ)によるＮ＋型層６とより成る２重拡
散ドレイン構造を有している(雑誌「日経エレクトロニ
クス別冊マイクロデバイセズ」p82〜86)。 ところで、ＭＩＳ素子からなる回路を、ＩＣの外部から
の異状な信号に対して保護するために、同一半導体基板
上に保護回路を形成するのが一般である。[Background Art] Semiconductor devices have been downsized for the purpose of speeding up and highly integrating semiconductor devices (ICs). A MOS element (M which is a typical example of the MIS element (MISFET)
OSFET) is no exception. Due to the miniaturization of MOS devices, the gate oxide film has become thinner and the channel length has become shorter. For this reason, a relatively high electric field is generated inside the device, and a phenomenon of injection of hot carriers into the gate oxide film is observed, which causes shift of the threshold voltage and deterioration of mutual conductance. In order to solve this, a double diffused drain structure as shown in FIG. 1 has been proposed. FIG. 1 shows a cross-sectional structure of a typical N-channel MOSFET. Reference numeral 1 is a P-type silicon semiconductor substrate, reference numeral 2 is a silicon dioxide (SiO 2 ) film, reference numeral 3 is a gate oxide film, and reference numeral 4 is a gate electrode. In order to relax the high electric field in the vicinity of the drain, the drain and the source are N − due to phosphorus (P), respectively.
It has a double-diffused drain structure composed of the type layer 5 and an N + type layer 6 of arsenic (As) (Magazine "Nikkei Electronics Separate Volume Micro Devices" p82-86). By the way, it is general to form a protection circuit on the same semiconductor substrate in order to protect a circuit composed of MIS elements against an abnormal signal from the outside of the IC.

保護回路以外の回路つまりＩＣの内部回路を保護する保
護回路９の代表的なものとして、第２図のような等価回
路で示されるもので知られている。ボンディングパッド
８にその一端を電気的に接続された拡散抵抗１０を介し
て内部回路に信号を送られるとともに、抵抗10と内部回
路との接続点に、そのゲートならびにソースが接地され
たクランプ用ＭＯＳＦＥＴ１１を接続している。As a typical protection circuit 9 that protects circuits other than the protection circuit, that is, the internal circuit of the IC, it is known that the equivalent circuit shown in FIG. A signal is sent to an internal circuit through a diffusion resistor 10 whose one end is electrically connected to a bonding pad 8, and a clamp MOSFET 11 whose gate and source are grounded at a connection point between the resistor 10 and the internal circuit. Are connected.

本発明者は、２重拡散ドレイン構造を採用している半導
体装置を試作したところ、次のような問題があることが
わかった。すなわち、前記半導体装置においては、保護
回路９も同様に２重拡散ドレイン構造によって形成され
る。保護回路９の断面構造は第３図に示すとおりであ
る。第３図において、符号１２はＰ型シリコン半導体基
板、符号１３は分離用のＳｉＯ２膜、符号１０は拡散抵
抗、符号１１はクランプ用ＭＯＳＦＥＴ、符号１４はソ
ース拡散層、符号１５はゲート酸化膜、符号１６はゲー
ト電極、符号１７はリンシリケートガラス(ＰＳＧ)膜、
符号１８はアルミニウム電極である。拡散抵抗１０なら
びにクランプ用ＭＯＳＦＥＴ１１のソース、ドレイン領
域である拡散層はともに２重拡散ドレイン構造であっ
て、Ｎ＋型層とＮ−型層より構成されている。The present inventor made a prototype of a semiconductor device adopting a double diffused drain structure, and found that the following problem was encountered. That is, in the semiconductor device, the protection circuit 9 is also formed by the double diffusion drain structure. The sectional structure of the protection circuit 9 is as shown in FIG. In FIG. 3, reference numeral 12 is a P-type silicon semiconductor substrate, reference numeral 13 is a separation SiO 2 film, reference numeral 10 is a diffusion resistance, reference numeral 11 is a clamping MOSFET, reference numeral 14 is a source diffusion layer, and reference numeral 15 is a gate oxide film. Reference numeral 16 is a gate electrode, reference numeral 17 is a phosphosilicate glass (PSG) film,
Reference numeral 18 is an aluminum electrode. The diffusion resistors 10 and the diffusion layers which are the source and drain regions of the clamping MOSFET 11 both have a double diffusion drain structure and are composed of an N + type layer and an N − type layer.

しかし、前記半導体装置においては、拡散層における接
合部のブレークダウン電圧が上昇するという原因によっ
て、クランプ用ＭＯＳＦＥＴのゲート破壊電圧（あるい
は静電破壊電圧）が低下するという問題点が生ずる。However, in the semiconductor device, there is a problem that the gate breakdown voltage (or electrostatic breakdown voltage) of the clamp MOSFET is lowered due to the increase of the breakdown voltage of the junction in the diffusion layer.

［発明の目的］ 本発明の目的は、ホットキャリヤによる特性劣化と破壊
耐圧劣化との両者をともに改良した半導体装置を提供す
ることである。[Object of the Invention] An object of the present invention is to provide a semiconductor device in which both characteristic deterioration due to hot carriers and breakdown voltage deterioration are improved.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面からあきらかになるであろ
う。The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

［発明の概要］ 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。[Outline of the Invention] The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

すなわち、ドレイン領域がボンディングパッドに接続さ
れたＭＩＳＦＥＴのドレイン耐圧が内部回路におけるＭ
ＩＳＦＥＴのドレイン耐圧より低くなるようにゲート電
極下のドレイン領域の不純物濃度を異ならしめることに
より、内部回路のホットキャリアによる特性劣化を低減
するとともに、クランプ用ＭＩＳＦＥＴのゲート酸化膜
に加わる電界強度を緩和し、高い破壊電圧をもつように
した半導体装置を提供するものである。That is, the drain breakdown voltage of the MISFET whose drain region is connected to the bonding pad is M in the internal circuit.
By varying the impurity concentration of the drain region under the gate electrode so as to be lower than the drain breakdown voltage of the ISFET, the characteristic deterioration due to hot carriers in the internal circuit is reduced and the electric field strength applied to the gate oxide film of the MISFET for clamping is relaxed. In addition, a semiconductor device having a high breakdown voltage is provided.

［実施例］ 以下本発明の半導体装置の一実施例を第４図から第１０
図を参照して説明する。[Embodiment] An embodiment of the semiconductor device of the present invention will be described below with reference to FIGS.
It will be described with reference to the drawings.

第４図は本発明の一実施例であるＤ−ＲＡＭのチップ７
のレイアウトを示す一例である。符号８はボンディング
パッド、符号９は各ボンディングパッドに対して形成さ
れた保護回路、符号１００は書き込み読み出しのタイミ
ング信号等を発生する信号発生回路、符号１０１はＭＩ
Ｓ素子をメモリセルとしたメモリアレイ、符号１０２は
コラムならびにロー用のデコーダである。これによって
Ｄ−ＲＡＭ(ダイナミック−ランダム アクセスメモリ)
チップが構成されている。FIG. 4 shows a D-RAM chip 7 according to an embodiment of the present invention.
Is an example showing a layout of. Reference numeral 8 is a bonding pad, reference numeral 9 is a protection circuit formed for each bonding pad, reference numeral 100 is a signal generation circuit for generating timing signals for writing and reading, and reference numeral 101 is MI.
A memory array in which the S element is a memory cell, reference numeral 102 is a column and row decoder. This allows D-RAM (Dynamic-Random Access Memory)
The chip is configured.

第５図から第８図は本発明の半導体装置を得るための製
造工程を示す図であって、各図の左側には保護回路、右
側には内部回路の一部であるメモリセルを各々対照して
示している。第８図は半導体装置の完成断面図、第９図
ならびに第１０図は第８図に示す半導体装置の概略平面
図である。5 to 8 are views showing a manufacturing process for obtaining the semiconductor device of the present invention. The left side of each figure is a protection circuit, and the right side is a memory cell which is a part of an internal circuit. Is shown. FIG. 8 is a completed sectional view of the semiconductor device, and FIGS. 9 and 10 are schematic plan views of the semiconductor device shown in FIG.

第５図は、従来の公知技術を用いてＤ−ＲＡＭのＭＯＳ
ＦＥＴのゲート電極までを形成した状態断面図である。
図において符号２０は半導体基板、符号２１はゲート酸
化膜、符号２２はゲート電極である。半導体基板２０
は、たとえば（100）結晶を有するＰ型単結晶シリコン
基板、ゲート酸化膜２１は、たとえばＳｉＯ２膜、そし
てゲート電極２２は、第２層目の導体層からなり、たと
えば多結晶シリコンをＣＶＤ（化学気相反応）法によっ
て形成した後、リン等を拡散して抵抗値を下げた多結晶
シリコンである。ゲート電極としては高融点金属層また
はそのシリサイド層、多結晶シリコンと高融点金属のシ
リサイドとの２層構造等を用いてもよい。第５図の左側
には保護回路の一例として第２図に示す回路が形成さ
れ、右側には内部回路の一例としてＤ−ＲＡＭのメモリ
セルが形成される。FIG. 5 shows a MOS of a D-RAM using a conventional known technique.
FIG. 6 is a cross-sectional view showing a state where the gate electrode of the FET is formed.
In the figure, reference numeral 20 is a semiconductor substrate, reference numeral 21 is a gate oxide film, and reference numeral 22 is a gate electrode. Semiconductor substrate 20
Is a P-type single crystal silicon substrate having (100) crystal, the gate oxide film 21 is, for example, a SiO 2 film, and the gate electrode 22 is a second conductor layer. For example, polycrystalline silicon is CVD ( Polycrystalline silicon, which is formed by a chemical vapor reaction method and then has a resistance value reduced by diffusing phosphorus or the like. As the gate electrode, a refractory metal layer or a silicide layer thereof, a two-layer structure of polycrystalline silicon and refractory metal silicide, or the like may be used. A circuit shown in FIG. 2 is formed as an example of a protection circuit on the left side of FIG. 5, and a memory cell of a D-RAM is formed as an example of an internal circuit on the right side.

符号２３は厚い分離用の酸化膜であって、たとえば、シ
リコン基板２０の表面を熱酸化によって選択的に酸化し
たものである。メモリセル側に形成されたこのフィール
ド酸化膜２３ならびにそれとつながる薄いＳｉＯ２酸化
膜２４の表面には、耐酸化膜である窒化シリコン(Ｓｉ
３Ｎ４)膜２５が形成され、その上部にＳｉＯ２膜２６
を介してリン等を拡散して低抵抗化した多結晶シリコン
電極２７が形成されている。この多結晶シリコン電極２
７からなる第１層目の導体層はメモリセルのキヤパシタ
の一方の電極が形成している。なお、この状態ですでに
反転防止層、しきい電圧制御等のイオン打込みはすでに
完了している。Reference numeral 23 is a thick isolation oxide film, which is obtained by selectively oxidizing the surface of the silicon substrate 20 by thermal oxidation, for example. On the surface of the field oxide film 23 formed on the memory cell side and the thin SiO 2 oxide film 24 connected to the field oxide film 23, a silicon nitride (Si
3 N 4 ) film 25 is formed, and a SiO 2 film 26 is formed on top of it.
A polycrystalline silicon electrode 27 is formed in which phosphorus or the like is diffused to reduce the resistance. This polycrystalline silicon electrode 2
The first conductor layer 7 is formed by one electrode of the capacitor of the memory cell. In this state, ion implantation such as inversion prevention layer and threshold voltage control has already been completed.

つぎに、第６図において、保護回路の表面にのみホトリ
ソグラフィ技術を用いて、ホトレジスト膜２８を選択的
に形成する。具体的には、このホトレジスト膜２８は第
４図の領域Ａ上にのみ形成される。このホトレジスト膜
２８をマスクとして、半導体装置全面に２重拡散ドレイ
ン構造のＮ−型を形成するためのイオン打込みを行う。
このイオン打込みは、Ｎ型不純物のたとえばリンイオン
を打込み、ソース、ドレイン領域となるＮ−型拡散層２
９を形成している。Next, in FIG. 6, a photoresist film 28 is selectively formed only on the surface of the protection circuit by using the photolithography technique. Specifically, this photoresist film 28 is formed only on the area A in FIG. Using this photoresist film 28 as a mask, ion implantation is performed on the entire surface of the semiconductor device to form an N − type with a double diffused drain structure.
This ion implantation is performed by implanting N-type impurities such as phosphorus ions to form the N − -type diffusion layer 2 serving as the source and drain regions.
9 is formed.

第７図において、ホトレジスト膜２８を除去した後に、
２重拡散ドレイン構造のＮ＋型層の３０の形成、およ
び、保護回路の拡散抵抗層３１とクランプ用ＭＯＳＦＥ
Ｔのソース、ドレイン領域３２の形成のために、Ｎ型不
純物のたとえばひ素イオンを打込む。In FIG. 7, after removing the photoresist film 28,
Formation of N + type layer 30 of double diffusion drain structure, diffusion resistance layer 31 of protection circuit and clamping MOSFE
To form the T source / drain regions 32, N-type impurities such as arsenic ions are implanted.

第６図ならびに第７図からわかるように、保護回路は１
重拡散ドレイン構造、内部回路は２重拡散ドレイン構造
として構成される。この場合、保護回路にＮ−型層のリ
ンイオンが打込まれないように、マスクとして、ホトレ
ジスト膜２８の選択的形成を利用しているが、イオン打
込み走査を制御することによって保護回路へのリンイオ
ンの打込みをなくすことが可能である。なぜなら、第４
図に示すように、静電保護回路は一般的にチップ周辺の
ある領域に偏在して形成されているので、イオン打込み
走査をこの領域に限定して中止することが比較的容易で
あるからである。As can be seen from FIGS. 6 and 7, the protection circuit is
The heavy diffusion drain structure and the internal circuit are configured as a double diffusion drain structure. In this case, selective formation of the photoresist film 28 is used as a mask so that the phosphorus ions of the N − type layer are not implanted into the protection circuit. However, the phosphorus ions to the protection circuit are controlled by controlling the ion implantation scanning. Can be eliminated. Because the 4th
As shown in the figure, since the electrostatic protection circuit is generally formed unevenly in a certain area around the chip, it is relatively easy to stop the ion implantation scanning only in this area. is there.

このようにして、１重拡散ドレイン構造の静電保護回路
と２重拡散ドレイン構造の内部回路とを形成した後、第
８図に示すように、フォスフォシリケートガラス膜(Ｐ
ＳＧ膜)３３ならびに第３層目の導体層としてのアルミ
ニウム層を形成する。アルミニウム層は、拡散抵抗３１
の引出し電極３４、内部回路への引出し電極３５、ソー
ス電極３６、ならびにメモリセルのデータ線３７等であ
る。なお、ＰＳＧ膜３３を形成した後、これら電極用の
コンタクタ孔形成のためのホトエッチングを行って、ア
ルミニウムのスパッタリングによって電極を形成してい
る。最後に保護膜としてのＰＳＧ膜３８が形成される。After the electrostatic protection circuit having the single diffused drain structure and the internal circuit having the double diffused drain structure are formed in this manner, as shown in FIG. 8, a phosphosilicate glass film (P
SG film) 33 and an aluminum layer as a third conductor layer are formed. The aluminum layer is a diffusion resistor 31
Of the extraction electrode 34, the extraction electrode 35 to the internal circuit, the source electrode 36, the data line 37 of the memory cell, and the like. After the PSG film 33 is formed, photo-etching for forming contactor holes for these electrodes is performed, and the electrodes are formed by sputtering aluminum. Finally, the PSG film 38 as a protective film is formed.

第９図ならびに第１０図は、各々、第８図の静電保護回
路ならびに内部回路の概略平面図である。第９図のＢ−
Ｂ矢視面、第１０図のＣ−Ｃ矢視面が各々第８図の保護
回路を示す領域ならびに内部回路を示す領域に対応して
いる。9 and 10 are schematic plan views of the electrostatic protection circuit and internal circuit of FIG. 8, respectively. B- in FIG.
The view on the arrow B and the view on the arrow C-C in FIG. 10 correspond to the region showing the protection circuit in FIG. 8 and the region showing the internal circuit, respectively.

第９図において、符号４０はボンディングパッド部、符
号４１は入力部拡散層、符号４２はコンタクトホール、
符号４３は拡散抵抗であり、符号４４はクランプ用ＭＯ
ＳＦＥＴに各々対応している。クランプ用ＭＯＳＦＥＴ
４４は、各々拡散抵抗４３に電気的に接続される領域４
５、ゲート電極４６、ならびにソース部４７とより成
る。領域４５はコンタクト４５ＡによりＡｌ信号線４５
Ｂにより接続され、Ａｌ信号線４５Ｂは内部回路に電気
的に接続されている。一方、ソース部４７はコンタクト
４７ＡによりＡｌ線４７Ｂに接続され、４７Ｂの一端は
コンタクト４８を介てゲート電極に接続され、そして他
端は接地されている。In FIG. 9, reference numeral 40 is a bonding pad portion, reference numeral 41 is an input diffusion layer, reference numeral 42 is a contact hole,
Reference numeral 43 is a diffusion resistance, and reference numeral 44 is a clamp MO.
It corresponds to each SFET. MOSFET for clamp
Reference numeral 44 denotes a region 4 electrically connected to the diffusion resistance 43.
5, a gate electrode 46, and a source part 47. The region 45 has an Al signal line 45 formed by the contact 45A.
A signal line 45B is electrically connected to the internal circuit. On the other hand, the source portion 47 is connected to the Al wire 47B by the contact 47A, one end of 47B is connected to the gate electrode through the contact 48, and the other end is grounded.

第１０図において、符号５０はメモリセルの活性領域を
規定するフイールド酸化膜の境界線であり、符号５１は
多結晶シリコンのワード線でＭＯＳＦＥＴのゲート電極
に対応している。符号５２はメモリセルのキャパシタン
スの一方の電極である多結晶シリコン、符号５３はデー
タ線のコンタクトホール５４に配線されたアルミニウム
電極である。In FIG. 10, reference numeral 50 is a boundary line of the field oxide film which defines the active region of the memory cell, and reference numeral 51 is a polycrystalline silicon word line corresponding to the gate electrode of the MOSFET. Reference numeral 52 is polycrystalline silicon which is one electrode of the capacitance of the memory cell, and reference numeral 53 is an aluminum electrode which is wired in the contact hole 54 of the data line.

第１１図は、保護回路が１重拡散ドレイン構造のもの
と、２重拡散ドレイン構造のものとの静電破壊電圧の比
較を示した実験的データの代表例を示すグラフである。
縦軸は％表示の累積不良率を示し、横軸はボルト表示が
静電破壊電圧を示している。折線(ａ)は２重拡散ドレイ
ン構造のもの、折線(ｂ)は１重拡散ドレイン構造のもの
で、供試サンプル５個を用い同一ピンについての耐圧を
調べた結果である。グラフから明らかなように、保護回
路に１重拡散ドレイン構造を用いたものの静電破壊電圧
がはるかに改善されていることがわかる。FIG. 11 is a graph showing a representative example of experimental data showing a comparison of electrostatic breakdown voltage between a protection circuit having a single diffusion drain structure and a protection circuit having a double diffusion drain structure.
The vertical axis represents the cumulative defective rate in%, and the horizontal axis represents the electrostatic breakdown voltage in volts. The polygonal line (a) has a double diffused drain structure, and the polygonal line (b) has a single diffused drain structure. The results are obtained by examining the withstand voltage for the same pin using five test samples. As is apparent from the graph, the electrostatic breakdown voltage of the protection circuit using the single diffusion drain structure is much improved.

［効 果］ 以上説明したように、保護回路を１重拡散ドレイン構造
とし、内部回路を２重拡散ドレイン構造としたことによ
り、内部回路の電界集中が緩和されるとともに保護回路
のゲート酸化膜への電界集中が緩和されるので、ホット
キャリヤならびに破壊電圧の両者に対する対策をともに
備えることができるという効果が得られる。[Effects] As described above, the protection circuit having the single-diffused drain structure and the internal circuit having the double-diffused drain structure alleviate the electric field concentration in the internal circuit and prevent the gate oxide film of the protective circuit from being formed. Since the concentration of the electric field is relaxed, it is possible to provide the countermeasures against both hot carriers and breakdown voltage.

また、保護回路にマスクを施して２重拡散ドレインの一
方の拡散層の形成を阻止しているので、ホトリソグラフ
ィの工程を１回追加することによって容易に本発明の半
導体装置を製造できるという効果が得られる。Further, since a mask is applied to the protection circuit to prevent formation of one diffusion layer of the double diffusion drain, the semiconductor device of the present invention can be easily manufactured by adding the photolithography step once. Is obtained.

さらに、イオン打込み走査を比較的偏在ないしは局在し
ている保護回路に局部的に制御する方法を用いれば、簡
単な製造工程によって実施できるという効果が得られ
る。Furthermore, if the method of locally controlling the ion implantation scanning to the protection circuit which is relatively unevenly distributed or localized, the effect that it can be implemented by a simple manufacturing process is obtained.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、保護回路を
１個の拡散抵抗と１個のクランプ用ＭＯＳＦＥＴより成
るものとして例示したが、これに限定されるものではな
く、少なくとも拡散層における接合部降伏およびクラン
プ用ＭＯＳＦＥＴのドレイン端における表面降伏を静電
破壊電圧の向上に利用している種々の保護回路に適用で
きる。同様に内部回路の例示としてＤ−ＲＡＭを挙げた
が、これに限定されるものではなく少なくとも２重拡散
ドレイン構造のＭＩＳ素子を有するもの全般に適用でき
る。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention. Nor. For example, although the protection circuit is illustrated as including one diffusion resistor and one clamp MOSFET, the present invention is not limited to this, and at least the junction breakdown in the diffusion layer and the surface at the drain end of the clamp MOSFET are performed. It can be applied to various protection circuits that utilize breakdown to improve electrostatic breakdown voltage. Similarly, although the D-RAM has been described as an example of the internal circuit, the present invention is not limited to this and can be applied to all those having at least a double diffusion drain structure MIS element.

［利用分野］ 以上の説明では主としてその発明の背景となったＤ−Ｒ
ＡＭとその保護回路に適用した場合について説明した
が、広く一般のＭＯＳ集積回路、たとえばＤ−ＲＡＭ、
Ｓ−ＲＡＭ、ＭＯＳロジック等に適用できる。[Field of Application] In the above description, the D-R that mainly became the background of the invention
Although the case where it is applied to the AM and its protection circuit has been described, widely used general MOS integrated circuits such as D-RAM,
It can be applied to S-RAM, MOS logic and the like.

【図面の簡単な説明】[Brief description of drawings]

第１図は２重拡散ドレイン構造のＮチャネルＭＩＳ素子
を示す断面図、 第２図は静電保護回路の一例を示す電気的等価回路、 第３図は第２図の等価回路に対応する具体的なデバイス
の断面図、 第４図は同一半導体基板上に静電保護回路と内部回路と
を有したＤ−ＲＡＭのチップパターンの一例を示す平面
図、 第５図から第８図は、本発明の半導体装置ならびにその
製造方法のプロセスの一実施例を示す断面図、 第９図ならびに第１０図は、第８図に示した静電保護回
路ならびに内部回路に対応した概略平面図、 第１１図は１重拡散ドレイン構造の静電保護回路と、２
重拡散ドレイン構造の静電保護回路との各々の静電破壊
電圧を比較実験したグラフである。 ９……静電保護回路、１０１〜１０２……内部回路、１
０……拡散抵抗、１１……クランプＭＯＳ、２８……ホ
トレジスト膜、２９……Ｎ−層（第１の拡散層）、３０
……Ｎ＋層（第２の拡散層）、３１，３２……Ｎ＋層
（静電保護回路の拡散層）。FIG. 1 is a sectional view showing an N-channel MIS element having a double diffused drain structure, FIG. 2 is an electrical equivalent circuit showing an example of an electrostatic protection circuit, and FIG. 3 is a concrete example corresponding to the equivalent circuit of FIG. FIG. 4 is a plan view showing an example of a chip pattern of a D-RAM having an electrostatic protection circuit and an internal circuit on the same semiconductor substrate, and FIGS. FIG. 9 is a cross-sectional view showing one embodiment of the process of the semiconductor device of the invention and the manufacturing method thereof, FIGS. 9 and 10 are schematic plan views corresponding to the electrostatic protection circuit and the internal circuit shown in FIG. The figure shows an electrostatic protection circuit with a single diffusion drain structure and 2
5 is a graph showing a comparative experiment of electrostatic breakdown voltages of an electrostatic protection circuit having a heavy diffusion drain structure. 9 ... Electrostatic protection circuit 101-102 ... Internal circuit, 1
0 ... Diffusion resistance, 11 ... Clamp MOS, 28 ... Photoresist film, 29 ... N - layer (first diffusion layer), 30
... N + layer (second diffusion layer), 31, 32 ... N + layer (diffusion layer of electrostatic protection circuit).

フロントページの続き (72)発明者 松本 哲郎 東京都小平市上水本町1450番地 株式会社 日立製作所デバイス開発センタ内 (72)発明者 宮沢 一幸 東京都小平市上水本町1450番地 株式会社 日立製作所デバイス開発センタ内Front page continuation (72) Inventor Tetsuro Matsumoto 1450, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Device Development Center (72) Inventor Kazuyuki Miyazawa 1450, Kamimizumoto-cho, Kodaira-shi, Tokyo Hitachi Device Development Co., Ltd. In the center

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】半導体基板上部の入力用ボンディングパッ
ドと、内部回路と、上記内部回路を保護する保護回路と
を有する半導体装置であって、 上記保護回路は第１ＭＩＳＦＥＴを有し、上記第１ＭＩ
ＳＦＥＴは上記半導体基板上の第１ゲート絶縁膜と、該
第１ゲート絶縁膜上に第１ゲート電極を有し、該第１ゲ
ート電極は接地されるとともに、上記第１ゲート電極の
下の部分で上記半導体基板とｐｎ接合を形成し、かつ上
記入力用ボンディングパッドに電気的に接続された第１
半導体領域とを持ち、 上記内部回路は第２ＭＩＳＦＥＴを有し、上記第２ＭＩ
ＳＦＥＴは、第２ゲート電極と、上記半導体基板上の第
２ゲート絶縁膜と、上記半導体基板内のソース及びドレ
イン領域と、上記第２ゲート絶縁膜の下のチャンネル領
域とを持ち、 上記第２ＭＩＳＦＥＴのソース及びドレイン領域は高濃
度の第１領域と、上記第１領域の濃度よりも低濃度の第
２領域とを有するものであって、上記第１領域と上記第
２領域は上記第１半導体領域と同一の導電型で形成され
ており、上記第２領域は上記第１領域よりも外側に形成
されるとともに上記第２ゲート電極下において上記チャ
ンネル領域に接するように形成され、 上記第１半導体領域の不純物濃度は上記第２領域の不純
物濃度よりも高く、 上記保護回路の第１ＭＩＳＦＥＴの第１半導体領域が、
上記内部回路の保護されるべき素子に接続されてなる半
導体装置。1. A semiconductor device having an input bonding pad on an upper part of a semiconductor substrate, an internal circuit, and a protection circuit for protecting the internal circuit, wherein the protection circuit has a first MISFET.
The SFET has a first gate insulating film on the semiconductor substrate and a first gate electrode on the first gate insulating film, and the first gate electrode is grounded and a portion below the first gate electrode. Forming a pn junction with the semiconductor substrate and electrically connecting to the input bonding pad.
A semiconductor region, the internal circuit has a second MISFET, and the second MI
The SFET has a second gate electrode, a second gate insulating film on the semiconductor substrate, source and drain regions in the semiconductor substrate, and a channel region under the second gate insulating film, the second MISFET The source and drain regions have a high-concentration first region and a second region having a lower concentration than the first region, and the first region and the second region are the first semiconductor. The second region is formed to have the same conductivity type as the region, the second region is formed outside the first region, and is formed so as to be in contact with the channel region under the second gate electrode. The impurity concentration of the region is higher than the impurity concentration of the second region, and the first semiconductor region of the first MISFET of the protection circuit is
A semiconductor device connected to an element to be protected of the internal circuit.
JP58243801A 1983-12-26 1983-12-26 Semiconductor device Expired - Lifetime JPH0646662B2 (en)

Priority Applications (17)

Application Number Priority Date Filing Date Title
JP58243801A JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device
FR8419428A FR2561042B1 (en) 1983-12-26 1984-12-19 SEMICONDUCTOR DEVICE PROVIDED WITH AN ELECTROSTATIC PROTECTION CIRCUIT OF AN INTERNAL CIRCUIT AND ITS MANUFACTURING METHOD
KR1019840008171A KR930001564B1 (en) 1983-12-26 1984-12-20 Semiconductor integrated circuit device
GB08432417A GB2152284B (en) 1983-12-26 1984-12-21 Semiconductor device and protective circuit
DE3446928A DE3446928A1 (en) 1983-12-26 1984-12-21 SEMICONDUCTOR ARRANGEMENT
IT24246/84A IT1179545B (en) 1983-12-26 1984-12-24 SEMICONDUCTOR DEVICE AND PROCEDURE FOR ITS MANUFACTURE
GB08702881A GB2186426B (en) 1983-12-26 1987-02-09 Semiconductor device and method of fabrication thereof
HK417/90A HK41790A (en) 1983-12-26 1990-05-31 Semiconductor device and method of fabrication thereof
HK480/90A HK48090A (en) 1983-12-26 1990-06-21 Semiconductor device and method of fabrication thereof
JP2406691A JPH0638498B2 (en) 1983-12-26 1990-12-26 Method for manufacturing semiconductor device
US07/815,863 US5276346A (en) 1983-12-26 1992-01-02 Semiconductor integrated circuit device having protective/output elements and internal circuits
KR1019920018776A KR930006139B1 (en) 1983-12-26 1992-10-13 Manufacturing method of semiconductor ic device
KR1019920018775A KR930001563B1 (en) 1983-12-26 1992-10-13 Semiconductor integrated circuit device
US08/143,151 US5436484A (en) 1983-12-26 1993-10-29 Semiconductor integrated circuit device having input protective elements and internal circuits
US08/142,965 US5436483A (en) 1983-12-26 1993-10-29 Semiconductor integrated circuit device having a first MISFET of an output buffer circuit and a second MISFET of an internal circuit
US08/431,568 US5534723A (en) 1983-12-26 1995-04-27 Semiconductor integrated circuit device having output and internal circuit MISFETS
US08/429,868 US5610089A (en) 1983-12-26 1995-04-27 Method of fabrication of semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58243801A JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2406691A Division JPH0638498B2 (en) 1983-12-26 1990-12-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS60136374A JPS60136374A (en) 1985-07-19
JPH0646662B2 true JPH0646662B2 (en) 1994-06-15

Family

ID=17109142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58243801A Expired - Lifetime JPH0646662B2 (en) 1983-12-26 1983-12-26 Semiconductor device

Country Status (7)

Country Link
JP (1) JPH0646662B2 (en)
KR (1) KR930001564B1 (en)
DE (1) DE3446928A1 (en)
FR (1) FR2561042B1 (en)
GB (2) GB2152284B (en)
HK (2) HK41790A (en)
IT (1) IT1179545B (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62169468A (en) * 1986-01-22 1987-07-25 Nec Corp Semiconductor integrated circuit device
JPS63119574A (en) * 1986-11-07 1988-05-24 Toshiba Corp Manufacture of semiconductor device
US5183773A (en) * 1989-04-13 1993-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing semiconductor device including such input protection transistor
US5142345A (en) * 1989-04-13 1992-08-25 Mitsubishi Denki Kabushiki Kaisha Structure of input protection transistor in semiconductor device including memory transistor having double-layered gate and method of manufacturing semiconductor device including such input protection transistor
JP2953192B2 (en) * 1991-05-29 1999-09-27 日本電気株式会社 Semiconductor integrated circuit
JP3456242B2 (en) * 1993-01-07 2003-10-14 セイコーエプソン株式会社 Semiconductor device and manufacturing method thereof

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US373249A (en) * 1887-11-15 Clock
GB1170705A (en) * 1967-02-27 1969-11-12 Hitachi Ltd An Insulated Gate Type Field Effect Semiconductor Device having a Breakdown Preventing Circuit Device and a method of manufacturing the same
US3999212A (en) * 1967-03-03 1976-12-21 Hitachi, Ltd. Field effect semiconductor device having a protective diode
DE2545871B2 (en) * 1974-12-06 1980-06-19 International Business Machines Corp., Armonk, N.Y. (V.St.A.) Field effect transistor with improved stability of the threshold voltage
NL176322C (en) * 1976-02-24 1985-03-18 Philips Nv SEMICONDUCTOR DEVICE WITH SAFETY CIRCUIT.
DE2940954A1 (en) * 1979-10-09 1981-04-23 Nixdorf Computer Ag, 4790 Paderborn METHOD FOR THE PRODUCTION OF HIGH-VOLTAGE MOS TRANSISTORS CONTAINING MOS-INTEGRATED CIRCUITS AND CIRCUIT ARRANGEMENT FOR SWITCHING POWER CIRCUITS USING SUCH HIGH-VOLTAGE MOS TRANSISTORS
US4342045A (en) * 1980-04-28 1982-07-27 Advanced Micro Devices, Inc. Input protection device for integrated circuits
JPS5715459A (en) * 1980-07-01 1982-01-26 Fujitsu Ltd Semiconductor integrated circuit
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
JPS57188364U (en) * 1981-05-25 1982-11-30
JPS57211272A (en) * 1981-06-23 1982-12-25 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
IT1179545B (en) 1987-09-16
FR2561042A1 (en) 1985-09-13
GB2186426A (en) 1987-08-12
GB8432417D0 (en) 1985-02-06
GB8702881D0 (en) 1987-03-18
JPS60136374A (en) 1985-07-19
GB2152284B (en) 1988-01-06
HK48090A (en) 1990-06-29
GB2152284A (en) 1985-07-31
GB2186426B (en) 1988-01-06
HK41790A (en) 1990-06-08
IT8424246A0 (en) 1984-12-24
FR2561042B1 (en) 1988-11-10
KR850005166A (en) 1985-08-21
KR930001564B1 (en) 1993-03-04
DE3446928A1 (en) 1985-07-04

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