JPH0646640B2 - Silicon thin film transistor and method of manufacturing silicon thin film transistor - Google Patents

Description

TECHNICAL FIELD The present invention relates to a silicon thin film transistor used for an active matrix type liquid crystal display and the like, and a manufacturing method thereof.

[Prior Art] FIG. 2 is a process sectional view showing a conventional method for manufacturing a silicon thin film transistor.

Hereinafter, the manufacturing method will be described with reference to FIGS.

(A) A gate insulating layer 3 made of silicon nitride, a silicon layer 4a made of amorphous silicon, and a protective insulating layer 5 made of silicon nitride are sequentially formed on the insulating substrate 1 on which the gate electrode 2 is formed. Then, a part of the protective insulating layer 5 is etched to expose the silicon layer 4a, and a pair of contact portions 6 that overlap the end portion of the gate electrode 2 are formed.

(B) An impurity silicon layer 8 containing, for example, an appropriate amount of phosphorus as an impurity is formed.

(C) Part of the impurity silicon layer 8 is etched to form the impurity silicon layer 8 in the shape of the source and drain electrodes including the pair of contact portions 6.

According to the above manufacturing method, a silicon thin film transistor as shown in FIG.

[Problems to be Solved] In the silicon thin film transistor manufactured as described above, stress is concentrated on the gate insulating layer 3 or the silicon layer 4a formed near the end of the gate electrode 2, and cracks are likely to occur at this portion. When the crack reaches the gate electrode 2, the impurity silicon layer 8 reaches the gate electrode 2 when the impurity silicon layer 8 is formed in the step of FIG. There arises a problem that the impurity silicon layer 8 serving as the source and drain electrodes becomes conductive. Even if the crack does not reach the gate electrode 2, the gate insulating layer 3 and the protective insulating layer 5 are usually formed of the same kind of material, so that the protective insulating layer is formed in the step of FIG. When the layer 5 is etched, the gate insulating layer 3 is simultaneously etched through the cracks in the silicon layer 4a, the vacancies reach the gate electrode 2 in the same manner as above, and the gate electrode 2 and the impurity silicon layer 6 are also electrically connected. The problem arises.

An object of the present invention is to provide a silicon thin film transistor and a method for manufacturing a silicon thin film transistor in which the gate electrode and the impurity silicon layer are not electrically connected.

[Means for Solving the Problems] A silicon thin film transistor of the present invention includes a gate electrode formed on an insulating substrate, a gate insulating layer formed on the insulating substrate and on the gate electrode, and the gate insulating film. A first silicon layer formed on the layer and not doped with impurity atoms, a pair of impurity silicon layers doped with n-type impurities to serve as a source and a drain, the first silicon layer and the pair of impurity silicon A pair of second silicon layers which are formed between the first silicon layer and the pair of impurity silicon layers and which are not doped with impurity atoms, and between the first silicon layer and the pair of second silicon layers. It has a formed protective insulating layer.

A method of manufacturing a silicon thin film transistor according to the present invention comprises a step of sequentially forming a gate insulating layer, a first silicon layer not doped with impurity atoms, and a protective insulating layer on an insulating substrate having a gate electrode formed thereon, and the above protection. A step of removing a part of the insulating layer to expose a part of the first silicon layer; and a second step in which impurity atoms are not doped on the protective insulating layer and the exposed first silicon layer. Forming a silicon layer, forming an impurity silicon layer doped with an n-type impurity on the second silicon layer, and removing a part of the impurity silicon layer to form a source and a drain And a step of forming the second silicon layer in the planar shape of the source and drain.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is an insulating substrate, 2 is a gate electrode, and 3
Is a gate insulating layer using silicon nitride, 4 is a first silicon layer using amorphous silicon, 5 is a protective insulating layer using silicon nitride, 6 is a contact portion, and 7 is amorphous silicon The second silicon layer 8 is an n-type silicon layer obtained by doping amorphous silicon with phosphorus.

Hereinafter, the manufacturing process will be described with reference to FIGS.

(A) On the insulating substrate 1 on which the gate electrode 2 is formed, a gate insulating layer 3 using silicon nitride, a first silicon layer (thickness 30 nm) 4 using amorphous silicon, and silicon nitride are used. The protective insulating layer 5 is formed, and the protective insulating layer 5 is formed.
Are removed to expose the first silicon layer 4 to form a pair of contact portions 6.

(B) A second silicon layer (film thickness 100 nm) 7 made of amorphous silicon and an n-type silicon layer (film thickness 30 nm) 8 obtained by doping amorphous silicon with phosphorus are sequentially formed. At this time, it is preferable that the second silicon layer 7 and the n-type silicon layer 8 are continuously formed in a vacuum state so that the interface characteristics between them do not deteriorate.

(C) The second silicon layer 7 and the n-type silicon layer 8
A part is removed and the second silicon layer 7 and the n-type silicon layer 8 are formed in the shape of the source and drain electrodes including the pair of contacts 6. The contact portion refers to a connection portion between the second silicon layer 7 formed in the shape of the source and drain electrodes and the first silicon layer 4.

With the above manufacturing method, a silicon thin film transistor as shown in FIG.

In addition, the first silicon layer 4, the second silicon layer 7,
The formation temperature and film thickness of the n-type silicon layer 8 are preferably set as follows.

First silicon layer 20 to 30 nm, 350 to 600 ° C. Second silicon layer 50 nm or more, 250 to 300 ° C. n-type silicon layer 20 to 50 nm, 200 to 300 ° C. Even if a hole reaching the contact portion 6 is formed, since the n-type silicon layer 8 is formed via the second silicon layer 7, the gate electrode 2 and n
The type silicon layer 8 does not conduct. Moreover, it is also possible to fill the voids when forming the second silicon layer 7.

Further, if the thickness of the second silicon layer 7 is increased, the withstand voltage between the gate electrode 2 and the n-type silicon layer 8 forming the source and drain electrodes can be increased.

Furthermore, in the case where the second silicon layer 7 and the n-type silicon layer 8 are continuously formed in a vacuum state, the interface characteristics between them are not deteriorated, so that good transistor characteristics can be obtained.

The first silicon layer 4, the second silicon layer 7, and the n-type silicon layer 8 are not limited to amorphous silicon, and polysilicon or the like may be used.

EFFECTS OF THE INVENTION According to the silicon thin film transistor of the present invention, since the second silicon layer not doped with impurity atoms is formed between the first silicon layer and the impurity silicon layer, the gate electrode and the impurity are not formed. It is possible to prevent conduction with the silicon layer.

According to the method of manufacturing a silicon thin film transistor of the present invention, a second silicon layer that is not doped with impurity atoms is formed on the first silicon layer, and an n-type impurity is doped on the second silicon layer. Since the impurity silicon layer is formed, it is possible to prevent conduction between the gate electrode and the impurity silicon layer even if a hole is formed in the gate insulating layer or the first silicon layer.
It is also possible to fill the voids with the silicon layer, and it is possible to greatly improve the yield.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process showing an embodiment of a silicon thin film transistor according to the present invention, and FIG. 2 is a sectional view of a manufacturing process of a conventional silicon thin film transistor. DESCRIPTION OF SYMBOLS 1 ... Insulating substrate 2 ... Gate electrode 3 ... Gate insulating layer 4 ... 1st silicon layer 5 ... Protective insulating layer 7 ... 2nd silicon layer 8 ... Impurity silicon layer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Katsuo Shirai 531 Shimodano, Shiobara-cho, Nasu-gun, Tochigi Prefecture Japan Precision Circuits Co., Ltd. (72) Kazunori Saito 531 Shimodano Shimohara, Nasu-gun, Tochigi Prefecture ―1 Within Japan Precision Circuits Co., Ltd. (56) Reference JP-A-1-149480 (JP, A)

Claims (2)

[Claims] 1. A gate electrode formed on an insulating substrate, a gate insulating layer formed on the insulating substrate and on the gate electrode, and an impurity atom formed on the gate insulating layer. A first silicon layer, a pair of impurity silicon layers doped with n-type impurities to serve as a source and a drain, and the pair of impurity silicon layers between the first silicon layer and the pair of impurity silicon layers. A pair of second silicon layers which are formed corresponding to the above and are not doped with impurity atoms, and a protective insulating layer which is formed on the first silicon layer and between the pair of second silicon layers. Characteristic silicon thin film transistor. 2. A gate insulating layer on an insulating substrate on which a gate electrode is formed, a first undoped impurity atom.
Sequentially forming a silicon layer and a protective insulating layer, exposing a part of the first silicon layer by removing a part of the protective insulating layer, and forming a part of the first silicon layer on the protective insulating layer and the exposed first insulating layer. Forming a second silicon layer not doped with impurity atoms on the first silicon layer; forming an impurity silicon layer doped with n-type impurities on the second silicon layer; And a step of removing a part of the impurity silicon layer to form a source and a drain and forming the second silicon layer into a planar shape of the source and the drain.