JPH0644697B2 - Gain control circuit - Google Patents

Description

The present invention relates to a gain control circuit controlled by a digital signal, and can be applied to, for example, a signal compression circuit, a signal expansion circuit and the like.

[Outline of Invention]

According to the present invention, the gain control circuit is connected to a plurality of stages, a predetermined effective bit length is determined from a digital input signal, and data for controlling the gain control circuit of each stage is created based on the effective bit length to obtain the effective The present invention provides a gain control circuit that can perform control with substantially high bit length precision by using a circuit having precision according to the bit length.

[Conventional technology]

Conventionally, as a gain control circuit for controlling the gain by a digital signal, a gain control circuit composed of a multiplication type D / A converter and an operational amplifier, a resistance attenuator or P
Those using a WM circuit are known.

FIG. 8 and FIG. 9 show an example of a gain control circuit composed of a multiplication D / A converter and an operational amplifier.

In FIG. 8, the multiplying D / A converter 6 has its terminal 1 connected to the negative feedback circuit of the operational amplifier 7, terminal 2 connected to the inverting terminal of the operational amplifier 7, and terminal 4 grounded. When the analog signal A is input to the terminal 3, the analog output signal AO is obtained from the operational amplifier 7.

As the multiplication type D / A converter 6, as shown in FIG. 10, a plurality of resistors R, 2R and analog switches 8 ₁ , 8 are used.
An R-2R type network composed of ₂ ... 8 _n and terminals _{1 to 4} , 5 ₁ , 5 ₂ ... 5 _n is used. Above terminal 5
_{1 to} 5 _n are input terminals for an n-bit digital signal D, and the analog switches 8 ₁ to 8 _n cause the contact H on the terminal 2 side by the signal of “H” input to each of the terminals 5 _{1 to} 5 _n.
And is closed to the contact L on the terminal 4 side by the signal of "L". A negative feedback resistor R is connected between the terminals 1 and 2.

The output signal AO of the operational amplifier 7 in FIG. And AO is proportional to the product of A × D. Therefore, this circuit operates as a multiplication type variable gain amplifier, and its gain is −∞ dB to 0 dB (0 times to 1 times). Such a multiplication type variable gain amplifier is disclosed, for example, in Japanese Patent Application No. 60-57216.
Can be used in the signal expander disclosed in No.

Next, in FIG. 8, when the terminal 3 and the terminal 1 are interchanged and connected, a division type variable gain amplifier as shown in FIG. 9 is constructed.

In this case, the resistance R between the terminals 1 and 2 is connected to the inverting terminal of the operational amplifier 7, and the analog switches 8 ₁ to 8 are connected.
_The resistance that changes with the switching of _n is connected to the negative feedback circuit of the operational amplifier 7. Therefore, the output AO of this division type variable gain amplifier is And is proportional to the value obtained by dividing A by D. Therefore, the gain is 0 dB to + ∞ dB to (1 to ∞ times). Such a division type variable gain amplifier can be used, for example, in the signal compressor disclosed in Japanese Patent Application No. 60-57213.

[Problems to be solved by the invention]

In the above-mentioned digital control type gain control circuit, in order to make the change amount of the output signal AO small for one step of the digital signal D, it is necessary to increase the number of bits of the signal D. However, in reality, only circuits that can handle signals with 16-bit precision are available,
Moreover, it is quite expensive. Therefore, it is conceivable to divide the number of bits into a plurality of bits and process them in each circuit, but even in that case, the accuracy itself required for each circuit is not relaxed at all.

[Means for solving problems]

According to the present invention, a plurality of gain control circuits and a control circuit which determines a predetermined effective bit length from a digital input signal and creates data for controlling the gain control circuits of respective stages based on the effective bit length are provided. There is.

[Action]

By using a circuit having a precision according to the effective bit length, it is possible to perform control with a substantially high bit length precision.

〔Example〕

FIG. 3 shows an embodiment of a gain control circuit using a resistance attenuator to which the present invention can be applied.

This circuit uses the n-bit digital signal D to output 2 ⁿ switches SW _{0 to} SW through the switch control circuit.
_{One of the 2 (n-1)} switches is turned on. ^If all 2 ⁿ resistors R ₁ -R _2n are equal, then the circuit operates as an analog-to-digital multiplier and its gain G is Becomes

FIG. 1 shows an embodiment of the present invention using the above resistance attenuator, and FIG. 2 shows the principle of the present invention.

In FIG. 1, the analog input signal A is controlled by the first gain control circuit 11 by the digital data d _{11 and then} by the second gain control circuit 12 by the digital data d ₂ . . (M +
The control input data d having a bit length of n) bits is generated into the data d ₁ and d ₂ in the control circuit 13, and the data d ₁ is converted into the data d ₁₁ by the conversion circuit 14.

As shown in FIG. 2, of the (m + n) -bit input data d, data d ₂ having an effective bit length of n bits is controlled to control the second gain control circuit 12. In this case, the data d ₂ has a different position for taking out n-bit data depending on the size of the data d as shown in the figure. In the illustrated example, when the data d is maximum, the data d ₂ takes out n pieces of data of MBS or less, and n pieces of data are taken out by shifting by 1 bit according to the size of the data d. . Therefore, a total of (m + 1) pieces of data d ₂ are obtained, and in the illustrated case, m
= 4, 5 pieces of data d ₂ are obtained. Also data d
The data on the upper side (the portion indicated by the dotted line) remaining after extracting the data d ₂ from is used as the data d ₁ . This data d _{1 is} also obtained (m + 1), and in FIG. 2, five data d ₁ are numbered 0-4. These five pieces of data d ₁ are converted into data d ₁₁ by the conversion circuit 14. Each data d ₁ , d ₁₁ , d _{2 for the} data d
Is represented as in FIG.

In FIG. 4, d ₁₁ represents d ₁ of 0 to 4 as 5-bit data. Also, d ₂ is always 111 ... 11 at maximum and 110 ... 00 at minimum when d ₁ is ₁ to 4. In this case, the maximum rate of change of the output AO when the least significant bit of d ₂ changes by one step is Becomes When d ₁ is 0, d ₂ is maximum 111 ... 11,
The minimum is 000 ... 00, and the effective bit length n is the data d.
However, this is not a problem because the same effective bit length is obtained even when a gain control circuit of (m + n) bits is used.

According to the above, the first gain control circuit 11 in FIG.
The first gain control circuit 11 is exponentially controlled by using the (m + 1) -bit signal for the second gain control circuit 12 and the n-bit second gain control circuit 12 for the second gain control circuit 12. It can be controlled mantissa. Therefore, for the data d whose total bit length is (m + n) bits, (m
By using the minimum necessary gain control circuits 11 and 12 of +1) bits and n bits, a gain control circuit having a practically high bit length can be obtained. In this case, it suffices to prepare the gain control circuits 11 and 12 having the same precision as the effective bit length n, and it is not necessary to prepare those having (m + n) bit precision as in the conventional case.

Since the first gain control circuit 11 does not need to have a minimum gain of zero, the resistance attenuator of FIG. 5 can be used instead of the resistance attenuator of FIG.

The gain obtained through the two gain control circuits 11 and 12 has different step widths depending on the size of the data d,
In the region where d ₁ is 1 or more, the ratio is 1/2 ^n-1 or less,
It will have monotonicity in all areas.

When the gain control circuit handles an audio signal, a video signal, etc., a circuit having a precision of 14 to 16 bits is conventionally required. However, audio signals and video signals have a limit of human detection, and therefore cannot be detected even if they are finely controlled to some extent. In such a case, if a gain control circuit with an accuracy of 9 to 10 bits that is easily available is used, it is possible to perform control as fine as the detection limit.

FIG. 6 shows the control circuit 13 and the conversion circuit 14 in FIG.
An example of is shown.

The present embodiment shows a case where m = 4, where (m + 1) -bit data d corresponds to (m + n) -bit input data d.
The data d ₂ of ₁ and n bits is obtained. Further, the data d ₁₁ of FIG. 4 is created from the data d through the logic circuit, and the switch 1 provided for each bit of d ₂ via the selector controller 15 by this d _{11 is} generated.
By switching the contacts of 6 ₁ , 16 ₂ ... 16 _n ,
Data for d ₂ are obtained. For example, in FIG. 4, d = 0
In the case of 000111 ... 11 and d ₁ = 0, the higher 4 bits “0000” of d are added to the negative logic AND gate 17 to output “1” from the AND gate 17.
Is obtained. Together with the output "1" is the LSB of d _11, since the inverted by the inverter 18 is applied to the AND gate 19, the output of the AND gate 19 becomes "0". Therefore, the output of the NOR gate 20 to which the output "0" and the output "1" are added becomes "0", and the output of the AND gate 21 becomes "0". The output of the NOR gate 23 to which the output "0" and the outputs "0" and "1" of the AND gates 19 and 17 are added becomes "0", so that the output of the AND gate 23 becomes "0". The outputs “0”, “0” of the AND gates 23, 21, 19, 17
“0” and “1” are the data of d ₁₁ , and the MS of d
B becomes the MSB of d ₁₁ . Therefore, d ₁₁ is “000
1 ”is output. Also, depending on this d ₁₁ , the switch 16
_{Since 1 to} 16 _n are closed at the bottommost contacts in the figure,
"111 ...... 11" - "000 ...... 00" is obtained as d _2. Also, by selectively adding the upper bits of d to the inverter 24 and the negative logic AND gates 25 and 26 as shown, respectively, d ₁ = 1 to 4
Can obtain d ₁₁ and d ₂ shown in FIG. 4, respectively.

In FIG. 1, the gain control circuit 11 serving as the exponent part is arranged in the preceding stage of the gain control circuit 12 serving as the mantissa part, but the mantissa part may be arranged in the preceding stage.

As the gain control circuit 11, as shown in FIG. 7, an amplifier 2 having a gain of 1 / k times, 2 / k times ... 16 / k times, respectively.
7 _1-27 using a circuit consisting of ₅ and a switch ₂₈ 1 to 28 _5, may be configured to switch the selector controller 29 in accordance with the switch ₂₈ 1 to 28 ₅ to the data _{d 1.}

Further, as the gain control circuits 11 and 12, those configured by the multiplier D / A converter 6 and the operational amplifier 7 as shown in FIG. 8 and FIG. 9 or those configured by the PWM circuit are used. Of course it is good. Further, the gain control circuit 11 serving as an exponent part can be further divided into a plurality of stages.

Further, in FIG. 2, the effective bit length n is shifted by 1 bit with respect to the data d, but it may be shifted by a bit number larger than 1 bit. Although the effective bit length n is fixed, the minimum bit length n may be set for the data d. In that case, the maximum effective bit length is (n +
s), input data d of (m + n) bits may be divided into (m−s) bits and (m + s) bits, and may be supplied to the gain control circuits 11 and 12, respectively.

[Effect of the Invention] By securing the effective bit length, it is possible to perform digital control with substantially high bit length accuracy by using the low to medium bit circuit having this effective bit length accuracy.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a data diagram showing the principle of the present invention, FIG. 3 is a circuit diagram of a resistance attenuator applicable to the present invention, and FIG. FIG. 5 is a diagram showing a data relationship, FIG. 5 is a circuit diagram showing another embodiment of the resistance attenuator, FIG. 6 is a block diagram showing an embodiment of a control circuit, and FIG. 7 is an embodiment of a gain control circuit. Block diagrams, FIGS. 8 and 9 are block diagrams of a variable gain amplifier to which the present invention can be applied, and FIG. 10 is a circuit diagram of a multiplication type D / A converter. In the reference numerals used in the drawings, 11, 12 ... Gain control circuit 13 ... Control circuit.

Claims (1)

[Claims] 1. A plurality of gain control circuits controlled by a digital control signal. A predetermined effective bit length is determined from a digital input signal, and data for controlling one gain control circuit based on the effective bit length and the rest. And a control circuit for generating data for controlling the other gain control circuit based on the bit length of the gain control circuit.