JPH0644583B2 - Board-to-board connection terminal and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a terminal connection technique, and more particularly to an inter-board connection terminal and a method for manufacturing the same.

2. Description of the Related Art As a terminal connection method between a chip and a wiring board, a solder bump connection method (flip chip bonding method) is known as shown in JP-B-43-1654 or JP-B-43-28735. In this connection method, as shown in FIG. 1, a large number of electrodes b formed on the chip a and the terminal portions d of the wiring board c that supports the electrodes are directly joined by solder bumps e. Since the chip a and the wiring board c have different thermal expansion coefficients, shearing strain occurs in the solder bump e due to temperature change. Since this shear strain increases with an increase in the distance between the solder bump e and the chip center f, as shown in FIG. 2, the larger the chip size g, the smaller the number of thermal cycles the solder bump will reach. Therefore, the allowable shear strain amount limits the area in which the solder bumps can be arranged. For example, as shown in JP-A-50-137484 and JP-A-59-996, a silicon chip is used for ceramic wiring. When connecting to a board, the area where solder bumps can be placed has a radius of about 2.5 mm from the center of the chip. Therefore, in the conventional solder bump connection method, it is difficult to increase the number of terminals because the area in which the solder bumps can be arranged is limited to the vicinity of the chip center. Further, since the distance between the element in the chip located in the area beyond the area where the solder bump can be arranged and the solder bump becomes large, the wiring connecting between these becomes long and the wiring delay also increases. Further, as shown in FIG. 3, a gear gap deviation j between the chip and the wiring board due to the warp / waviness of the chip or the wiring board, which increases with the size of the chip (j ₁ at the center, j _{1 at} the end, If the gear tap is j ₂ , the gear tap deviation j
= J ₂ −j ₁ ) is difficult to be absorbed by only one step of the solder bump e, and in an extreme case, as shown in FIG. 4, a part of the terminal may be short-circuited. It was

Further, in the conventional one-step solder bump connection, the above gap deviation is not sufficiently absorbed and mechanical stress cannot be sufficiently absorbed, so that the back surface of the chip cannot be completely fixed to the heat sink, and a heat dissipation method is devised. It has the drawback of requiring a complicated cooling structure.

As a method of improving the drawbacks of such a conventional solder bump connection method, as shown in JP-A-59-996, through the through hole provided in the relay board, the solder terminal of the chip and the wiring board A method of connecting is proposed. That is, in this method, as shown in FIG. 5, in order to reduce the shear strain generated in the solder bump e covering the chip electrode b and the solder bump e ′ covering the wiring board electrode d, the chip a and the wiring board are reduced. relay substrate h having a coefficient of thermal expansion intermediate that of b
Solder, or Ag, C that has wettability to solder
A through hole i filled with u is provided, and the solder terminal (electrode) b of the chip a and the solder terminal (electrode) d of the wiring board c are connected via this. In this method,
As shown in (a), the relay board h is inserted between the chip a and the wiring board b, and the solders e and e ′ are fused and connected. However, when the solder is melted by heating, as shown in FIG. 6 (b), the upper and lower solders e, e ′ are solder or through-hole metal i ′ filled with Ag, Cu having wettability with respect to the solder.
There is a problem that the solder e on the upper side penetrates the through hole i and is integrated with the solder e ′ on the lower side. That is, since the height of the upper solder bump e ″ becomes lower, the shear strain becomes extremely large and the connection life becomes shorter than that of the first conventional example shown in FIG. Since the diameter of the bump e increases and the connecting solder bumps are electrically short-circuited with each other, it is necessary to widen the terminal interval, which makes it impossible to perform high-density terminal connection.

Objects of the Invention A first object of the present invention is to provide a highly reliable, large chip inter-board connecting terminal and a method for manufacturing the same, in which there are no restrictions on the area where solder bumps can be placed, and which has a small shear strain in the solder bumps. To provide.

A second object of the present invention is to provide a board-to-board connecting terminal of a large chip which can sufficiently absorb the deviation of the gear chip between the chip and the wiring board due to the warp / waviness of the chip or the wiring board, and a manufacturing method thereof. .

A third object of the present invention is to provide a small-sized and high-density multi-terminal connection method for large chips.

A fourth object of the present invention is to provide a connection method for a large chip, which has a short connecting portion, a small capacitance and inductance, and a short signal delay time at the connecting portion.

Configuration of the invention Description of the difference between the features of the invention and the prior art In order to solve the above-mentioned problems of the prior art, the present invention provides a metal material that has no wettability with respect to solder and has a diffusion preventing effect to the solder. Of the basic intermediary layer, which is sandwiched between the chips and the wiring board by sandwiching it with a wettable metal material, and then soldering it to the electrode terminals of the chip. The main feature is that the electrode terminals of the wiring board and the wiring board are connected. In the conventional technology, a structure in which the chip and each electrode / terminal of the wiring board are connected by a single-stage solder bump, or a relay board having a through hole filled only with a metal material that is wettable by solder is used. The structure of the present invention is different from the conventional technique because it has a structure for connecting the solder bumps of the chip and the solder bumps of the wiring board.

Description of Examples Generally, it is widely known that the connection life Nf of a solder bump portion has the following relationship with shear strain, material constants and structural dimensions. (For example, P. Lin “Design Considerations
for a Flip-Chip Joining Technique ”, Solid State
Technology, p.48, July 1970) Nf = A / γ ² γ = Δα · g ′ · ΔT / H where A is a constant determined by the solder material, γ is shear strain, and Δα is a chip. Difference in thermal expansion coefficient from the wiring board, g'is the distance from the chip center of the solder bump farthest from the chip center, ΔT is the temperature difference in each heat cycle, and H is
Is the height between the chip and the wiring board.

Therefore, in order to reduce the shear strain, it is necessary to increase the height of the solder bump. Ideally, several solder bumps should be stacked in a column to increase their height. However, when the solder bump and the chip or the wiring board are fusion-bonded, the pillar-shaped solder bump becomes one sphere due to the surface tension. Therefore, while maintaining the distance between the adjacent solder bumps at a certain constant value, the high solder bumps Is extremely difficult to obtain. Therefore, as a method of increasing the height of the solder bumps, the following method of stacking the solder bumps in multiple stages was devised.

FIG. 7 is a diagram for explaining the first embodiment of the present invention.
a is a chip, b is an electrode, c is a wiring board, d is a terminal portion (electrode), e is a solder bump, l is a metal layer such as Cu having wettability to solder, m is an intermediate metal layer l. A diffusion preventive layer such as W or Mo that is not wettable by solder, j
Is a ceramic that has no wettability to solder and is not electrically conductive. The multilayer metal layer l-m-l 'must be capable of joining the front and back surfaces to the solder and preventing the solder from diffusing and penetrating into the multilayer metal layer due to melting and integrating the upper and lower solders. Therefore, in the structure of the present invention, as shown in FIG. 7, a layer such as W or Mo having no wettability with respect to solder and having a diffusion preventing effect is used as a Cu layer having wettability with respect to solder. The structure inserted in the middle of is used.

Next, regarding the first embodiment of the present invention shown in FIG.
The manufacturing method will be described in order with reference to FIG. Fig. 8 (1)
As shown in Fig. 5, a ceramic green sheet j with a thickness of about 500 μm is formed with a diameter of 125 μm by a method such as punching.
A through hole k of a certain degree is opened and firing is performed. Next, as shown in FIG. 8 (2), the thickness of the through hole k is reduced to approximately 1 by inserting and firing Cu paste having wettability to solder.
200 μm. Next, as shown in FIG. 8 (3), m such as W paste having no wettability with respect to solder is inserted and baked on the Cu layer l to have a thickness of about 100 μm. Then, as shown in FIG. 8 (4), Cu paste 1'having a wettability with respect to solder is inserted and burned on the layer m of W so as to have a thickness of about 200 μm. Next, as shown in FIG. 8 (5), a metal mask q having an opening is aligned with the Cu (l ') portion on the upper surface, and a spherical SmPb is placed in the opening.
Alternatively, a solder ball e such as ImPb is put and a flux is applied. Next, the solder ball e is melted in this state through an electric furnace, and as shown in FIG.
u (l ') and solder ball e are joined to form solder bump e. Next, as shown in FIG. 8 (7), another metal mask q ′ is aligned with Cu (l) on the lower surface, solder balls e ′ are put in this portion, and a flux is applied.
As shown in (8), Cu (l) on the lower surface and solder balls e ′
To form a solder bump e ′. In order to obtain solder bumps with three or more steps, the solder bumps shown in FIGS. 8 (6) and 8 (8) are stacked and melted to form a multi-step solder bump as shown in FIG. 8 (9). The bumps s are formed. Next, using the multi-stage solder bumps s thus produced,
As shown in FIG. 8 (10), the electrode b of the chip and the terminal d of the wiring board are aligned so as to correspond to each other, and after applying the flux, the chip a and the wiring board c are connected to remove the flux. .

In the above-mentioned embodiment, the example using the ceramic support substrate has been described, but the inter-substrate connection terminals can be similarly formed by using the flexible resin support substrate or the polyimide support substrate. When a polyimide support substrate is used, the polyimide film can be removed by etching in the final step as described in the examples below.

FIG. 9 is a diagram for explaining the second embodiment of the present invention, in which a is a chip, b is an electrode, c is a wiring board, d is a terminal portion (electrode), e is a solder bump, and l, l. ′ And l ″ are metal layers such as Cu having wettability to solder, m is not wettable to solder sandwiched between metal layers l and l ′
A diffusion prevention layer such as Ti, and m is a heat resistant resin film such as polyimide.

Next, regarding the second embodiment of the present invention shown in FIG.
The manufacturing method will be described in order with reference to FIG. Fig. 10 (1)
As shown in Fig. 1, using polyimide film n of 12.5 to 25 μm as a base material, a vacuum deposition method or the like is used to deposit Cu on the upper surface.
(About 5 μm), Ti (about 0.2-1 μm), Cu (about 5 μm)
m), Ti (about 0.2 μm), in this order 1′-m−l−m ′
Then, deposit Cu (approximately 2 μm) l ″ on the lower surface. Then, as shown in FIG. 10 (2), a film-like resist (dry film) with a thickness of approximately 50 μm is laminated on both sides. Then, it is sandwiched between two pre-aligned masks, both sides are exposed, and a film-like resist o is developed using a developing solution such as trichloroethane to obtain a desired pattern. 10 As shown in Fig. (3), C on the lower surface
u (l ″) is etched with an aqueous solution of ammonium persulfate, which has selectivity for Ti, etc. Next, as shown in FIG. 10 (4), the film-like resist o on the upper surface is used as a mask to form Cu.
Etching Ti (m ') with an aqueous solution of hydrofluoric acid, etc., which has selectivity for Cu, etching Cu (l) with an aqueous solution of ammonium persulfate, and finally etching Ti (m) with an aqueous solution of hydrofluoric acid. Next, as shown in FIG. 10 (5), after removing the film-shaped resist o with acetone or the like,
Polyimide film using Cu (l ″) on the lower surface as a mask
Is etched with a hydrazine aqueous solution or the like to obtain an opening p. Next, as shown in FIG. 10 (6), a film-like resist is laminated and developed on the upper surface and the lower surface to obtain patterns o'and o "in which the opening p is slightly larger than this. After etching the lower surface Cu (l ″) with an aqueous solution of ammonium persulfate using the film-shaped resists o ′ and o ″ as masks, the film-shaped resist is peeled off using acetone or the like, as shown in FIG. 10 (7). Again, laminating the film-shaped resist o again,
Etch (l ') with an aqueous solution of ammonium persulfate. Next, as shown in Fig. 10 (8), T
After etching i (m '), the film-shaped resist o on the lower surface is removed using acetone or the like. Next, Fig. 10
As shown in (9), a metal mask q having an opening is aligned with the Cu (l) portion on the upper surface, and a spherical mask is formed in the opening.
A solder ball e such as SmPb or ImPb is put and a flux is applied. Next, the solder ball e is melted through an electric furnace as it is, and as shown in FIG. 10 (10), Cu (l) on the upper surface and the solder ball e are bonded to each other to form the solder bump e.
And Next, as shown in FIG. 10 (11), another metal mask q'is aligned with the film opening p, a solder ball e is put in this portion, and a flux is applied to the film opening p.
As shown in 2), Cu (l ′) on the lower surface and solder balls e
To form a solder bump e ′. Where Cu on the lower surface
The effect of (l ″) is to ensure the adhesion between the solder bump e ′ and the polyimide film n. In order to obtain a solder bump having three or more steps, FIG. 10 (10) and FIG. Fig. 10 shows the solder bumps shown in Fig.
Multi-stage solder bumps s as shown in (13) are formed. Next, using the multi-stage solder bumps s thus manufactured, as shown in FIG. 10 (14), the electrodes b of the chip and the terminals (electrodes) d of the wiring board are aligned so as to correspond to each other. Then, after applying the flux, the chip a and the wiring board c are connected to remove the flux. Further, after that, the polyimide film n can be removed by etching with hydrazine or the like. In this case, the solder bumps e are bonded only via the multilayer metal layers l-m-l '.

The present invention is not limited to the second embodiment shown here, and it is possible to change the manufacturing method, dimensions, etc. within the scope of the claims of the present invention. For example, as the multilayer metal layer, Cu-Cr-Cu, Cu
-CuCr alloy-Cr-CuCr alloy-Cu, Cu-CuTi alloy-Ti-Cu
Ti alloy-Cu, Pd-Ti-Pd, Pd-Cr-Pd or a structure in which these are laminated on each other, or Cu in contact with solder
In order to prevent the oxidation of Cu, the surface of Cu may be covered with Au. There is also a method in which a material having a different melting point is used for each solder bump in each stage and the difference in the melting points is used to facilitate fusion connection with a chip or a wiring board. That is, the solder bumps of each step are Sn _0.05 Pb _0.95 (melting point 31
4 ° C), In _0.50 Pb _0.50 (melting point 215 ° C), Sn _0.63 Pb _0.37 (melting point 184 ° C), so that the solder bumps only in the necessary parts are melted without melting the solder bumps fused in the previous process. Since it can be attached and unnecessary diffusion of solder to the metal layer can be prevented, deterioration of connection reliability can be suppressed. Further, as a method of manufacturing the solder layer, a vapor deposition method or the like may be used in addition to the method shown here.

Figure 8 (5), (7) and (10) or Figure 10 (9), (11)
As shown in (14) and (14), the number of melting times must be at least 3 times. FIG. 11 shows the number of times the solder is melted and the rate of occurrence of corrosion (the rate at which the solder diffuses and penetrates the metal layer due to melting and the upper and lower solders are integrated). From this, it can be seen that the structure in which the W or Ti layer is inserted in the middle of the Cu layer is superior to the structure having only the Cu layer without the occurrence of corrosion.

Figure 12 shows an analysis of the relationship between the number of stacked solder bumps and the shear strain generated at the solder bumps. By increasing the number of steps of the solder bumps, it is possible to reduce the shear strain, and it is understood from the above relational expression that the connection reliability is improved. Therefore, even if the chip size increases, by increasing the number of steps of the solder bumps correspondingly, the shear strain can be suppressed to an allowable value or less, so that the area where the solder bumps can be placed is limited. You can relax and place solder bumps anywhere on the chip.

Next, the reason why the shear strain can be reduced by the structure of the present invention will be described.

As described above, the shear strain of the solder bump portion generally decreases as the height thereof increases. In the structure having only the multilayer metal layer, as shown in Table 1, the coefficient of thermal expansion, the Young's modulus and the Poisson's ratio (related to the rigidity) of the solder bump and the metal layer Cu-Ti-Cu directly related to the shear strain are Even if there is a difference, the adjacent solder bumps are not connected by a relay board, etc., and the solder bumps of each row can be freely deformed, so the solder bumps can be multi-tiered and the height of the connection part can be increased. There is almost no loss of the effect of reducing shear strain due to the increase of

Further, in the structure having the relay substrate, a thin polyimide film is added to the metal layer Cu-Ti-Cu, and even if the thermal expansion coefficient of the relay substrate is larger than that of the chip and the wiring board, these Young's moduli are small, That is, since it is soft and has a small difference in material constant from the solder bumps, it is possible to reduce shear strain by increasing the height of the connection portion by arranging the solder bumps in multiple stages. Actually, the shear strain is deeply related to not only the coefficient of thermal expansion but also the Young's modulus and the Poisson's ratio (involved in the rigidity) indicating the hardness of the material. That is, as shown in the prior art, even if a relay substrate having an intermediate thermal expansion coefficient between the chip and the wiring board is used, the Young's modulus is large and hard, so that the shear strain cannot be reduced. However, even if the thermal expansion coefficient of the intermediate layer or the intermediate substrate is larger than that of the chip and the wiring board, as in the structure of only the intermediate layer shown in the present invention or the intermediate substrate structure in which a thin polyimide film supporting the intermediate layer is added, Since the solder bumps in each row can be independently deformed and the Young's modulus of the relay board is small and soft, it is possible to significantly reduce the shear strain by increasing the height of the connection portion by arranging the solder bumps in multiple stages.

Further, as shown in FIG. 13, there is no one-step structure or flexibility in absorbing the gap deviation between the chip and the wiring board due to the warp / waviness of the wiring board, which increases with the size of the chip. In the conventional two-stage structure using the relay substrate, only one solder bump can be absorbed, but in the structure of the present invention, a structure having only the intermediate layer or a thin polyimide film having flexibility even when the relay substrate is present. Therefore, it is possible to absorb almost the same number of steps as the solder bumps.

Table 2 shows SiC with a coefficient of thermal expansion intermediate between that of the chip and the wiring board.
A comparison of electrical characteristics and connection lengths by analysis between a conventional structure in which solder bumps are stacked in two stages and a structure of the present invention by using a relay substrate having a ceramic as a base material is shown.
In the structure of the second embodiment of the present invention, since the length of the connecting portion is short and the capacitance is small, the capacitance and inductance of the connecting portion can be made very small as compared with the conventional structure, and the signal propagation delay can be reduced. It is possible to connect terminals with a short time and a small amount of crosstalk between terminals, that is, with excellent electrical characteristics at high frequencies.

Further, as shown in FIG. 13, in the second embodiment of the present invention, since the structure of only the intermediate layer or the flexible thin polyimide film is used as the relay support substrate, the individual solder bumps are not deformed. It is flexible and can sufficiently absorb the deviation of the gear gap between the chip and the wiring board due to the warp / waviness of the wiring board, which increases with the size of the chip.

14 (a) and 14 (b) are cross-sectional views of an example of an integrated circuit package having a heat sink using the multi-stage solder bump of the second embodiment of the present invention. In FIG. 14, (a) shows a single chip case, and (b) shows a multi-chip case. Further, a is a chip, b is an electrode, c is a wiring board, d is a terminal portion, e is a solder bump, l-m-l 'is a multi-layer metal layer, n is a polyimide resin film, t is a heat sink fin, and u is a heat sink. Indicates a fixed portion by low melting point solder, and v indicates a terminal pin. Since flexible multi-stage solder bumps are used as the terminals of the chip, the back surface of the chip can be fixed to the heat sink with a low melting point solder or the like having good thermal conductivity. As a result, most of the heat generated from the chip is transferred to the radiating fins by conduction in the solid, and the thermal resistance of the heat transfer path from the chip to the radiating fins is small, realizing an integrated circuit package with excellent cooling performance. it can.

As shown in FIGS. 15 (a) and 15 (b), it is possible to realize an integrated circuit package having a structure in which the radiation fins in the above-mentioned integrated circuit package are replaced with cold plates having at least one conduit through which a coolant flows. Is. A multi-stage solder bump having a structure in which the flexible polyimide resin film of the relay support substrate is removed can also be used. Further, the chip can be fixed to the heat sink by using an adhesive material having good thermal conductivity.

EFFECTS OF THE INVENTION As described above, according to the present invention, in multi-terminal connection of a large chip, relaxation of the region where solder bumps can be arranged, reduction of shear strain of solder bumps, and warpage of wiring board It is possible to absorb the gap deviation between the chip and the wiring board due to the undulation. Therefore, the connection terminal of the present invention can be applied not only to the embodiment shown here, but also to the connection of wiring boards having a size larger than that of the chip.

Further, the present invention can realize an integrated circuit package having high heat dissipation characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view of a first example of a conventional solder bump connection method (flip chip bonding), and FIG. 2 is a chip size and connection in the conventional solder bump connection method as shown in FIG. Relationship with life, FIG. 3 is a relationship between chip size and gear deviation, and FIG. 4 is a diagram showing that a solder bump is short-circuited by a chip, a warp or undulation of a wiring board in a chip with a large size. FIG. 5 is a second conventional example, which is a cross-sectional view of a connection terminal having a structure having a relay substrate, and FIG. 6 shows a case where the conventional structure shown in FIG. FIG. 7 is a diagram showing a problem of moving to a substrate, and FIG. 7 is a first embodiment of the present invention, in which a ceramic is used as a relay support substrate and upper and lower solder bumps are formed of a metal layer with a diffusion prevention layer sandwiched therebetween. A cross-sectional view of FIG. 8 is shown in FIG. Manufacturing process example of the first embodiment of the present invention, FIG. 9 is a second embodiment of the present invention, a sectional view of a connection terminal using a polyimide resin film as a relay support substrate, FIG. 10 is shown in FIG. Manufacturing process example of the second embodiment of the present invention shown, FIG. 11 is a diagram showing the effect of reducing the corrosion occurrence rate by the diffusion prevention layer insertion, FIG. 12 is a multi-stage solder bump according to the present invention, shearing FIG. 13 shows that the strain can be reduced, and FIG. 13 is a cross-sectional view showing that the warp / waviness of the surface of the wiring board is absorbed by the multi-step solder bumps when the structure of the second embodiment of the present invention is used. . FIG. 14 (a) is a single-chip integrated circuit package having a radiation fin, which shows the second embodiment of the present invention.
FIG. 14 (b) is a cross-sectional view of an example of an integrated circuit package for a multi-chip, and FIGS. 15 (a) and 15 (b) are cold pipes having at least one conduit through which a coolant flows through the heat radiation fins. Sectional drawing of the integrated circuit package for single chips and multichips of the structure changed into the plate. a is a chip b is an electrode c is a wiring board d is a terminal portion (electrode) e is a solder bump l-m-l 'is a multi-layer metal layer l and l'is a metal layer such as Cu having wettability to solder m is a solder A metal support layer such as W or Ti that prevents the diffusion of n is a relay support substrate t made of ceramic or a flexible polyimide resin film that has no wettability to solder and is not electrically conductive. Cold plate u having at least one or more u is a low melting point solder or an adhesive having high thermal conductivity

Claims (8)

[Claims] 1. A first electrode formed on the surface of a first substrate, the surface of which is made of a metal having wettability to solder, and a surface of a second substrate which is arranged so as to face the first electrode. In a board-to-board connecting terminal that forms a current path by connecting the upper second electrodes to each other with solder bumps, there is no wettability to solder between thin metal layers having wettability to solder, and solder A solder bump intermediary portion sandwiching an intermediate layer made of a metal that does not alloy with
A first and a second solder bump which are arranged on both sides of the solder bump intermediary portion so as to face each other, and an end portion of the first solder bump opposite to the intermediary portion is provided with the first electrode. And an end portion of the second solder bump opposite to the intermediary portion is connected to the second electrode. 2. The inter-board connection terminal according to claim 1, wherein in the inter-board terminal, the melting points of the first and second solder bumps are different. 3. A first electrode formed on the surface of the first substrate, the first electrode being made of a metal having wettability to solder, and a second substrate surface arranged so as to face the first electrode. In the inter-board connecting terminal in which the upper second electrodes are connected by solder bumps to form a current path, there is no wettability to solder between thin metal layers having wettability to solder, and Solder bump intermediary portions sandwiching an intermediate layer made of a metal that is not alloyed with solder are stacked in multiple stages at predetermined intervals in a direction perpendicular to the main surface of the intermediary portion, and between the solder bump intermediary portions described above. And a solder bump having the same or different melting point is inserted between the solder bump intermediary portion of the lowermost layer and the first electrode and between the solder bump intermediary portion of the uppermost layer and the second electrode. Connection terminal. 4. The solder bump intermediary portion comprises a plurality of solder bump intermediary portion groups which are discretely arranged at predetermined intervals in a plane parallel to the main surface of the solder bump intermediary portion. Claims 1 and 2
The board-to-board connection terminal according to any one of items 1 and 2. 5. A step of forming a through-hole in a supporting substrate which is not wettable by solder and has an insulating property, and the through-hole is selectively filled with a first metal having wettability by solder. At least forming a first metal layer, and having no wettability to solder on the first metal layer,
And a step of forming a second metal layer made of a second metal that does not alloy with solder, and a third metal layer made of the first metal on the second metal layer.
And a step of forming a metal layer of the above-described first, second, and third metal layers to form a solder bump intermediary portion, and a solder bump intermediary portion is provided directly above the mask having a through hole. After arranging the minute solder balls, heating and melting, then cooling, to form a solder bump fixed to the upper surface of the solder bump intermediary portion, and directly below the solder bump intermediary portion, through a mask having a predetermined through hole After arranging the fine solder balls, heating and melting, and then cooling to form a single-layer basic structure having solder bumps fixed on the upper and lower surfaces of the solder bump intermediary portion, and the single-layer basic structure or the single-layer basic structure. A multilayer structure in which a plurality of layers of the basic structure are laminated and then the solder bumps are heated and melted and then fixed is provided between the first substrate having the first electrode and the second substrate having the second electrode. Insert After heating and melting the solder bumps, the preparation of inter-board connection terminals, characterized in that it consists of the steps of allowed to connecting between the by allowed to cool first and second electrodes. 6. A first metal layer made of a first metal having a wettability with solder on a first main surface of a supporting substrate having an insulating property, and an alloy having no wettability with solder and being alloyed with solder. The second metal layer made of the second metal, the third metal layer made of the first metal, and the fourth metal layer made of the second metal are sequentially stacked, and the first metal is placed on the second main surface. A step of forming a fifth metal layer consisting of, a step of applying a resist on the fourth metal layer to form a mask after pattern formation, and etching the second, third, and fourth metal layers with the mask, The resist is applied to the fifth metal layer provided on the second main surface to form a mask after patterning, and the second, third, fourth
A step of forming an opening having a smaller area than that of the remaining portion in the fifth metal layer on the back surface of the remaining portion of the metal layer, and etching the support substrate from the opening of the fifth metal layer to reach the first metal layer. Forming a hole, forming a resist residual pattern having an area slightly larger than the opening of the fifth metal layer, etching the fifth metal layer using the resist pattern as a mask, and the fourth metal layer With the mask as a mask, etching the first metal layer, removing the fourth metal layer, removing the resist, and removing the remaining portions of the first, second, and third metal layers on the first main surface. A step of arranging a minute solder sphere directly above a mask, heating and melting, and then cooling and fixing to form a single-layer basic structure with the solder pump fixed, and the single-layer basic structure or the single-layer basic structure. After laminating a plurality of layers of the structure, the solder bumps are melted by heating and then fixed, and the multilayer structure is inserted between the first substrate having the first electrode and the second substrate having the second electrode. And a step of disposing fine solder balls on the lower surface of the single-layer or multi-layer structure, heating and melting, and then cooling to connect the first and second electrodes to each other. Method for manufacturing inter-connection terminals. 7. The method for manufacturing an inter-board connection terminal according to claim 5, wherein the support substrate is a ceramic thin plate, a polyimide film, or a flexible insulating plate. . 8. A first metal layer made of a first metal having wettability with solder, and a second metal layer made of a second metal having no wettability with solder and not alloying with solder. A step of preparing a three-layer structure by sequentially stacking a third metal layer made of the first metal, a step of discretely arranging the three-layer structure on a polyimide support substrate, and polishing both surfaces of the support substrate. The step of exposing the first and third metal layers, the first, second, and third metal layers are used as a solder bump intermediary portion, and a predetermined through hole is provided directly above the solder bump intermediary portion. After arranging the minute solder balls through the mask, heating and melting, and then cooling, forming a solder bump on the upper surface of the solder bump intermediary portion, and immediately below the solder bump intermediary portion, through a mask having a predetermined through hole And place a small solder ball A step of heating and melting after placing, and then cooling to form a single-layer basic structure to which the solder bumps are fixed, and the above-mentioned single-layer basic structure, or a solder bump after laminating a plurality of layers of the single-layer basic structure. A plurality of structures, which are heated and melted, and then cooled and fixed, are attached to a first electrode having a first electrode.
The second substrate having the second electrode and the second electrode,
A step of connecting the first and second electrodes by heating and melting the solder bumps to cool the solder bumps, and dissolving and removing the polyimide film by permeating the structure into an aqueous hydrazine solution, and only the solder bumps and solder bump intermediary parts And a step of allowing the laminated structure consisting of to remain, and a method for manufacturing an inter-board connecting terminal.