JPH0641392Y2 - Phase comparator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a phase comparator used in an analog phase locked loop circuit including a voltage controlled oscillator, and particularly to a burst digital signal as well as a continuous digital signal. The present invention relates to a phase comparator which can obtain a control signal such as a clock.

(Prior Art) For example, in digital signal communication, an analog automatic phase-locking circuit (APLL) is used to reproduce a control signal such as a clock signal from a digital signal used as a transmission or reception signal. Such an APLL includes a voltage controlled oscillator (VCO), a phase comparator and a loop filter.

As a phase comparator used in such an APLL, for example, there is an IC called MC4044 manufactured by Motorola Co. as disclosed in the literature (“How to use PLL-IC”, P.171-172, P.171-172).

Further, as other examples of the phase comparator, those using an Ex-OR (exclusive OR) and those using a D type flip-flop circuit (D-FF) have been known.

(Problems to be Solved by the Invention) However, the conventional phase comparator using the MC4044 performs frequency detection to perform phase comparison. Therefore, when a clock or the like is reproduced from a non-periodic signal such as a burst signal or a PCM (pulse code modulation) signal, if such a signal is input as it is, there is a problem that phase comparison cannot be performed. It was

Further, as is well known, the phase comparator using the Ex-OR has a problem that an error in phase comparison occurs when the duty of the pulse input to the phase comparator changes.

Further, the phase comparator using the D-FF has a structure in which the burst signal is input to the clock terminal of the D-FF and the output signal of the VCO is input to the D terminal of the D-FF. As the comparison output in the section, the phase comparison output immediately before the burst signal is disconnected is output as it is. Therefore, there is a problem that an error in phase comparison is enlarged.

An object of the present invention is to solve the above-mentioned problems and to provide a phase comparator which does not cause a control error not only for a continuous digital signal but also for a burst digital signal.

(Means for Solving the Problems) In order to achieve this object, according to the present invention, the phase difference between the output signal from the voltage controlled oscillator and the continuous or burst digital signal is compared to obtain the control signal. In a phase comparator that outputs a lead pulse indicating the lead or lag of the phase of the output signal from the voltage-controlled oscillator with respect to the digital signal, with reference to the change point at the rise or fall of the continuous or burst digital signal. And a pulse generation circuit that generates a delay pulse, a pulse generation circuit that generates a advance pulse and a delay pulse that represent the advance and delay of the phase, and a delay advance pulse and a delay delay pulse that are delay pulses of the advance pulse and the delay pulse. And a control signal having the following (a), (b), (c), (d) and (e): Characterized in that comprises a power circuit.

(A) A first switch element having one terminal connected to a first reference voltage point and turned on / off by the advance pulse, a second switch element turned on / off by the delay advance pulse, and turned on by the delay delay pulse A series circuit of a third switch element that is turned off and a fourth switch element that has one terminal connected to the second reference voltage point and that is turned on and off by the delayed pulse.

(B) A first capacitor connected between the connection point of the first and second switch elements and the second reference voltage point.

(C) A second capacitor connected between the connection point of the third and fourth switch elements and the second reference voltage point.

(D) A third capacitor connected between the connection point of the second and third switch elements and the second reference voltage point.

(E) A control signal output terminal connected to the connection point of the second and third switch elements.

In carrying out this invention, it is preferable that the above-mentioned second reference voltage point is grounded.

In implementing the invention, in the control signal output circuit described above, the first reference voltage point is a positive voltage point, and the second reference voltage point is a negative voltage having the same voltage as the first voltage point but a different polarity. A voltage point, an integrator may be connected to the connection point of the second and third switch elements instead of the third capacitor, and the control signal output terminal may be connected to the output terminal of the integrator. .

Further, it is preferable that the delay circuit described above is configured by a first delay element that outputs the delay pulse of the advance pulse and a second delay element that outputs the delay pulse of the delay pulse. .

(Operation) The operation of the phase comparator having such a configuration will be described with reference to FIG. A detailed description of the connection relationship between the constituent components shown in FIG. 1 will be given later.

The pulse generation circuit 20 compares the phase of the continuous or burst digital signal with the phase of the output signal of the voltage controlled oscillator. Here, the pulse generation circuit 20 of the present invention
Generates a lead pulse and a lag pulse representing the lead or lag of the phase of the output signal from the voltage controlled oscillator with respect to the digital signal with reference to the change point at the rising or falling of the continuous or burst digital signal. Therefore, if the burst digital signal is disconnected, the pulse generating circuit does not output the leading pulse and the lagging pulse. Therefore, the delay circuit 30
Also, if the burst digital signal is cut off,
Delayed advance pulse and delayed delay pulse are not output. Then, as described above, when none of the leading pulse, the lagging pulse, the lagging leading pulse, and the lagging delay pulse is output, the first to fourth switching elements of the control signal output circuit 40 do not change their states, so the second switching element 43 And a third switch element
The potential of the third capacitor 55 (in another example, the integrator 103 (FIGS. 4 and 5)) connected to the connection point of 45 does not change, so that the control signal does not change. On the other hand, when a continuous digital signal is input, or when the burst digital signal is not broken, the pulse generation circuit 20 outputs the phase of the output signal of the voltage controlled oscillator to the digital signal described above. If it is ahead of the phase of
The advance pulse S ₁₀ can be sequentially generated. In addition, the progressive pulse sequentially generated by the first delay element 31.
Delayed advance pulses S ₁₁ corresponding to S ₁₀ are sequentially generated. The leading pulse S ₁₀ turns on / off the first switching element 41, and the delayed leading pulse S ₁₁ turns on / off the second switching element 43. By the way, a capacitor 51 (referred to as a first capacitor 51) having a capacitance C ₁ is connected between the connection point P _{1 of} the first switching element 41 and the second switching element 43 and, for example, the ground, and The terminal of the one switch element 41 on the opposite side to the second switch element 43 is connected to a first reference voltage point (voltage source) at which a voltage V volt is obtained, for example. Furthermore, a connection point P _{2 of} the second switch element 43 and the third switch element 45,
For example, a smoothing capacitor 55 (referred to as a third capacitor 55) having a capacitance C ₂ is connected to the ground.

Therefore, when the first switch element 41 is turned on in response to the advance pulse S ₁₀ , the first capacitor is turned on by the voltage source described above.
51 is charged. Next, when the second switch element 43 is turned on in response to the delayed advance pulse S ₁₁ which is generated with a certain time delay from this advance pulse, the charge of the first capacitor 51 passes through the second switch element 43 to the third state. Charge the capacitor 55.

When the advance pulse S ₁₀ is generated, the charging / discharging operation of the first capacitor 51 is repeated as described above, and
The third capacitor 55 is sequentially charged. Therefore, the output terminal
The voltage level at 61 is boosted. For example, the signal from the output terminal 61 can be used as a control signal for correcting that the phase of the output signal of the voltage controlled oscillator leads the phase of the digital signal and synchronizing them.

On the other hand, the pulse generation circuit 20 can sequentially generate the delay pulse S ₂₀ when the phase of the output signal of the voltage controlled oscillator is behind the phase of the digital signal. Further, the second delay element 33 sequentially generates the delayed delay pulse S ₂₁ corresponding to the sequentially generated delayed pulse. The delay pulse S ₂₀ turns on / off the fourth switch element 47, and the delay delay pulse S ₂₁ turns on / off the third switch element 45. By the way, a capacitor 53 having a capacitance C ₁ (referred to as a second capacitor 53) is connected between a connection point P _{3 of} the third switch element 45 and the fourth switch element 47 and, for example, the ground. Therefore, when the fourth switch element 47 is turned on in response to the delayed pulse S ₂₀ , the electric charge of the second capacitor 53 is discharged via the fourth switch element 47. Next, when the third switching device 45 according to the delay delayed pulse S ₂₁ that is delayed a certain period of time from the delay pulse is turned on, the charge of third capacitor 55 through the third switching element 45 second It is moved to the condenser 53 and charges the second condenser 53.

When the delayed pulse S ₂₀ is generated, the charging / charging operation of the second capacitor 53 is repeated as described above, and
The third capacitor 55 is sequentially discharged. Therefore, the output terminal
The voltage level at 61 is stepped down. The signal from the output terminal 61 can be used as a control signal for correcting, for example, the phase of the output signal of the voltage controlled oscillator being behind the phase of the digital signal and synchronizing them.
Further, in the present invention, a predetermined delay circuit 30 and a predetermined control signal output circuit 40 are provided. And this delay circuit 30
Since the second switching element 43, the third switching element 45, the first capacitor 51 and the second capacitor 53 of the control signal output circuit 40 are provided, the potential of the third capacitor 55 (integrator 103 in another example) is It is changed in an analog manner and an analog control signal is obtained. That is, if the delay circuit 30 and the second switch element 43 of the control signal output circuit 40, the third switch element 45, the first capacitor 51 and the second capacitor 53 are not provided, the first switch element 41 is turned on. At the moment when the
Further, the third capacitor 55 becomes the second reference voltage (for example, ground) at the moment when the fourth switch element 47 is turned on, so that only a binary control signal is obtained.

(Embodiment) An embodiment of the phase comparator of the present invention will be described below with reference to the drawings.

First Embodiment <Configuration of Phase Comparator> FIG. 1 is a circuit diagram showing the configuration of a first embodiment of the phase comparator of the present invention.

In FIG. 1, 11 indicates a first input terminal.

This input terminal 11 is connected to a voltage controlled oscillator (not shown below,
It may be called VCO). 13 indicates a second input terminal. This input terminal
For example, a certain continuous digital signal or a burst digital signal can be input to 13. This specific signal is, for example, PCM in digital signal communication.
These are transmission / reception signals (hereinafter referred to as reference signals). The input terminals 11 and 13 correspond to the input terminals of the phase comparator of this invention.

Reference numeral 20 denotes a pulse generation circuit for generating a leading pulse S ₁₀ and a lagging pulse S ₂₀ , respectively, which represent leading and lagging of the phase of the output signal of the VCO with respect to the reference signal.

The pulse generation circuit 20 in this embodiment is a logical product circuit 21.
And 23 and an inverter 25. Then, the connection between them is made as follows.

One input terminal of the AND circuit 21 and the input terminal of the inverter 25 are connected to the first input terminal 11. The output terminal of the inverter 25 is connected to one input terminal of the AND circuit 23. The other input terminal of each of the AND circuits 21 and 23 is connected to the second input terminal 13.

Reference numeral 30 denotes a delay circuit for outputting the delay pulse of the lead pulse and the delay pulse described above. In the case of this embodiment, the delay circuit 30 includes a first delay element 31 and a second delay element 33. Each of these delay elements has a delay time of W, for example. The output terminal of the AND circuit 21 is connected to the input terminal of the first delay element 31, for example. The output terminal of the AND circuit 23 is connected to the input terminal of the second delay element 33, for example. Therefore, the first delay element 31 outputs the delayed advance pulse S ₁₁ of the advanced pulse S ₁₀ , and the second delay element 33 outputs the delayed pulse S _20.
The delay delay pulse S _{21 of} is output. Depending on the design, one delay element may be configured and used as the leading pulse and the lagging pulse in common.

Reference numeral 40 denotes a control signal output circuit. The control signal output circuit 40 in the case of the first embodiment is a first switch element indicated by 41, a second switch element indicated by 43, a third switch element indicated by 45, and a third switch element indicated by 47. With four switch elements. Further, in this case, the respective switching elements are connected in series in the order of the first, second, third and fourth.
Further, a first reference voltage source that outputs, for example, a voltage V volt is connected to the terminal of the first switch element 41 opposite to the terminal connected to the second switch element 43. Further, the terminal of the fourth switch element 47 opposite to the terminal connected to the third switch element 45 is connected to the second reference voltage source, which is ground in this case.

The first switch element 41 of this embodiment is opened / closed according to the voltage state of the output terminal of the AND circuit 21 of the pulse generation circuit 20, that is, the signal S ₁₀ . In this case, the switch element 41 is in a conductive (ON) state when the signal S ₁₀ is at a high level, and is in an open (OFF) state when the signal S ₁₀ is at a low level. The second switch element 43 is a first delay element.
It is opened and closed by the voltage state of the output terminal of 31, that is, the signal S ₁₁ . Third switching device 45, the voltage state of the output terminal of the second delay element 33, i.e. opened and closed by the signal S _21.
The fourth switch element 47 is an AND circuit of the pulse generation circuit 20.
It is opened and closed by the voltage state of the output terminals of 23, that is, the signal S ₂₀ . Each operation of the second, third and fourth switch elements with respect to the applied voltage is preferably configured to operate similarly to the first switch element 41. It should be noted that these switch elements can be configured with suitable electronic elements such as NPN transistors.

Also, 51 the first capacitor having a capacitance for example C _1, 53 is a second capacitor having a capacitance for example C _1, 55 denotes a third capacitor having a capacitance for example, C _2. One terminal of the first capacitor 51 is connected to the connection point P ₁ between the first switching element 41 and the second switching element 43. One terminal of the second capacitor 53 is a connection point between the second switching element 43 and the third switching element 45.
Connect to P ₂ . One terminal of the third capacitor 53 is connected to the connection point P ₃ between the third switch element 45 and the fourth switch element 47. Also, the other terminal of each of these capacitors is connected to ground (the second reference voltage point).

Reference numeral 61 denotes an output terminal of the phase comparator of the present invention, which outputs the charging voltage of the second capacitor 53 in this embodiment.

<Example of Use of Phase Comparator> An example in which the phase comparator of the present invention described with reference to FIG. 1 is applied to, for example, a phase locked loop circuit for performing clock recovery of a burst PCM signal will be described.

FIG. 2 is a diagram showing a timing extraction circuit which detects a rising edge of a bipolar signal in a burst PCM signal and outputs a pulse based on the detection result. It should be noted that this circuit is an example of the timing extraction circuit used when the clock is reproduced from the PCM signal, and a circuit having another configuration may be used.

FIG. 3 is a diagram showing a timing chart for explaining the operations of the phase comparator and the timing extraction circuit.

To the input terminal 73 of the timing extraction circuit 71 shown in FIG.
Bipolar burst signal S ₁ (see Fig. 3 (A))
Enter. The signal S ₁ is converted into a signal S ₂ (see FIG. 3B) showing the absolute value or the squared value of this signal by the square circuit 75 provided in the timing extraction circuit 71. Signal S ₂
Is input to the input terminal of the delay element 77 provided in the timing extraction circuit and one input terminal of each of the exclusive OR 79 and the logical product circuit 81. Also, the output of the delay element 77 is exclusive ORed.
Input to the other input terminal of 79. Further, the output of the exclusive OR 79 is input to the other input terminal of the AND circuit 81. The timing extraction signal S ₃ (see FIG. 3C) is obtained at the output terminal 83 of the AND circuit 81.

When this timing extraction signal S ₃ is input to the input terminal 13 of the phase comparator of the present invention which has already been described with reference to FIG. 1, this signal S ₃ is an AND circuit of the pulse generation circuit 20 of the phase comparator.
Input to one of the input terminals 21 and 23 respectively. On the other hand, when the output signal S ₄ from the VCO (see FIG. 3 (D)) is input to the input terminal 11 of the phase comparator, this signal S ₄ is output from the inverter 25 of the pulse generation circuit 20 and the AND circuit 21. It is input to the other input terminal. Further, the output of the inverter 25 is input to the other input terminal of the AND circuit 23.

Here, when the output signal S ₃ of the timing extraction circuit and the output signal S _{4 of the} VCO are compared in the section X shown in FIG. ₃ , the phase of the signal S ₄ leads the phase of the signal S ₃ . Therefore, the pulse generation circuit 20 outputs a pulse S ₁₀ (see FIG. 3 (E)) that advances through the AND circuit 21. or,
When the signal S ₁₀ indicates a high level, the first switching element 41 is turned on, so that the first capacitor 51 having a capacitance of C ₁ has a charge of Q from the power source of the voltage V via the first switching element 41. Only _{1 is} charged and the terminal voltage of this first capacitor 51 is V
become. Next, when the signal S ₁₀ becomes low level and the delayed advance pulse S ₁₁ of the signal S ₁₀ becomes high level, the second switch element 43 is turned on this time. At this time, the electric charge charged in the first capacitor 51 charges the third capacitor 55 having a capacity of C ₂ via the second switch element 43. The terminal voltage V ₂ of the third capacitor 55 at this time is represented by V ₂ = VC ₁ / (C ₁ + C ₂ ) = Q ₁ / (C ₁ + C ₂ ).

When the pulse generation circuit 20 continues to output the pulse, the charging / discharging operation as described above is repeated. At this time, the signal waveform at the switch-side terminal (position P ₁ ) of the first capacitor 51 becomes a waveform as shown in the region corresponding to the section X in FIG. 3 (I). On the other hand, the signal waveform at the output terminal of the phase comparator becomes a waveform as shown in the region corresponding to the section X in FIG. 3 (K).

Next, the operation of the phase comparison circuit in the section Y shown in FIG. 3, that is, in the non-signal section in the burst-shaped reference signal will be described. Since the reference signal is in a non-signal state, the input terminal 13 of the phase comparator becomes low level. Therefore, the outputs of the AND circuits 21 and 23 of the pulse generation circuit 20 are both at the low level, so that the second switch element 43 and the third switch element are
Both 45 are turned off. Therefore, the output terminal of the phase comparator holds the voltage charged in the third capacitor 55 (the voltage indicated by V ₃ in FIG. 3K) in association with the final leading pulse in the section X. . As described above, the phase comparator of the present invention holds a certain control voltage V ₃ charged in the third capacitor 55 even if the VCO free-run oscillation frequency has an error when the reference signal is in a non-signal state. It Because of this
A large phase error does not occur even in the non-signal section of the reference signal.

Next, in the section Z shown in FIG. ₃ , when comparing the output signal S ₃ of the timing extraction circuit and the output signal S _{4 of the} VCO,
The phase of signal S ₄ lags the phase of signal S ₃ . Therefore,
The pulse generation circuit 20 outputs a delayed pulse S ₂₀ (see FIG. 3 (F)) via the AND circuit 23. When this signal S ₂₀ indicates a high level, the fourth switch element 47
Is turned on, the second capacitor 53 is completely discharged. Next, the signal S ₂₀ goes low and the signal S
_When the delayed delay pulse S _{21 of 20} becomes high level, the third switch element 45 is turned on this time. At this time, section X
In, the electric charge charged in the third capacitor 55 is discharged to the side of the second capacitor 53 having a capacitance of C ₁ via the third switch element 45, and the second capacitor 53 is discharged. Therefore,
The output voltage of the output terminal 61 of the phase comparator at this time is from V ₃ to V ₄
(See Fig. 3 (K)).

When the delayed pulse is continuously output from the pulse generation circuit 20, the charging / discharging operation as described above is repeated. At this time, the signal waveform at the switch-side terminal (position P ₃ ) of the second capacitor 53 becomes a waveform as shown in the area corresponding to the section Z in FIG. 3 (J). On the other hand, the signal waveform at the output terminal of the phase comparator becomes a waveform as shown in the region corresponding to the section z in FIG. 3 (K).

Second Embodiment FIG. 4 is a circuit diagram showing a second embodiment of the phase comparator of the present invention, particularly a modification of the control signal output circuit 40.

The phase comparator of the second embodiment, the pulse generation circuit 20,
The delay circuit 30 and the first to fourth switch elements 41, 43, 45 and 47
And the first and second capacitors 51 and 53 in the same connection relationship as the phase comparator of the first embodiment. Further, the phase comparator of the second embodiment, in the control signal output circuit 40, at the connection point P ₂ of the second and third switch elements 43, 45, instead of the third capacitor 55 of the first embodiment, Capacitor 10
An integrator composed of 1 and the operational amplifier 103 is added. This connection is made as follows. Connection point between the negative input terminal of the operational amplifier 103 and the second and third switch elements
P ₂ is connected, and the capacitor 101 is connected between the output terminal of the operational amplifier 103 and the negative input terminal. Also, operational amplifier 1
Apply half the first reference voltage to the positive input terminal of 03.

According to the phase comparator of the second embodiment having such a configuration, the influence of load fluctuation can be reduced.

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the phase comparator of the present invention, particularly a modification of the control signal output circuit 40.

The phase comparator of the third embodiment, the pulse generation circuit 20,
The delay circuit 30 and the first to fourth switch elements 41, 43, 45 and 47
And the first and second capacitors 51 and 53 as in the phase comparator of the first embodiment. However, the phase comparator of the third embodiment, in the control signal output circuit, the first reference voltage point connected to the first switch element 41 is a positive voltage point having a predetermined value, and is connected to the fourth switch element 47. The second reference voltage point is a negative voltage point having the same absolute value and the opposite polarity as the positive voltage point. Further, the terminals of the first and first capacitors 51 and 53 opposite to the terminals connected to the switch element are connected to a third reference voltage point, for example, ground. Further, at the connection point P ₂ of the second and third switching elements 43, 45, instead of the third capacitor 55 in the first embodiment, the capacitor 10
An integrator composed of 1 and operational amplifier 103 is added. This connection is made as follows. The negative input terminal of the operational amplifier 103 is connected to the connection point P _{2 of} the second and third switch elements, and the capacitor 101 is connected between the output terminal of the operational amplifier 103 and the negative input terminal. Further, the positive input terminal of the operational amplifier 103 is connected to the ground.

According to the phase comparator of the third embodiment having such a configuration, the output voltage from the phase comparator can be output centered on zero volt.

In each of the above-described embodiments, the example in which the output signal level from the phase comparator rises in response to the leading pulse and the output signal level falls in response to the delayed pulse has been described. However, even in the reverse state of the embodiment, that is, the phase comparator having a configuration in which the output signal level of the phase comparator increases according to the delayed pulse and the output signal level decreases according to the leading pulse, If the circuit configuration of the subsequent stage of the phase comparator is changed accordingly, the same effect as that of the embodiment can be expected. As such an example, for example, it is conceivable that each output terminal of the AND circuits 21 and 23 is connected to a delay element opposite to each delay element of the embodiment. Further, in the above-described embodiment, the bipolar signal is used as the input digital signal, so the timing extraction circuit shown in FIG. 2 is used. However, when the input digital signal is a unipolar signal, "0" or Since the signal change of "1" is obtained, the timing extraction circuit is not particularly necessary. However, even if it is a unipolar signal, if the duty ratio is 50% or more, the first switching element and the second switching element are operated simultaneously, so it is necessary to use one edge of the signal. do. This allowance can be performed by a known circuit such as the circuit shown in FIG. 2 (although the square circuit is not always necessary).

Further, it is obvious that the circuit parts described in the above-mentioned respective embodiments can be replaced with other circuit parts within the range in which the object of the present invention can be achieved.

Further, it is apparent that the connection relationship of the circuit components described in each of the above-described embodiments can be changed within the range in which the object of the present invention can be achieved.

(Effect of the Invention) As is apparent from the above description, according to the phase comparator of the present invention, the lead pulse and the delay pulse generated from the pulse generating circuit are generated based on the phase difference between the output signal of the VCO and the reference signal. The charge and discharge of the capacitor can be controlled by the pulse and the delayed advance pulse and the delayed delay pulse generated in the delay circuit according to these advanced and delayed pulses, and an analog phase comparison output can be obtained. Further, the charging voltage of the above-mentioned capacitor can be continuously output as a phase comparison output even in the no signal section of the burst signal. Therefore, even if there is an error in the VCO free-run frequency, a large phase error does not occur,
Moreover, there is no loss of synchronization.

Therefore, it is possible to provide a phase comparator which does not cause a control error not only for a continuous digital signal but also for a burst digital signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a phase comparator of this invention, FIG. 2 is a diagram showing a timing extraction circuit suitable for use with the phase comparator of this invention, and FIG. 3 (A). (K) are timing charts for explaining the operation of the phase comparator of the first embodiment of the present invention, FIG. 4 is a circuit diagram showing a second embodiment of the phase comparator of the present invention, and FIG. FIG. 6 is a circuit diagram showing a third embodiment of the phase comparator of the present invention. 11, 13 ... Phase comparator input terminal 20 ... Pulse generation circuit, 21, 23 AND circuit 25 ... Inverter, 30 ... Delay circuit 31 ... First delay element 33 ... Second delay element 40 ... Control signal output circuit, 41 ... First switch element 43 ... Second switch element, 45 ... Third switch element 47 ... Fourth switch element, 51 ... First capacitor 53 ... Second capacitor, 55 ... Third capacitor 61 ... Output terminal, 101 ... Capacitor 103 ... Operational amplifier.

Claims (4)

[Scope of utility model registration request] 1. A phase comparator which compares the phase difference between an output signal from a voltage controlled oscillator and a continuous or burst digital signal and outputs a control signal, wherein the continuous or burst digital signal rises or rises. A pulse generation circuit that generates a leading pulse and a lagging pulse that represent leading and lagging of the phase of the output signal from the voltage controlled oscillator with respect to the change point when falling, and a delay of the leading pulse and the lagging pulse. A delay circuit for outputting a delayed advance pulse and a delayed delay pulse, which are pulses, and a control signal output circuit having the following (a), (b), (c), (d) and (e): Characteristic phase comparator. (A) A first switch element having one terminal connected to a first reference voltage point and turned on / off by the advance pulse, a second switch element turned on / off by the delay advance pulse, and turned on by the delay delay pulse A series circuit of a third switch element that is turned off and a fourth switch element that has one terminal connected to the second reference voltage point and that is turned on and off by the delayed pulse. (B) A first capacitor connected between the connection point of the first and second switch elements and the second reference voltage point. (C) A second capacitor connected between the connection point of the third and fourth switch elements and the second reference voltage point. (D) A third capacitor connected between the connection point of the second and third switch elements and the second reference voltage point. (E) A control signal output terminal connected to the connection point of the second and third switch elements. 2. The phase comparator according to claim 1, wherein the second reference voltage point is grounded. 3. In the control signal output circuit, the first reference voltage point is a positive voltage point, the second reference voltage point is a negative voltage point having the same voltage as the first voltage point but different polarity, An integrator is connected to the connection point of the second and third switch elements instead of the third capacitor, and the control signal output terminal is connected to the output terminal of the integrator. The phase comparator according to claim 1, wherein the utility model is registered. 4. The delay circuit comprises a first delay element for outputting a delay pulse of the advance pulse and a second delay element for outputting a delay pulse of the delay pulse. The phase comparator according to claim 1 of the utility model registration claim.