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JPH0637314A - Thin-film transistor and manufacture thereof - Google Patents

Thin-film transistor and manufacture thereof

Info

Publication number
JPH0637314A
JPH0637314A JP18933492A JP18933492A JPH0637314A JP H0637314 A JPH0637314 A JP H0637314A JP 18933492 A JP18933492 A JP 18933492A JP 18933492 A JP18933492 A JP 18933492A JP H0637314 A JPH0637314 A JP H0637314A
Authority
JP
Japan
Prior art keywords
gate electrode
layer
electrode
lower layer
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18933492A
Other languages
Japanese (ja)
Other versions
JP3171673B2 (en
Inventor
Keiji Tarui
敬次 垂井
Tatsuo Morita
達夫 森田
Shuhei Tsuchimoto
修平 土本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP18933492A priority Critical patent/JP3171673B2/en
Publication of JPH0637314A publication Critical patent/JPH0637314A/en
Application granted granted Critical
Publication of JP3171673B2 publication Critical patent/JP3171673B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78627Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To facilitate the formation of a gate overlapping LDD by forming a gate electrode in two-layer structure of an upper layer and a lower layer and performing the ion implantation of impurities with both electrodes being used for a mask without equalling the width of both electrodes. CONSTITUTION:A gate electrode 5 of a lower layer is worked for a predetermined shape with a reactive ion etcher. Then, the width of an electrode for the gate electrode 5 of a lower layer is made to be 5mum. After that, a polysilicon film to act as a gate electrode 7 of an upper layer is formed on the whole surface of a glass substrate 1 including the electrode 5 of a lower layer. And then the width of an electrode for the gate electrode 7 of an upper layer is so worked as to become 3mum with the center line of the electrode width of the gate electrode 5 of a lower layer being aligned with that of the gate electrode 7 of an upper layer. Next, P-type ion implantation is so performed as to form a high concentration region in a gate electrode 6 and at the same time to form an impurity region 10 having an LDD structure in the polysilicon film. Since the gate electrode width of an upper and a lower layer is not the same, a gate overlapping LDD structure may be easily formed with once implantation of impurity ions being performed by using the gate electrode of an upper and a lower layer for a mask.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は薄膜トランジスタ及び
その製造方法に関するものであり、特に液晶ディスプレ
イ等の絶縁性基板上に作製される薄膜トランジスタ及び
その製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor manufactured on an insulating substrate such as a liquid crystal display and a manufacturing method thereof.

【0002】[0002]

【従来の技術】近年、液晶ディスプレイの性能向上はめ
ざましく、特に、絵素毎にダイオードや薄膜トランジス
タ等のスイッチング機能をもたせたアクティブマトリク
ス型液晶ディスプレイは画質の向上、画面サイズの大型
化に大きく貢献している。絵素毎に設けた薄膜トランジ
スタは絶縁性の基板上に、トランジスタの活性層として
非晶質シリコンを用いたものが多く、大面積化が可能で
あり、プロセス温度が低温(〜350℃)であるといっ
た長所を有している。
2. Description of the Related Art In recent years, the performance of liquid crystal displays has been remarkably improved. In particular, an active matrix liquid crystal display having a switching function such as a diode or a thin film transistor for each picture element greatly contributes to the improvement of image quality and the increase in screen size. ing. Many thin film transistors provided for each picture element use amorphous silicon as an active layer of the transistor on an insulating substrate, which enables a large area and a low process temperature (up to 350 ° C.). It has advantages such as.

【0003】また、ポリシリコンを活性層とした薄膜ト
ランジスタも一部に商品化されており、その高移動度特
性を利用して、絵素毎のスイッチングのみならず駆動回
路をも構成しており、駆動回路一体型液晶ディスプレイ
を実現している。しかし、ポリシリコン薄膜トランジス
タは、通常、プロセス温度が高温であるため、ガラス基
板を使用することができず石英基板が使用されている。
石英基板はガラス基板に比べ高価であり、また大面積化
が困難である。したがって、ポリシリコン薄膜トランジ
スタの当面の目標はガラス基板の使用可能な温度(〜6
00℃)で安定した特性の得られるプロセスを開発する
ことにある。
In addition, a thin film transistor using polysilicon as an active layer has been partially commercialized, and by utilizing its high mobility characteristic, not only switching for each picture element but also a driving circuit is constituted, We have realized a liquid crystal display with an integrated drive circuit. However, since the process temperature of a polysilicon thin film transistor is usually high, a glass substrate cannot be used and a quartz substrate is used.
The quartz substrate is more expensive than the glass substrate, and it is difficult to increase the area. Therefore, the immediate goal of polysilicon thin film transistors is to reach the usable temperature of the glass substrate (~ 6
It is to develop a process that can obtain stable characteristics at (00 ° C).

【0004】[0004]

【発明が解決しようとする課題】前記のようにポリシリ
コン薄膜トランジスタを用いた場合、駆動回路一体型液
晶ディスプレイを実現できることが最大の利点である。
しかし、ポリシリコン薄膜トランジスタのオフ電流は非
晶質シリコン薄膜トランジスタに比べ高いことから、絵
素毎に設けるトランジスタとしては決して適していると
はいえない。
When a polysilicon thin film transistor is used as described above, the greatest advantage is that a liquid crystal display integrated with a drive circuit can be realized.
However, since the off-state current of the polysilicon thin film transistor is higher than that of the amorphous silicon thin film transistor, it cannot be said to be suitable as a transistor provided for each pixel.

【0005】ポリシリコン薄膜トランジスタのオフ電流
の低減方法としてはデュアルゲート構造、ポリシリコン
の薄膜化、LDD(Lightly Doped Drain) 構造が考えら
れているがいずれも一長一短がある。デュアルゲート構
造は2個以上のトランジスタを並列に接続し、ゲート電
極を共通にする方法であり、トランジスタをオフしたと
きのドレイン電界を緩和することによってオフ電流を減
少させる。しかし、限られたスペースに2個以上のトラ
ンジスタを形成することは、絵素の開口率の低下につな
がってしまい、望ましくない。
As a method of reducing the off current of a polysilicon thin film transistor, a dual gate structure, a thin film of polysilicon, and an LDD (Lightly Doped Drain) structure have been considered, but all have advantages and disadvantages. The dual gate structure is a method in which two or more transistors are connected in parallel and have a common gate electrode, and the off-current is reduced by relaxing the drain electric field when the transistors are turned off. However, it is not desirable to form two or more transistors in a limited space because it leads to a reduction in the aperture ratio of the picture element.

【0006】ポリシリコンの薄膜化は非常に簡便な方法
であり薄膜化によりソース、ドレイン間の抵抗を高くす
ることでオフ電流の低減を図る。しかし、期待されるほ
どの低減効果は得られていない。LDD(Lightly Doped
Drain) 構造は、例えば、ソース・ドレインがn+ 層の
場合、チャネルとソースとの間、およびチャネルとドレ
インとの間にn- 層を設けている。これは、図13に示
すように、通常、ポリシリコン膜22上にゲート電極2
3を形成したのち、ゲート電極23をマスクとして低濃
度イオンを注入してn- 層24を形成する(図13
(a))。次にゲート電極23の側壁にサイドウォール
絶縁体25を形成した後、再度イオン注入し、n+ 層2
6を形成する(図13(b))ことで実現される。
The thinning of polysilicon is a very simple method, and the off current is reduced by increasing the resistance between the source and the drain by thinning. However, the expected reduction effect has not been obtained. LDD (Lightly Doped
In the Drain structure, for example, when the source / drain is an n + layer, an n layer is provided between the channel and the source and between the channel and the drain. As shown in FIG. 13, the gate electrode 2 is usually formed on the polysilicon film 22.
3 is formed, low-concentration ions are implanted using the gate electrode 23 as a mask to form an n layer 24 (FIG. 13).
(A)). Next, a side wall insulator 25 is formed on the side wall of the gate electrode 23, and then ion implantation is performed again to form the n + layer 2
This is realized by forming 6 (FIG. 13B).

【0007】また、別の方法として図14に示すよう
に、ゲート電極33をマスクとして、斜め回転イオン注
入によりn- 層34を形成した(図14(a))後、通
常のイオン注入法にてn+ 層35を形成する(図14
(b))。この方法ではn- 層34が深くチャネル領域
に入り込み、ゲートと大きく重なりを有する構造となる
ことから、ゲートオーバーラップLDD構造と呼ばれて
いる。
As another method, as shown in FIG. 14, an n layer 34 is formed by oblique rotation ion implantation using the gate electrode 33 as a mask (FIG. 14A), and then a normal ion implantation method is applied. To form the n + layer 35 (FIG. 14).
(B)). This method is called a gate overlap LDD structure because the n layer 34 deeply enters the channel region and has a structure having a large overlap with the gate.

【0008】どちらの構造においてもドレイン電界を緩
和させ耐圧の向上を図ることでオフ電流を減少させる事
ができるが、図13のLDD構造ではゲートに電圧を印
加していったときソースn- 層の寄生抵抗により電流駆
動能力が低下してしまう。一方、図14のゲートオーバ
ーラップLDD構造においてはn- 層がゲート電極の下
に存在することにより、電流駆動能力を損なうことがな
い。しかし、いずれの方法にしても、イオン注入を2回
行う必要があることや、サイドウォール絶縁体の形成あ
るいは斜め回転イオン注入など製造工程が複雑になると
いう課題があった。
In either structure, the off-current can be reduced by relaxing the drain electric field and improving the breakdown voltage, but in the LDD structure of FIG. 13, the source n - layer is formed when a voltage is applied to the gate. The current resistance is reduced due to the parasitic resistance of. On the other hand, in the gate overlap LDD structure of FIG. 14, the n layer exists below the gate electrode, so that the current driving capability is not impaired. However, in any of the methods, there are problems that it is necessary to perform ion implantation twice, and the manufacturing process such as formation of sidewall insulators or oblique rotation ion implantation becomes complicated.

【0009】次に、ガラス基体の使用可能な低温プロセ
スのポリシリコン薄膜トランジスタの問題点について触
れる。薄膜トランジスタは、一般に電界効果トランジス
タであるために、その特性はゲート絶縁層とチャネルと
なる多結晶Si膜との界面状態に非常に大きく影響され
る。このため、従来の高温プロセスでは熱酸化法によ
り、ゲート絶縁層とチャネルの界面とをチャネル層内部
に作り込み、界面状態を良好に保っている。これに対
し、低温プロセスでは、ゲート絶縁層も低温で形成する
必要があるため、上記の熱酸化法は使えない。そのた
め、多結晶Si膜を所定の形状に加工した後、弗酸等を
用いて表面の清浄化処理を行い、その後スパッタ、ある
いは、CVD法等を用いてゲート絶縁膜を形成する方法
が採られているが、界面準位密度の十分な低減には至っ
ていない。
Next, the problems of low temperature process polysilicon thin film transistors which can use glass substrates will be touched upon. Since the thin film transistor is generally a field effect transistor, its characteristics are greatly affected by the state of the interface between the gate insulating layer and the polycrystalline Si film that serves as the channel. Therefore, in the conventional high temperature process, the interface between the gate insulating layer and the channel is formed inside the channel layer by the thermal oxidation method, and the interface state is kept good. On the other hand, in the low temperature process, since the gate insulating layer also needs to be formed at a low temperature, the above thermal oxidation method cannot be used. Therefore, a method is adopted in which the polycrystalline Si film is processed into a predetermined shape, the surface is cleaned with hydrofluoric acid or the like, and then the gate insulating film is formed by sputtering, CVD, or the like. However, the interface state density has not been sufficiently reduced.

【0010】そこで、多結晶Si膜を成膜した後、大気
にさらさずゲート絶縁膜を連続して成膜する方法が検討
されているが、この方法においては、ゲート絶縁膜およ
び多結晶Si膜を所定の形状に加工したときに、多結晶
Si膜側面が露出してしまう。そして、その後ゲート電
極を形成した際にゲート電極と露出した多結晶Si膜と
の側壁が接し、リーク電流が増大することになるという
問題があった。したがって、ポリシリコンの側壁を絶縁
体で保護する必要があるが、ポリシリコンの側壁を保護
する絶縁体とゲート絶縁膜とが選択的にエッチングでき
ることが必要条件となるため、ゲート絶縁膜、及び側壁
保護のための絶縁体材料が限定されてしまうという問題
があった。
Therefore, a method of continuously forming a gate insulating film without exposing it to the atmosphere after forming a polycrystalline Si film has been studied. In this method, the gate insulating film and the polycrystalline Si film are formed. When processed into a predetermined shape, the side surface of the polycrystalline Si film is exposed. Then, when the gate electrode is formed thereafter, the sidewalls of the gate electrode and the exposed polycrystalline Si film come into contact with each other, which causes a problem that the leak current increases. Therefore, it is necessary to protect the sidewall of the polysilicon with an insulator, but it is necessary that the insulator protecting the sidewall of the polysilicon and the gate insulating film can be selectively etched. Therefore, the gate insulating film and the sidewall are protected. There is a problem that the insulating material for protection is limited.

【0011】この発明は上記のような問題点に鑑みてな
されたもので、ガラス基板の使用可能な低温プロセスに
おいても理想的な製造方法であるとともに、オフ電流を
低減するための最良の方法であるゲートオーバーラップ
LDD構造を比較的容易に実現することができる薄膜ト
ランジスタ及びその製造方法を提供することを目的とし
ている。
The present invention has been made in view of the above problems, and is an ideal manufacturing method even in a low temperature process in which a glass substrate can be used, and is the best method for reducing the off current. It is an object of the present invention to provide a thin film transistor and a method of manufacturing the thin film transistor which can relatively easily realize a certain gate overlap LDD structure.

【0012】[0012]

【課題を解決するための手段】上記の目的を達成するた
め、この発明によれば、絶縁性基板上にトランジスタの
活性層となるポリシリコン層、ゲート絶縁膜及びゲート
電極が順次形成された薄膜トランジスタであって、前記
ゲート電極が上層ゲート電極及び下層ゲート電極の2層
構造からなり、かつ前記上層ゲート電極の電極幅と前記
下層ゲート電極の電極幅とが同一幅でない薄膜トランジ
スタが提供される。
In order to achieve the above-mentioned object, according to the present invention, a thin film transistor in which a polysilicon layer which becomes an active layer of a transistor, a gate insulating film and a gate electrode are sequentially formed on an insulating substrate. There is provided a thin film transistor, wherein the gate electrode has a two-layer structure of an upper layer gate electrode and a lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode width of the lower layer gate electrode are not the same width.

【0013】また別の観点から、(i) 絶縁性基板上にポ
リシリコン層、ゲート絶縁膜及び下層ゲート電極を順次
連続して成膜して積層膜を形成する工程、(ii)前記積層
膜を島状パターンに加工した後、前記島状パターンの側
壁に絶縁体を形成する工程、(iii) 前記下層ゲート電極
のみを所定の形状に加工し、さらに、前記下層ゲート電
極上に上層ゲート電極を成膜する工程、(iv)前記上層ゲ
ート電極を所定の形状に加工する工程、(v) 前記下層ゲ
ート電極及び前記上層ゲート電極をマスクにして不純物
イオンを前記ポリシリコン層に注入して、不純物拡散領
域を形成する工程を含む薄膜トランジスタの製造方法が
提供される。
From another point of view, (i) a step of sequentially forming a polysilicon layer, a gate insulating film, and a lower gate electrode on an insulating substrate to form a laminated film, (ii) the laminated film And then forming an insulator on the sidewall of the island pattern, (iii) processing only the lower gate electrode into a predetermined shape, and further forming an upper gate electrode on the lower gate electrode. And (iv) processing the upper gate electrode into a predetermined shape, (v) implanting impurity ions into the polysilicon layer using the lower gate electrode and the upper gate electrode as a mask, A method of manufacturing a thin film transistor including a step of forming an impurity diffusion region is provided.

【0014】この発明における絶縁性基板とは、通常薄
膜トランジスタに用いられる基板であれば特に限定され
るものではなく、ガラス基板、石英基板等を用いること
ができる。そして、この絶縁性基板上に直接、あるいは
基板からの不純物の拡散を防止するために窒化膜等の絶
縁膜を500〜3000Å程度積層した上に、薄膜トラ
ンジスタの活性層となるポリシリコン膜を形成する。こ
のポリシリコンは、公知の方法、例えば、CVD法によ
り、400〜600℃でシランガス等を用いて非晶質の
シリコン膜を形成したのち、真空中あるいは不活性ガス
雰囲気中で、500〜600℃、数時間アニールを行う
ことにより形成することができる。また、石英基板等を
使った高温プロセスにおいても同様に行うことができ
る。この際のポリシリコンの膜厚は500〜1500Å
程度が好ましい。また、ゲート絶縁膜として形成される
膜は、トランジスタ特性に悪影響を及ぼさない範囲で種
々選択することができるが、SiO2 膜が好ましい。S
iO2 膜は公知の方法、例えば、CVD法により形成す
ることができる。この際のSiO2 膜の膜厚は500〜
1500Å程度が好ましい。なお、絶縁性基板上に非晶
質シリコンを形成する工程からゲート絶縁膜を成膜する
までの工程は、外気に曝されることなく、真空中あるい
は不活性ガス雰囲気中に保持して行うことが好ましい。
The insulating substrate in the present invention is not particularly limited as long as it is a substrate usually used for a thin film transistor, and a glass substrate, a quartz substrate or the like can be used. Then, an insulating film such as a nitride film is laminated on the insulating substrate directly or in order to prevent diffusion of impurities from the substrate to a thickness of about 500 to 3000 Å, and a polysilicon film to be an active layer of the thin film transistor is formed. . This polysilicon is formed at a temperature of 500 to 600 ° C. in a vacuum or in an inert gas atmosphere after forming an amorphous silicon film using silane gas or the like at 400 to 600 ° C. by a known method such as a CVD method. It can be formed by annealing for several hours. Further, it can be similarly performed in a high temperature process using a quartz substrate or the like. At this time, the film thickness of polysilicon is 500 to 1500Å
A degree is preferable. The film formed as the gate insulating film can be variously selected within the range that does not adversely affect the transistor characteristics, but the SiO 2 film is preferable. S
The iO 2 film can be formed by a known method, for example, a CVD method. At this time, the thickness of the SiO 2 film is 500 to
About 1500Å is preferable. Note that the steps from forming amorphous silicon on an insulating substrate to forming a gate insulating film should be performed in a vacuum or in an inert gas atmosphere without being exposed to the outside air. Is preferred.

【0015】また、この発明における薄膜トランジスタ
のゲート電極は下層及び上層の2層構造からなってお
り、上層ゲート電極と下層ゲート電極との電極幅は同一
幅を有していない。つまり、上層ゲート電極が下層ゲー
ト電極より大きな電極幅を有しているか、あるいは下層
ゲート電極が上層ゲート電極より大きな電極幅を有して
いるものである。しかし、下層ゲート電極の電極幅が上
層ゲート電極の電極幅より大きい場合には、上層ゲート
電極を加工する際、下層ゲート電極の一部が露出するこ
ととなるので、エッチング時間を精度よく管理しないと
下層ゲート電極をエッチングしてしまうという問題が生
じるが、下層ゲート電極の方が上層ゲート電極の電極幅
より小さい場合には上記のような問題が防止されるとう
いう点から、上層ゲート電極が下層ゲート電極より大き
な電極幅を有している方が好ましい。なお、これらゲー
ト電極の電極幅は作製する薄膜トランジスタの大きさに
依存しており、特に限定されるものではない。また、下
層ゲート電極及び上層ゲート電極は、それぞれ各種メタ
ルあるいはポリシリコン膜等、トランジスタ特性に悪影
響を及ぼさない範囲で種々選択することができるが、ポ
リシリコンの場合はソース・ドレイン形成のイオン注入
時に同時にイオン注入することによってゲート電極とす
ることが出来る。ポリシリコンは、公知の方法、例え
ば、シランガスを用いたCVD法で形成することができ
る。
The gate electrode of the thin film transistor according to the present invention has a two-layer structure of a lower layer and an upper layer, and the electrode widths of the upper layer gate electrode and the lower layer gate electrode do not have the same width. That is, the upper layer gate electrode has a larger electrode width than the lower layer gate electrode, or the lower layer gate electrode has a larger electrode width than the upper layer gate electrode. However, when the electrode width of the lower layer gate electrode is larger than that of the upper layer gate electrode, a part of the lower layer gate electrode is exposed when processing the upper layer gate electrode, and therefore the etching time is not accurately controlled. However, if the lower gate electrode is smaller than the electrode width of the upper gate electrode, the above problem is prevented. It is preferable to have an electrode width larger than that of the lower layer gate electrode. Note that the electrode width of these gate electrodes depends on the size of a thin film transistor to be manufactured and is not particularly limited. Further, the lower layer gate electrode and the upper layer gate electrode can be variously selected from various metals or polysilicon films, etc. within a range that does not adversely affect the transistor characteristics, but in the case of polysilicon, at the time of ion implantation for source / drain formation, A gate electrode can be formed by simultaneously implanting ions. Polysilicon can be formed by a known method, for example, a CVD method using a silane gas.

【0016】この発明においては、絶縁性基板上にポリ
シリコン層、ゲート絶縁膜及び下層ゲート電極を順次形
成したのち、同一のレジストパターンを用いて、これら
3層構造を同時にエッチングして島状のパターンに形成
する。この場合のエッチングは公知の方法により、それ
ぞれエッチングすることができるが、各層のエッチング
後の断面形状が基板に対して垂直になるように、異方性
エッチングによりパターニングすることが好ましい。ま
た、これらパターニングされた3層構造の側壁には絶縁
体のサイドウォールが形成されている。このサイドウォ
ールは、公知の絶縁膜、例えば、SiO2 膜を3000
〜8000Å程度積層し、異方性エッチングによるよう
な、公知の方法により形成することができる。
In the present invention, a polysilicon layer, a gate insulating film and a lower gate electrode are sequentially formed on an insulating substrate, and then these three layer structures are simultaneously etched using the same resist pattern to form an island shape. Form in a pattern. The etching in this case can be performed by a known method, but it is preferable to perform patterning by anisotropic etching so that the cross-sectional shape of each layer after etching becomes perpendicular to the substrate. Moreover, sidewalls of an insulator are formed on the sidewalls of the patterned three-layer structure. This sidewall is formed of a known insulating film, for example, a SiO 2 film for 3000.
It can be formed by a known method such as stacking up to about 8000 Å and anisotropic etching.

【0017】また、この発明においては、下層ゲート電
極のみを所定の形状に加工し、さらに下層ゲート電極上
に上層ゲート電極を成膜、加工した後、下層及び上層ゲ
ート電極をマスクにして不純物イオンをポリシリコン層
に注入して、不純物拡散領域を形成する。
Further, in the present invention, only the lower layer gate electrode is processed into a predetermined shape, and the upper layer gate electrode is formed and processed on the lower layer gate electrode, and then the lower layer and the upper layer gate electrodes are used as a mask for impurity ions. Is implanted into the polysilicon layer to form an impurity diffusion region.

【0018】[0018]

【作用】上記のような構造及び方法においては、ゲート
電極が上層ゲート電極及び下層ゲート電極の2層構造か
らなり、かつ上層ゲート電極の電極幅と下層ゲート電極
の電極幅とが同一幅でないので、上層及び下層ゲート電
極をマスクに不純物イオンを注入することで、ゲートオ
ーバーラップLDD構造が容易に形成される。
In the above structure and method, since the gate electrode has a two-layer structure of the upper layer gate electrode and the lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode width of the lower layer gate electrode are not the same width. The gate overlap LDD structure is easily formed by implanting impurity ions using the upper and lower gate electrodes as a mask.

【0019】また、トランジスタの活性層となるポリシ
リコン層、ゲート絶縁膜及び下層ゲート電極を順次連続
して成膜するので、ポリシリコン層とゲート絶縁膜との
界面が常に安定で良好な状態が保たれる。さらに、ポリ
シリコン層、ゲート絶縁膜及び下層ゲート電極の積層膜
の上面が下層ゲート電極材料となっているので、パター
ニングされた3層構造の積層膜の側壁に絶縁体を形成す
るためのエッチング加工の際、特にゲート絶縁膜との選
択的なエッチングを必要とせず、容易に形成することが
できる。
Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film and the lower gate electrode are successively formed, the interface between the polysilicon layer and the gate insulating film is always stable and in good condition. To be kept. Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film and the lower gate electrode is the lower gate electrode material, the etching process for forming the insulator on the sidewall of the patterned laminated film of the three-layer structure is performed. At this time, it can be easily formed without requiring selective etching with the gate insulating film.

【0020】[0020]

【実施例】この発明に係わる薄膜トランジスタの実施例
を図面に基づいて説明する。 実施例1 図1は薄膜トランジスタの一実施例を示しており、
(a)は平面図、(b)はA−A線断面図、(c)はB
−B線断面図である。この薄膜トランジスタは、ガラス
基板1上にSiN膜2、ポリシリコン層3及びSiO2
膜4が順次積層されて構成されており、SiO2 膜4上
に下層ゲート電極5が形成されており、下層ゲート電極
5上に下層ゲート電極5幅よりも小さい幅を有する上層
ゲート電極7が形成されている。そして、チャネル部と
なるポリシリコン層3には自己整合的にLDD構造を有
する不純物拡散領域10が形成されており、不純物拡散
領域10にメタル電極配線9が接続されて、薄膜トラン
ジスタが形成されている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a thin film transistor according to the present invention will be described with reference to the drawings. Example 1 FIG. 1 shows an example of a thin film transistor,
(A) is a plan view, (b) is a sectional view taken along the line AA, and (c) is B.
It is a -B line sectional view. This thin film transistor includes a SiN film 2, a polysilicon layer 3 and a SiO 2 film on a glass substrate 1.
The films 4 are sequentially laminated, the lower gate electrode 5 is formed on the SiO 2 film 4, and the upper gate electrode 7 having a width smaller than the width of the lower gate electrode 5 is formed on the lower gate electrode 5. Has been formed. Then, an impurity diffusion region 10 having an LDD structure is formed in a self-aligned manner in the polysilicon layer 3 serving as a channel portion, and the metal electrode wiring 9 is connected to the impurity diffusion region 10 to form a thin film transistor. .

【0021】以下に、上記の薄膜トランジスタの製造方
法を図面に基づいて説明する。まず、図2に示したよう
に、ガラス基板1上にガラスからの不純物の拡散を防ぐ
ためにSiN膜2を約3000Å堆積させた後、その上
にプラズマCVD装置にて非晶質シリコン膜を成膜す
る。成膜条件は基板温度400〜600℃でH2希釈さ
れたSiH4 ガスを熱とプラズマとで分解し、約100
0Å堆積させる。次に非晶質シリコン膜を多結晶化する
ため、真空中にて約600℃で1時間のアニールを行
い、ポリシリコン膜3とする。続いて、減圧CVD装置
にてゲート絶縁膜となるSiO2 膜4を約1000Å成
膜する。以上の非晶質シリコン膜の成膜からゲート絶縁
膜の成膜までの工程において、プラズマCVD装置から
アニール炉、及びアニール炉から減圧CVD装置へのガ
ラス基板1の移動は真空で保持されたロードロック室を
介して行っている。次に、減圧CVD装置にて下層ゲー
ト電極5となるポリシリコン膜を約1500Å成膜す
る。
A method of manufacturing the above thin film transistor will be described below with reference to the drawings. First, as shown in FIG. 2, a SiN film 2 is deposited on the glass substrate 1 to prevent the diffusion of impurities from the glass by about 3000 Å, and then an amorphous silicon film is formed thereon by a plasma CVD apparatus. To film. The film forming conditions are as follows: SiH 4 gas diluted with H 2 at a substrate temperature of 400 to 600 ° C. is decomposed by heat and plasma to obtain about 100
Deposit 0Å. Next, in order to polycrystallize the amorphous silicon film, annealing is performed in vacuum at about 600 ° C. for 1 hour to form a polysilicon film 3. Subsequently, a SiO 2 film 4 serving as a gate insulating film is formed by a low pressure CVD apparatus to a thickness of about 1000Å. In the above steps from the formation of the amorphous silicon film to the formation of the gate insulating film, the movement of the glass substrate 1 from the plasma CVD apparatus to the annealing furnace and from the annealing furnace to the low pressure CVD apparatus is performed by a load held in vacuum. It goes through the lock room. Then, a polysilicon film to be the lower gate electrode 5 is formed by a low pressure CVD apparatus to a thickness of about 1500 Å.

【0022】次いで、図3に示したように、窒化シリコ
ン膜2上のポリシリコン層3、SiO2 膜4及び下層ゲ
ート電極5の3層の膜を同一のレジストパターンでエッ
チングし、島状パターンに加工する。各層のエッチング
は反応性イオンエッチャーを用い、エッチングした後の
断面形状がガラス基板1に対し垂直となるように異方性
エッチングを行っている。尚、ポリシリコン層3のエッ
チングにはSF6 とCCl4 との混合ガスを、SiO2
膜4のエッチングにはCHF3 をそれぞれエッチングガ
スとして用いた。
Then, as shown in FIG. 3, three layers of the polysilicon layer 3, the SiO 2 film 4 and the lower gate electrode 5 on the silicon nitride film 2 are etched with the same resist pattern to form an island pattern. To process. Reactive ion etching is used for etching each layer, and anisotropic etching is performed so that the cross-sectional shape after etching is perpendicular to the glass substrate 1. For the etching of the polysilicon layer 3, a mixed gas of SF 6 and CCl 4 is used as SiO 2
CHF 3 was used as an etching gas for etching the film 4.

【0023】次に、図4に示したように、ガラス基板1
全面にスパッタ装置にてSiO2 膜6を約5000Å成
膜する。その後、反応成イオンエッチャーにてCHF3
を反応性ガスとして用い、図5に示したように、SiO
2 膜6が島状パターンの側壁のみに残存するように異方
性エッチングを行う。エッチングの終点はエッチングが
進行し、窒化シリコン膜2が露出したことをプラズマ分
析により知ることで検知が可能である。
Next, as shown in FIG. 4, the glass substrate 1
A SiO 2 film 6 is formed on the entire surface by a sputtering device to a thickness of about 5000Å. After that, CHF 3 with reactive ion etcher
Is used as a reactive gas, as shown in FIG.
2 Anisotropic etching is performed so that the film 6 remains only on the sidewalls of the island pattern. The end point of the etching can be detected by knowing that the silicon nitride film 2 is exposed by the progress of the etching by plasma analysis.

【0024】その後、図6に示したように、下層ゲート
電極5を反応性イオンエッチャーにて、所定の形状に加
工する。この際、下層ゲート電極5の電極幅(図6
(b)中、トランジスタ長:L)を5μmとした。その
後、図7に示したように、下層ゲート電極5を含むガラ
ス基板1全面に、減圧CVD装置にて上層ゲート電極7
となるポリシリコン膜を約1500Å成膜する。
Thereafter, as shown in FIG. 6, the lower gate electrode 5 is processed into a predetermined shape by a reactive ion etcher. At this time, the electrode width of the lower gate electrode 5 (see FIG.
In (b), the transistor length: L) was set to 5 μm. After that, as shown in FIG. 7, the upper gate electrode 7 is formed on the entire surface of the glass substrate 1 including the lower gate electrode 5 by a low pressure CVD apparatus.
Then, a polysilicon film to be used as a film is formed by about 1500 Å.

【0025】次いで、図8に示したように、下層ゲート
電極5の電極幅の中心線を同一として、上層ゲート電極
7の電極幅(図8(b)中、トランジスタ長:M)を3
μmに加工する。次に、図9に示したように、プラズマ
イオンドーピング装置にて水素ガスで希釈されたPH3
ガスを用いてプラズマを形成し、P(リン)イオンを注
入して、ゲート電極6に高濃度領域を形成するととも
に、ポリシリコン膜にLDD構造を有する不純物拡散領
域10を形成する。
Next, as shown in FIG. 8, the electrode width of the upper gate electrode 7 (transistor length: M in FIG. 8B) is set to 3 with the center line of the electrode width of the lower gate electrode 5 being the same.
Process to μm. Next, as shown in FIG. 9, PH 3 diluted with hydrogen gas was used in a plasma ion doping apparatus.
Plasma is formed using gas and P (phosphorus) ions are implanted to form a high concentration region in the gate electrode 6 and an impurity diffusion region 10 having an LDD structure in the polysilicon film.

【0026】その後、図10に示したように、層間絶縁
膜となるSiO2 膜11を約5000Å成膜し、不純物
拡散領域10となる部分にコンタクトホールを形成した
後、メタル配線9を形成してN型の薄膜トランジスタを
作製する。このように作製した薄膜トランジスタのPイ
オンの濃度分布を図11に示す。図11に示したよう
に、直上にゲート電極6の存在しない不純物拡散領域1
0となる部分のポリシリコン層3には、充分な濃度のP
イオンが注入されて、n+領域となっている。一方、下
層ゲート電極5のみが直上に存在するポリシリコン層3
には高濃度の不純物拡散領域10に比べ、約2桁少ない
量のPイオンが注入されて、n- 領域となっている。ま
た、上層ゲート電極7及び下層ゲート電極5の両方が直
上に存在するポリシリコン層3にはほとんどPイオンは
到達していなかった。
After that, as shown in FIG. 10, a SiO 2 film 11 to be an interlayer insulating film is formed to a thickness of about 5000 Å, a contact hole is formed in a portion to be an impurity diffusion region 10, and then a metal wiring 9 is formed. To produce an N-type thin film transistor. The P ion concentration distribution of the thin film transistor thus manufactured is shown in FIG. As shown in FIG. 11, the impurity diffusion region 1 in which the gate electrode 6 does not exist immediately above
In the portion of the polysilicon layer 3 which becomes 0, P of sufficient concentration is formed.
Ions are implanted to form an n + region. On the other hand, the polysilicon layer 3 in which only the lower gate electrode 5 exists immediately above
Is doped with P ions in an amount that is about two orders of magnitude smaller than that in the high-concentration impurity diffusion region 10 to become an n region. In addition, almost no P ions reached the polysilicon layer 3 where both the upper gate electrode 7 and the lower gate electrode 5 exist immediately above.

【0027】従って、この薄膜トランジスタは上層ゲー
ト電極7及び下層ゲート電極5の電極幅を同一の3μm
とした場合の薄膜トランジスタと比較して、オフ電流が
約2桁低減できた。また、オン時のドレイン電流の駆動
能力は同程度であった。 実施例2 実施例1と同様の方法により、活性層となるポリシリコ
ン層3、ゲート絶縁膜であるSiO2 膜4及び下層ゲー
ト電極15となるポリシリコン膜の3層膜を島状パター
ンに加工し、その島状パターンの側壁にSiO2 膜6の
絶縁体を形成する。実施例2においては下層ゲート電極
15の電極幅(L)を3μmに加工した後、上層ゲート
電極17となるポリシリコン膜を成膜し、下層ゲート電
極15の電極幅の中心線を同一にして、上層ゲート電極
17の電極幅(M)を5μmに加工する。そして、実施
例1と同様の方法で図12に示す、薄膜トランジスタを
作製した。
Therefore, in this thin film transistor, the upper layer gate electrode 7 and the lower layer gate electrode 5 have the same electrode width of 3 μm.
As compared with the thin film transistor in the case of, the off current could be reduced by about 2 digits. Further, the driving capability of the drain current when turned on was about the same. Example 2 By the same method as in Example 1, a three-layer film of a polysilicon layer 3 to be an active layer, a SiO 2 film 4 to be a gate insulating film and a polysilicon film to be a lower gate electrode 15 is processed into an island pattern. Then, the insulator of the SiO 2 film 6 is formed on the side wall of the island pattern. In Example 2, after processing the electrode width (L) of the lower layer gate electrode 15 to 3 μm, a polysilicon film to be the upper layer gate electrode 17 was formed and the center line of the electrode width of the lower layer gate electrode 15 was made the same. The electrode width (M) of the upper gate electrode 17 is processed to 5 μm. Then, the thin film transistor shown in FIG. 12 was manufactured in the same manner as in Example 1.

【0028】このように作製された薄膜トランジスタの
オフ電流も実施例1と同等の約2桁の低減効果が認めら
れた。以上の実施例1、及び2のように上層ゲート電極
と下層ゲート電極のそれぞれの電極幅を異ならせた形状
としたうえで、イオン注入を施すことによりゲートオー
バーラップLDDが実現されるため、オン電流の駆動能
力を損なうことなくオフ電流の低減を図ることができ
た。
The off-current of the thin film transistor thus manufactured was also reduced by about two digits, which is the same as in Example 1. Since the gate overlap LDD is realized by performing ion implantation after forming the upper layer gate electrode and the lower layer gate electrode with different electrode widths as in the first and second embodiments, It was possible to reduce the off-current without impairing the current driving capability.

【0029】[0029]

【発明の効果】上記のようにこの発明の薄膜トランジス
タ及びその製造方法においては、ゲート電極が上層ゲー
ト電極及び下層ゲート電極の2層構造からなり、かつ上
層ゲート電極の電極幅と下層ゲート電極の電極幅とが同
一幅でないので、上層及び下層ゲート電極をマスクに不
純物イオンを1回注入することで、ゲートオーバーラッ
プLDD構造を容易に形成することができる。従って、
イオン電流の駆動能力を損なうことなく、オフ電流の低
減化を実現することができた。
As described above, in the thin film transistor and the method of manufacturing the same according to the present invention, the gate electrode has a two-layer structure of the upper layer gate electrode and the lower layer gate electrode, and the electrode width of the upper layer gate electrode and the electrode of the lower layer gate electrode. Since the width is not the same as the width, the gate overlap LDD structure can be easily formed by implanting impurity ions once using the upper and lower layer gate electrodes as a mask. Therefore,
It was possible to realize a reduction in off-current without impairing the drive capability of the ion current.

【0030】また、トランジスタの活性層となるポリシ
リコン層、ゲート絶縁膜、及び下層ゲート電極を順次連
続して成膜するので、ポリシリコン層とゲート絶縁膜と
の界面を常に安定に良好な状態で、薄膜トランジスタを
製造することができる。従って、600℃以下の低温プ
ロセスにおいても高性能なトランジスタ特性を安定して
得ることができる。
Further, since the polysilicon layer serving as the active layer of the transistor, the gate insulating film, and the lower gate electrode are successively formed, the interface between the polysilicon layer and the gate insulating film is always stable and in a good state. Thus, a thin film transistor can be manufactured. Therefore, high-performance transistor characteristics can be stably obtained even in a low temperature process of 600 ° C. or lower.

【0031】さらに、ポリシリコン層、ゲート絶縁膜及
び下層ゲート電極の積層膜の上面が下層ゲート電極材料
となっているので、パターニングされた3層構造の積層
膜の側壁に絶縁体を形成するためのエッチング加工の
際、特にゲート絶縁膜との選択的なエッチングを必要と
せず、薄膜トランジスタの製造工程を簡略化することが
できる。
Further, since the upper surface of the laminated film of the polysilicon layer, the gate insulating film and the lower layer gate electrode is the lower layer gate electrode material, in order to form an insulator on the side wall of the patterned laminated film of the three-layer structure. In the etching process, the selective manufacturing of the gate insulating film is not particularly required, and the manufacturing process of the thin film transistor can be simplified.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明に係わる薄膜トランジスタの一実施例
を示す要部の概略平面図、概略断面図である。
FIG. 1 is a schematic plan view and a schematic cross-sectional view of a main part showing an embodiment of a thin film transistor according to the present invention.

【図2】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
2A and 2B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 2A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

【図3】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
3A and 3B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 3A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. 3B is a cross-sectional view taken along the line BB of FIG. .

【図4】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
4A and 4B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 4A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

【図5】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
5A and 5B are schematic cross-sectional views of a main part showing a manufacturing process of Example 1, where FIG. 5A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. 5B is a cross-sectional view taken along the line BB of FIG. .

【図6】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
6A and 6B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 6A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 6B is a cross-sectional view taken along the line BB of FIG. .

【図7】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
7A and 7B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 7A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

【図8】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
8A and 8B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 8A is a cross-sectional view taken along the line AA of FIG. 1 and FIG. .

【図9】実施例1の製造工程を示す要部の概略断面図で
あり、(a)は図1のA−A線断面図、(b)は図1の
B−B線断面図である。
9A and 9B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 9A is a cross-sectional view taken along the line AA of FIG. 1, and FIG. 9B is a cross-sectional view taken along the line BB of FIG. .

【図10】実施例1の製造工程を示す要部の概略断面図
であり、(a)は図1のA−A線断面図、(b)は図1
のB−B線断面図である。
10A and 10B are schematic cross-sectional views of a main part showing the manufacturing process of Example 1, where FIG. 10A is a cross-sectional view taken along the line AA of FIG. 1 and FIG.
FIG. 6 is a sectional view taken along line BB of FIG.

【図11】実施例1における薄膜トランジスタの、Pイ
オン注入後のPイオン濃度分布を示す図である。
FIG. 11 is a diagram showing a P ion concentration distribution after P ion implantation in the thin film transistor in Example 1.

【図12】この発明に係わる薄膜トランジスタの別の実
施例を示す要部の概略平面図、概略断面図である。
12A and 12B are a schematic plan view and a schematic sectional view of a main part showing another embodiment of the thin film transistor according to the present invention.

【図13】従来のLDD(Lightly Doped Drain) 構造を
有する薄膜トランジスタの製造方法を説明するための概
略断面図である。
FIG. 13 is a schematic cross-sectional view for explaining a method of manufacturing a thin film transistor having a conventional LDD (Lightly Doped Drain) structure.

【図14】従来のゲートオーバラップLDD構造を有す
る薄膜トランジスタの製造方法を説明するための概略断
面図である。
FIG. 14 is a schematic cross-sectional view for explaining a method of manufacturing a conventional thin film transistor having a gate overlap LDD structure.

【符号の説明】[Explanation of symbols]

1 ガラス基板(絶縁性基板) 3 ポリシリコン層 4 SiO2 膜(ゲート絶縁膜) 5 下層ゲート電極 6 SiO2 膜(絶縁体) 7 上層ゲート電極 8 ゲート電極 10 不純物拡散領域1 glass substrate (insulating substrate) 3 polysilicon layer 4 SiO 2 film (gate insulating film) 5 lower layer gate electrode 6 SiO 2 film (insulator) 7 upper layer gate electrode 8 gate electrode 10 impurity diffusion region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性基板上にトランジスタの活性層と
なるポリシリコン層、ゲート絶縁膜及びゲート電極が順
次形成された薄膜トランジスタであって、前記ゲート電
極が上層ゲート電極及び下層ゲート電極の2層構造から
なり、かつ前記上層ゲート電極の電極幅と前記下層ゲー
ト電極の電極幅とが同一幅でないことを特徴とする薄膜
トランジスタ。
1. A thin film transistor in which a polysilicon layer serving as an active layer of a transistor, a gate insulating film, and a gate electrode are sequentially formed on an insulating substrate, and the gate electrode is a two-layer structure including an upper gate electrode and a lower gate electrode. A thin film transistor having a structure, wherein the electrode width of the upper gate electrode and the electrode width of the lower gate electrode are not the same.
【請求項2】 (i) 絶縁性基板上にポリシリコン層、ゲ
ート絶縁膜及び下層ゲート電極を順次連続して成膜して
積層膜を形成する工程、 (ii)前記積層膜を島状パターンに加工した後、前記島状
パターンの側壁に絶縁体を形成する工程、 (iii) 前記下層ゲート電極のみを所定の形状に加工し、
さらに、前記下層ゲート電極上に上層ゲート電極を成膜
する工程、 (iv)前記上層ゲート電極を所定の形状に加工する工程、 (v) 前記下層ゲート電極及び前記上層ゲート電極をマス
クにして不純物イオンを前記ポリシリコン層に注入し
て、不純物拡散領域を形成する工程、 を含む請求項1記載の薄膜トランジスタの製造方法。
2. (i) a step of forming a laminated film by successively and continuously forming a polysilicon layer, a gate insulating film and a lower gate electrode on an insulating substrate, (ii) forming the laminated film in an island pattern And then forming an insulator on the side wall of the island pattern, (iii) processing only the lower layer gate electrode into a predetermined shape,
Further, a step of forming an upper layer gate electrode on the lower layer gate electrode, (iv) a step of processing the upper layer gate electrode into a predetermined shape, (v) an impurity using the lower layer gate electrode and the upper layer gate electrode as a mask The method of manufacturing a thin film transistor according to claim 1, further comprising the step of implanting ions into the polysilicon layer to form an impurity diffusion region.
JP18933492A 1992-07-16 1992-07-16 Thin film transistor and method of manufacturing the same Expired - Fee Related JP3171673B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18933492A JP3171673B2 (en) 1992-07-16 1992-07-16 Thin film transistor and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18933492A JP3171673B2 (en) 1992-07-16 1992-07-16 Thin film transistor and method of manufacturing the same

Publications (2)

Publication Number Publication Date
JPH0637314A true JPH0637314A (en) 1994-02-10
JP3171673B2 JP3171673B2 (en) 2001-05-28

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Country Link
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2322968A (en) * 1997-03-04 1998-09-09 Lg Electronics Inc Thin-film transistor and method of making same
EP1006589A2 (en) * 1998-12-03 2000-06-07 Semiconductor Energy Laboratory Co., Ltd. MOS thin film transistor and method of fabricating same
US6531713B1 (en) 1999-03-19 2003-03-11 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and manufacturing method thereof
US6839135B2 (en) 2000-04-11 2005-01-04 Agilent Technologies, Inc. Optical device
US6909117B2 (en) 2000-09-22 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and manufacturing method thereof
US6917408B2 (en) * 2001-11-30 2005-07-12 Sharp Kabushiki Kaisha Display panel
US8049275B2 (en) * 1998-11-17 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8183135B2 (en) 2003-03-13 2012-05-22 Nec Corporation Method for manufacturing thin film transistor having hydrogen feeding layer formed between a metal gate and a gate insulating film

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2322968A (en) * 1997-03-04 1998-09-09 Lg Electronics Inc Thin-film transistor and method of making same
GB2322968B (en) * 1997-03-04 1999-09-29 Lg Electronics Inc Thin-film transistor and method of making same
US8957422B2 (en) 1998-11-17 2015-02-17 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
US9627460B2 (en) 1998-11-17 2017-04-18 Semiconductor Energy Laboratory Co., Ltd. Method of fabricating a semiconductor device
US8049275B2 (en) * 1998-11-17 2011-11-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US7235810B1 (en) 1998-12-03 2007-06-26 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
EP2264771A3 (en) * 1998-12-03 2015-04-29 Semiconductor Energy Laboratory Co., Ltd. MOS thin film transistor and method of fabricating same
EP1006589A3 (en) * 1998-12-03 2000-09-27 Semiconductor Energy Laboratory Co., Ltd. MOS thin film transistor and method of fabricating same
EP1006589A2 (en) * 1998-12-03 2000-06-07 Semiconductor Energy Laboratory Co., Ltd. MOS thin film transistor and method of fabricating same
US6777255B2 (en) 1999-03-19 2004-08-17 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and manufacturing method thereof
US7462866B2 (en) 1999-03-19 2008-12-09 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and manufacturing method thereof
US6531713B1 (en) 1999-03-19 2003-03-11 Semiconductor Energy Laboratory Co., Ltd. Electro-optical device and manufacturing method thereof
US6839135B2 (en) 2000-04-11 2005-01-04 Agilent Technologies, Inc. Optical device
US6909117B2 (en) 2000-09-22 2005-06-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor display device and manufacturing method thereof
US6917408B2 (en) * 2001-11-30 2005-07-12 Sharp Kabushiki Kaisha Display panel
US8183135B2 (en) 2003-03-13 2012-05-22 Nec Corporation Method for manufacturing thin film transistor having hydrogen feeding layer formed between a metal gate and a gate insulating film

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