JPH06350088A - Field-effect transistor and its manufacture - Google Patents

Abstract

PURPOSE:To make with good precision, a multiinput gate type FET excelling in drive capability and occupying a small area. CONSTITUTION:A gate electrode 4 of the first layer formed on a gate SiO2 3 is covered by a thin conformal SiO2 5, and gate electrodes 6c after the second layer are formed in the shape of a side wall through a combination of the deposit of a poly-silicon layer over the entire surface and etchback. Further, a source region 8 and a drain region 9 are formed on both external sides of these gate electrodes. An equivalent circuit is formed to the case of connecting in series a plurality of MOS-FETs without an impurity diffused region between each gate electrode. Consequently, a minute gate electrode 6b can be arranged adjacently without being constrained by the marginal resolution of photolithography. In contrast to the constitution in series connection of the conventional type, because of no impurity diffused region existing between gate electrodes 6c, high-speed operation is possible without parasitic resistance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-input gate type field effect transistor (FET) which can be configured with a small occupied area and can perform a high speed NAND operation, and a manufacturing method thereof.

[0002]

2. Description of the Related Art A circuit configuration for connecting MOS-FETs in series is, for example, two n-types in a 2-input NAND circuit.
MOS-FET series connection or feedback
This can be seen in, for example, a series connection of a feedback gate transistor and a vertical selection transistor in the photo sensor section of the gate type amplification type solid-state imaging device.

In order to improve the degree of integration of a semiconductor integrated circuit, it is necessary to reduce the area occupied by each circuit as much as possible. In the case where the MOS-FETs are connected in series as described above, the conventional configuration that minimizes the occupied area is a configuration in which the drain region and the source region of adjacent MOS-FETs are shared.

As an example, a schematic diagram of a conventional three-input type circuit formed on a semiconductor substrate is shown in FIG. This circuit
In the element formation region surrounded by the element isolation region 32 on the substrate 31, the three transistors Tr ₁₁ , Tr ₁₂ , Tr
_{The thirteen} gate electrodes 34, 35, 36 are spaced apart from each other on the gate oxide film 33 formed by the surface oxidation of the substrate 31. Gate electrode 34 of transistor Tr ₁₁
An impurity diffusion region 37 serving as a source region is disposed between the element isolation region 32 and the element isolation region 32, and an impurity diffusion region 40 serving as a drain region is disposed between the transistor Tr ₁₃ and the element isolation region 32. Furthermore, the transistor T
The impurity diffusion regions 38 and 39 arranged between r ₁₁ and Tr _{12 and} between the transistors Tr ₁₂ and Tr ₁₃ serve as the drain region of the transistor in the front stage and the source region of the transistor in the rear stage, respectively.

In this structure, the three gate electrodes 3
Control signal voltage V _in11 ,
When V _in12 and V _in13 are applied and the inversion layer is formed in all of the channel region immediately below, the drain voltage V _DS
Drop between the source and drain (that is, the impurity region 3
Drain current I _D flows between (7, 40).

[0006]

In the fine processing of semiconductor integrated circuits, a pattern in which a plurality of wiring layers (lines) are arranged at regular intervals (spaces) is generally called a line-and-space pattern. I'm out. The gate electrodes 34, 35, 36 and the impurity diffusion region 3 of FIG.
The arrangement of 8 and 39 is also a typical example, and in this case, assuming that the line width of the gate electrodes 34, 35 and 36 is L and the space width of the impurity diffusion regions 38 and 39 is S, in the case of such a 3-input configuration. , The distance between source and drain is (3L + 2
S). Especially L = S, number of inputs (ie number of gates)
= X, the distance between the source and drain is generally nL
It is represented by + (n-1) L = (2n-1) L.

The minimum dimensions of the line width L and the space width S are determined by the resolution of photolithography. However, in recent years, the width of these patterns has approached the wavelength of the exposure light, so the reduction in depth of focus and the reduction in contrast due to diffraction and interference are significant, and fine line-and-space patterns can be resolved with high precision. This is far more difficult than resolving an isolated line pattern. Therefore, there is a limit in reducing the above-mentioned source-drain distance (2n-1) L.

Further, in the case of the 3-input type circuit as shown in FIG. 8, the impurity diffusion region 3 is formed in the region connecting the channels formed directly under the gate electrodes 34, 35, 36.
There are 8,39. For this reason, a parasitic resistance is inevitably generated between the adjacent gate electrodes, which causes a decrease in drive capability.

Therefore, the present invention solves these problems,
It is an object of the present invention to provide a multi-input gate type field effect transistor that can be accurately configured with a small occupied area and can operate at high speed, and a manufacturing method thereof.

[0010]

The field effect transistor of the present invention is proposed in view of the above object,
A maximum of (2n-1) gate electrodes formed by patterning n layers (where n represents an integer of 2 or more) of gate electrode material layers on a common channel region sandwiches a conformal insulating film. Adjacent to each other in the horizontal direction, the m-th layer (where m is an integer satisfying the condition of 2 ≦ m ≦ n) always forms the sidewall of the (m−1) -th layer gate electrode. It will be.

Here, if the gate insulating film immediately below the m-th layer gate electrode and the (m-1) -th layer gate electrode has different thicknesses, the channel is correspondingly changed. It is effective to control the impurity concentration distribution in the region.

The field effect transistor can perform a NAND operation based on the voltage applied state to each of the gate electrodes.

In such a field effect transistor, the (m-1) th layer (where m is 2) as if traversing the channel region.
Represents the above integers. ) Patterning step of forming a gate electrode, and at least the channel region and the (m-
1) An insulating film forming step of covering the first-layer gate electrode with a conformal insulating film; an electrode forming step of forming an m-th layer gate electrode material layer on the insulating film; The gate electrode material layer may be etched back, and an etching back step of forming a sidewall-shaped m-th layer gate electrode on the side wall surface of the (m-1) -th layer gate electrode may be performed.

At this time, prior to the electrode forming step of forming the m-th layer gate electrode material layer, if ion implantation is carried out using all the gate electrodes before the (m-1) th layer as masks,
An impurity concentration distribution can be formed in the channel region.

In the patterning step, the processed end of the m-th layer gate electrode outside the channel region is
It is also effective to form the gate electrode so that it is always closer to the channel region than the processed end of the (m-1) th layer gate electrode.

[0016]

In the field-effect transistor of the present invention, adjacent ones of a plurality of gate electrodes arranged horizontally adjacent to each other on the common channel region are adjacent to each other to form a main pattern having a conformal thin insulating film therebetween. It has a sidewall relationship. That is, the area occupied by the circuit can be reduced because there is no conventional impurity diffusion region between the adjacent gate electrodes, and the parasitic resistance between the gate electrodes can be eliminated to speed up the operation. .

In such a structure, the region where the inversion layer is formed by applying the gate voltage from one gate electrode is only a part of the single channel region. In order to obtain the drain current I _D , the inversion layer must be formed over the entire channel region existing between the source and drain. That is, when the control signal voltage is applied from all the gate electrodes (H level), the drain voltage first drops (L level), and this transistor is turned on. This is a NAND operation.

In the method of manufacturing the field effect transistor, the line width of the plurality of gate electrodes is determined by the limit resolution of photolithography only for the first gate electrode formed. For such isolated patterns, it is possible to achieve a relatively high resolution even by conventional photolithography. On the other hand, the second and subsequent gate electrodes are formed on the basis of the self-aligned sidewall process, and therefore are not limited by the resolution limit of photolithography. Also in this sense, the field effect transistor of the present invention facilitates miniaturization of design rules.

As described above, according to the process of sequentially forming a certain gate electrode as the sidewall of the immediately preceding gate electrode, when an n-layer gate electrode material layer is used, these are not patterned at all in the subsequent process. However, at least n gate electrodes arranged concentrically can be formed. However, since the gate electrode of a field effect transistor is generally formed so that the longitudinal direction thereof crosses the channel region, the sidewalls are sequentially extended outward along the left and right side wall surfaces of the first gate electrode in the longitudinal direction. It will be formed. Therefore, by always removing both ends of the second and subsequent gate electrodes by patterning, the left side wall and the right side wall can be made independent gate electrodes with respect to the main pattern, A maximum of (2n-1) gate electrodes can be formed.

By the way, a conformal insulating film is always interposed between the plurality of gate electrodes. That is, the insulating film forming step is always performed before the electrode forming step of forming the next gate electrode material layer. This insulating film is
On the surface of the gate electrode, it functions as an insulating film between itself and a gate electrode to be formed next, and on the channel region, it functions as a normal gate insulating film. Therefore, as the gate electrode is formed later, the thickness of the gate insulating film directly below the gate electrode becomes larger, which causes variation in the threshold value. However, depending on the difference in film thickness of the gate insulating film, an impurity having an appropriate concentration is introduced into the channel region immediately below it by so-called channel doping. As a result, it is possible to cancel the fluctuation of the threshold value due to the nonuniformity of the film thickness and realize a stable operation.

Such an impurity concentration distribution can be created in a completely self-aligned manner by performing appropriate ion implantation using all the gate electrodes formed before that as masks before forming the next gate electrode material layer. it can.

When the sidewall-shaped gate electrode formed according to the present invention has an extremely fine dimension, the contact formation position with the upper layer wiring is shifted between the adjacent gate electrodes outside the channel region. Otherwise, there is a high possibility that the gate electrodes will short-circuit. In such a case, patterning is performed so that the processed end of the immediately preceding gate electrode is always projected beyond the processed end of the gate electrode formed later, outside the channel region, and the obtained stepped protrusion is formed. If you make contact sequentially,
The short circuit as described above can be avoided.

[0023]

EXAMPLES Specific examples of the present invention will be described below.

[0024]Example 1 In this embodiment, a 3-input type MO configured by applying the present invention
The S-FET will be described. This MOS-FET is
As shown in the schematic cross-sectional view of FIG.
In the element formation region surrounded by the element isolation region 2, 3
Transistors Tr ₁, Tr₂, Tr₃Gate electrode
6c, 4, 6c are isolated from each other and from the Si substrate 1.
They are arranged in a state of having a limbal membrane.

The gate electrodes 6c, 4 and 6c are SiO ₂ films 5 which conformally cover the central gate electrode 4.
Are insulated from each other by the gate electrodes 6c at both ends,
6c forms a sidewall of the gate electrode 4. Therefore, the total line width of these three gate electrodes 6c, 4 and 6c is only about 40% of the case where the three gate electrodes are spaced apart according to the conventional line-and-space pattern. It has been reduced.

Impurity diffusion regions are formed in the Si substrate 1 in a self-aligned manner on both outer sides of these three gate electrodes 6c, 4, 6c. These function as a source (S) region 8 and a drain (D) region 9, respectively. A region sandwiched between the source region 8 and the drain region 9 is a channel region. This channel region functions as one continuous channel region when the inversion layer is formed in the portions corresponding to the portions directly below the gate electrodes 6c, 4, 6c, that is, in all of the channels Ch1, Ch2, Ch3. Has been done.

The central gate electrode 4 is a gate Si formed by surface oxidation of the Si substrate 1 as in the conventional case.
Although formed on the O ₂ film 3, the gate electrodes 6 on both ends are formed.
In addition to the gate SiO ₂ film 3,
The horizontal extension of the _two films 5 also insulates the Si substrate 1. That is, Si that functions as a gate insulating film
The O ₂ film thickness is not the same for all gate electrodes. Therefore, in order to match the operating threshold of the transistor Tr ₂ with that of the transistors Tr ₁ and Tr ₃ , the impurity concentration in the channels Ch1 and Ch3 is set to the channel C.
It is set to a level different from that of h2.

Next, a three-input type MOS having such a structure
The NAND operation of the FET will be described. This MOS
The equivalent circuit diagram of the -FET is as shown in FIG. Now, the control signal voltages applied to these three gate electrodes 6c, 4 and 6c are V _in1 , V _in2 and V respectively.
_in3 As shown in FIG. 1A, when the input signal voltage is not applied to any gate electrode, (L
Level), no inversion layer is formed in either channel,
Therefore, the current I does not flow between the source and drain (I
= 0).

Further, as shown in FIG. 1B, for example, the gate electrodes 6c, 6 of the transistors Tr ₁ , Tr ₃ are formed.
When the control voltage signals V _in1 and V _in3 are applied only to c (H level) and the middle gate electrode 4 is at L level, the inversion layers (represented by black dots in the figure) in the channels Ch1 and Ch3. ) Is formed, but not in the channel Ch2. Therefore, the current I does not flow between the source and the drain (I = 0).

However, as shown in FIG. 1C, the control voltage signal V _in1 ,
When V _in2 and V _in3 are applied, all channels C
An inversion layer is formed in h1, Ch2, and Ch3, the transistor is turned on, and the drain current I _D flows. That is,
NAND operation is performed. The driving capability at this time has been improved by the absence of parasitic resistance, unlike the conventional case where an impurity diffusion region is interposed between each gate electrode.

Embodiment 2 In this embodiment, a manufacturing process of a MOS-FET to which the present invention is applied will be described with reference to FIGS. First, as shown in FIG.
The gate SiO ₂ film 3 is formed by thermally oxidizing the surface of the element formation region 7 on the Si substrate 1 in which the element isolation region 2 is formed by the S method or the like, and the gate SiO ₂ film 3 contains, for example, impurities. The polysilicon film (first-layer gate electrode material layer) to be patterned was patterned to form the gate electrode 4 (first-layer gate electrode).

The Si substrate 1 may be previously subjected to channel doping before forming the gate electrode 4 to control the impurity concentration of the channel Ch2 (see FIG. 1).

Next, as shown in FIG.
Conformal SiO that covers the gate electrode 4₂Membrane 5
Was formed. This SiO₂As a method of forming the film 5, heat is used.
Oxidation or O₃-TEOS atmospheric pressure CVD method, O₂-T
EOS plasma CVD method, H ₂O-TEOS Plasma C
Any of the CVD methods such as the VD method, which has excellent step coverage, is used.
It doesn't matter.

Next, as shown in FIG. 3C, ion implantation was performed using the gate electrode 4 as a mask. This is channel doping for matching the threshold value of the second-layer gate electrode formed next with the threshold value of the gate electrode 4. Next, as shown in FIG. 3D, a polysilicon layer 6 (second gate electrode material layer) containing impurities was deposited on the entire surface of the wafer.

Next, the polysilicon layer 6 was etched back to form a sidewall-shaped polysilicon layer 6a on the side wall surface of the gate electrode 4, as shown in FIG. 4 (e). A top view of the state of the wafer at this stage is also shown on the lower side of FIG. The drawing on the upper side is a cross-sectional view taken along the line AA of this top view. The polysilicon layer 6a before patterning is formed around the central gate electrode 4. Since this etch-back process is self-aligned and is not restricted by the resolution limit of photolithography, the line width of each gate electrode could be miniaturized to 0.4 μm or less.

Next, the polysilicon layer 6a is patterned to form a gate electrode 6b as shown in FIG. 4 (f).
(Or 6c) is formed, and ion implantation is performed using all of these gate electrodes as a mask to form a source region 8 and a drain region 9. Here, the number of gate electrodes to be formed can be determined by the patterning method of the polysilicon layer 6a.

That is, if one end on the short side of the polysilicon layer 6a that surrounds the gate electrode 4 is removed, the structure shown in FIG.
As shown in (f-1), a two-input MOS-FET having the gate electrode 4 and the gate electrode 6b can be formed. In this case, if the contact holes CH1 and CH2 are formed at positions separated from each other as shown in the drawing so that the contact positions of the gate electrodes 4 and 6b and the upper layer wiring do not overlap, the contact holes CH1 and CH2 between the gate electrodes 4 and 6b are formed. A short circuit can be prevented.

Alternatively, as shown in FIG. 5F-2, if both ends on the short side of the polysilicon layer 6a are removed, the three-input type MOS-FET as described in the first embodiment is obtained.
Can be formed. In this case, as an example, the contact hole CH1 for the gate electrode 4 and the contact hole CH2 for the gate electrodes 6c, 6c.
By providing CH3 and the element formation region 7 on opposite sides of each other, it is possible to prevent a short circuit between the gate electrodes.

As yet another modification, as shown in FIG. 6, the sidewall-shaped gate electrode 6d is left only on one side of the central gate electrode 4, and the 2-input MOS-FET is formed.
Can also be manufactured. This is apparent from the plan view, and the polysilicon layer 6a [see FIG. 4 (e)]. ] Can be manufactured by removing only one side in the longitudinal direction. However, in this case, the channel doping in the previous step may be performed only on one side of the gate electrode 4.

Embodiment 3 In this embodiment, the structure and manufacturing method of a 5-input MOS-FET will be briefly described with reference to FIG.
The lower side of FIG. 7 is a schematic plan view of the MOS-FET, and the upper side is a sectional view taken along the line BB. 5 of this embodiment
The configuration of the input type MOS-FET is the above-mentioned three-input type MOS.
-It has a configuration in which two gate electrodes are added to the outside of the three gate electrodes of the FET. That is, as shown in the schematic cross-sectional view on the upper side of FIG. 7, five gate electrodes 18, 16, 14, 16 are formed in the element formation region 19 surrounded by the element isolation region 12 on the Si substrate 11. 18
Are arranged with an insulating film interposed between them and with the Si substrate 11. Where the gate electrode 1
Reference numerals 6 and 16 are sidewalls formed on both side wall surfaces of the central gate electrode 14, and are insulated from each other by a SiO ₂ film 15 which conformally covers the gate electrode 14. The gate electrodes 18, 18 are formed of sidewalls on the side wall surfaces of the gate electrodes 16, 16 and are insulated from each other by the SiO ₂ film 17 which conformally covers the gate electrodes 16, 16. .

In the Si substrate 11, impurity diffusion regions are formed in a self-aligned manner on both outsides of these five gate electrodes 18, 16, 14, 16, 18, respectively, and the source region 20 and the drain region are respectively formed. Function as 21. A region sandwiched between the source region 20 and the drain region 21 is a channel region. Here, the gate SiO ₂ film 13 is the only film that functions as a gate insulating film with respect to the central gate electrode 14, but the SiO ₂ film 15 is added to the gate electrodes 16 and 16 on both sides thereof, and The SiO ₂ film 17 is further added to the gate electrodes 18 on both sides. Therefore, the impurity concentration of the channel region immediately below each gate electrode is controlled in a self-aligned manner by sequentially performing channel doping using all the gate electrodes formed immediately before as a mask.

The 5-input type MOS-FET is manufactured by a process in which the step of forming the SiO ₂ film and the step of forming the gate electrode on the outermost peripheral side are added once to the manufacturing process of the aforementioned 3-input type MOS-FET. can do. Although details of the process are omitted, the central gate electrode 14
(First layer gate electrode) is the first layer of gate electrode material,
Gate electrodes 16 and 16 on both sides thereof (second-layer gate electrode)
Is formed from the second-layer gate electrode material layer, and the gate electrodes 18 and 18 (third-layer gate electrodes) on both sides thereof are formed from the third-layer gate electrode material layer.

Here, if the processed end of the gate electrode outside the channel region is sequentially brought closer to the channel region in each step from the first layer to the third layer, as shown in the figure,
The planar profile of the whole of these five gate electrodes is stepwise. A short circuit between the gate electrodes can be prevented by making contact with the upper layer wiring at each step portion of the stepwise profile. For example, as shown in the drawing, a contact hole CH1 for the gate electrode 14, contact holes CH2, CH3 for the gate electrodes 16, 16 and contact holes CH4, CH5 for the gate electrodes 18, 18 are provided at mutually separated positions. Is effective.

Although the MOS-FET has five gate electrodes, the area occupied by the gate electrode portion is extremely small. This MOS-FET turns on when a control input voltage is applied from all five gates, and performs a 5-input NAND operation. In this embodiment, 2
Five gate electrodes were formed by removing both the third-layer gate electrode material layer and the third-layer gate electrode material layer at both ends on the short side, but by changing the patterning pattern, 4 input types or 3
It is also possible to manufacture an input type MOS-FET.

[0045]

As is apparent from the above description, according to the present invention, fine gate electrodes can be formed adjacent to each other with almost no restriction on the resolution of the photolithography process. Therefore, the present invention is
This is a great contribution to the manufacture of field-effect transistors that are designed according to the rules and perform high-speed NAND operation with excellent reliability, reproducibility, and productivity.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view for explaining the configuration of a 3-input type MOS-FET to which the present invention is applied and its NAND operation. FIG. 1A is a MOS-type MOS transistor in which an inversion layer is not formed in any channel. In the state where the FET is OFF, (b) shows that the inversion layer is formed only in a part of the channel, and the MOS-F
The state where ET is OFF, and (c) show the state where the inversion layer is formed in all the channels and the MOS-FET is ON.

FIG. 2 is an equivalent circuit diagram of the 3-input type MOS-FET.

FIG. 3 is a 2-input type or 3-input type MO to which the present invention is applied.
3A and 3B are schematic cross-sectional views showing a method of manufacturing an S-FET in the order of steps, in which (a) is a state in which a first-layer gate electrode is formed on a gate SiO ₂ film, and (b) is a mask over the entire surface of a wafer. With a formal SiO ₂ layer deposited,
(C) shows the channel using the first-layer gate electrode as a mask
A state in which doping is performed, (d) shows a state in which a polysilicon layer is deposited as a second-layer gate electrode material layer on the entire surface of the wafer.

FIG. 4 is a diagram showing a continuation of the manufacturing method, wherein (e) is a schematic plan view showing a state in which the polysilicon layer is etched back and a sectional view taken along the line AA, and (f) is etched back. The states in which the polysilicon layer is patterned and the ion implantation for forming the source / drain regions are performed are shown.

FIG. 5 is a schematic plan view showing the patterning pattern of the polysilicon layer which has been etched back and the formation positions of contact holes, and (f-1) is a 2-input MOS.
-FET and (f-2) correspond to 3-input type MOS-FETs, respectively.

FIG. 6 is a schematic plan view showing a two-input type MOS-FET manufactured by patterning the etched-back polysilicon layer according to another method and a cross-sectional view taken along the line AA.

FIG. 7 is a schematic plan view showing a configuration example of a 5-input type MOS-FET to which the present invention is applied and a cross-sectional view taken along the line BB thereof.

FIG. 8 is a schematic cross-sectional view showing a configuration example of a three-input type MOS-FET based on a conventional line-and-space pattern.

[Explanation of symbols]

1, 11 ・ ・ ・ Si substrate 2,12 ・ ・ ・ Element isolation region 3,13 ・ ・ ・ Gate SiO ₂ film 4,14 ・ ・ ・ (first layer) Gate electrode 5,15,17 ・ ・ ・ SiO ₂ Film 6 ... Polysilicon layer (second layer gate electrode material layer) 6a ... (After etchback) polysilicon layer 6b ... (2 input type MOS-FET 2
Layer) Gate electrode 6c (2 for 3-input type MOS-FET 2)
Layer) Gate electrode 7, 19 ... Element formation region 8, 20 ... Source region 9, 21 ... Drain region 16 ... (For 5 input type MOS-FET 2)
Layer) Gate electrode 18 (for 5 input type MOS-FET 3)
Layer) Gate electrode

Claims (6)

[Claims] 1. An n-layer (wherein
n represents an integer of 2 or more. (2n-1) gate electrodes formed by patterning the gate electrode material layer of (1) are arranged horizontally adjacent to each other with a conformal insulating film interposed therebetween, and the m-th layer (where m is 2 ≦ m ≦ A field effect transistor characterized in that the gate electrode always constitutes a sidewall of the (m-1) th layer gate electrode. 2. The m-th layer gate electrode and the (m-1)
2. The thickness of the gate insulating film immediately below these layers is made different from that of the layer gate electrode, and the impurity concentration distribution in the channel region is controlled accordingly. Field effect transistor. 3. The field effect transistor according to claim 1, wherein the NAND operation is performed based on a voltage applied state to each of the gate electrodes. 4. As the channel region is traversed (m-
1) a patterning step of forming a gate electrode in the first layer (where m represents an integer of 2 or more); and at least the channel region and the gate electrode in the (m-1) th layer are covered with a conformal insulating film. An insulating film forming step; an electrode forming step of forming an m-th layer gate electrode material layer on the insulating film; and an etch-back of the m-th gate electrode material layer to form the (m-1) An etch back step of forming a sidewall-shaped m-th layer gate electrode on the side wall surface of the second-layer gate electrode, and a maximum of (2n-1) (however, n
Represents an integer satisfying the condition of 2 ≦ m ≦ n. 2.) A method for manufacturing a field effect transistor, characterized in that the gate electrodes are formed adjacent to each other in the horizontal direction with a conformal insulating film interposed therebetween. 5. Impurity is implanted in the channel region by performing ion implantation using all gate electrodes before the (m-1) th layer as a mask, prior to the electrode forming step of the gate electrode material layer of the mth layer. The method of manufacturing a field effect transistor according to claim 4, wherein a concentration distribution is formed. 6. In the patterning step, the processed end of the m-th layer gate electrode outside the channel region is formed by (m−
1) The method for manufacturing a field effect transistor according to claim 4 or 5, wherein the gate electrode is formed so as to be always closer to the channel region than the processed end of the layer gate electrode.