JPH0635671A - Floating point adder-subtracter - Google Patents

Abstract

PURPOSE:To execute the addition and subtraction of a floating point accompanying a rounding-off at a high speed in a circuit constitution whose scale is smaller than used to be. CONSTITUTION:A floating point adder-subtracter is constituted of three fixed- point part inverting means 115-117 which are operated mainly in parallel, and two fixed-point part adders 118 and 119, and the rounding-off and absolute value of a fixed-point part in the floating point addition and subtraction is exclusively generated in the following cases. In the case of a real addition or a real subtraction in which the difference of excomponents is not 0, two rounded results are simultaneously calculated, and the correctly rounded results are selected by the constituting elements. In the case of the real subtraction in which the difference of the excomponents is 0, the difference of fixed-point parts and the number of the code inversion are simultaneously calculated, and the absolute value of the difference of the fixed-point parts is selected by the constituting elements. Therefore, it is not necessary to provide a borrow predicting mechanism, so that the scale of the circuit can be sharply reduced. And also, a critical path is shortened according to it, so that the high speed of an operating frequency can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating point addition / subtraction device for calculating the sum or difference of floating point numbers in information processing equipment.

[0002]

2. Description of the Related Art In recent years, high-speed floating point arithmetic is required in many information processing fields such as digital signal processing and numerical calculation. Microprocessors that process floating-point arithmetic at high speed in small computers such as workstations are being developed one after another. Since the floating-point addition / subtraction has a larger processing amount than the integer addition / subtraction, the one-clock processing of the floating-point addition / subtraction causes a large increase in the area and the number of elements. In the microprocessor incorporating the latest floating point arithmetic unit, by adopting the pipeline processing technique, one clock execution of the floating point addition / subtraction which has been difficult for the microprocessor and the signal processor until several years ago has been realized.

A conventional floating point addition / subtraction device is, for example, Le
slie Kohn, Sai-Wai Fu: "WAM3.6: A1,000,000 Transist
or Microprocessor ", IEEE International Solid-State
Circuits Conference, pp.54-55,1989 and Hon P. Sit,
Monica Rosenrauch Nofal, Sunhyuk Kimn: "An 80MFLOPS
Floating-point Engine in the Intel i860 (TM) Proces
sor ", IEEE International Conference on Computer Des
ign, pp.374-379,1989.

Regarding floating point arithmetic, for example, the ANSI / ITER PURIE P754-1985 standard (the Institute of Electrical and Electronics Electronics Inc.)
Floating Point Arismatic ", 1985) (ANSI / IEEE Std 754-19
85 (The Institute of Electrical and Electronics Eng
ineers, Inc: "IEEE Standard for Binary Floating-Poin
t Arithmetic ", 1985)). If the floating-point number is a denormalized number or a special number, or if a floating-point exception such as high-order overflow occurs during addition or subtraction, it differs from the following explanation. In the detailed description of the invention, for example, additions and subtractions of normalized numbers are performed without rounding and overflow, and the sum or difference of the normalized numbers or 0 is generated. Only the situation that can be obtained is described, and since the rounding algorithm is not an essential part of the present invention, the most complex and frequently used nearest rounding (of the four rounding modes defined in the above IEEE754 standard is used here. RN mode), but it is clear that the other three rounding methods can be easily realized by analogy with this description. It is.

The following symbols are defined in the following description. Floating-point numbers shall consist of a sign, exponent, and mantissa. The sign bit of the operand (augend or minuend) A is represented by s _A , the exponent part is represented by e _A , and the mantissa part is represented by f _A.
Similarly, the sign bit, exponent part, and mantissa part of the operation number (addition or subtraction) B are summed or subtracted by s _B , e _B , and f _B , respectively.
The sign bit, exponent, and mantissa of _R are s _R ,
Expressed as e _R and f _R.

'!' For a logical variable 'And the overline (used in the table) means logical negation, and the operator' + 'means logical sum. The operator '>>1' is a 1-bit right logical shift, and '<<
1'represents a 1-bit left logical shift. The symbol '*' is don '
t care, that is, it indicates that the logic may be 0 or 1.
The symbols X, x, y, z, w, etc. are logical variables representing either logic 0 or 1.

The least significant bit within the range of mantissa precision (the number of significant digits) of the floating point number to be added and subtracted is a symbol
Represented by L, the bit one digit lower than bit L is represented by symbol G, the bit one digit less than bit G is represented by symbol R, and the logical sum of all bits of the mantissa that are lower than bit R, that is, sticky bit Is represented by the symbol S. The 1's integer bit in the mantissa is the most significant bit of the mantissa and is represented by the symbol M, the bit one digit lower than the bit M is represented by the symbol U, and the bit one digit higher than the bit M. Represented by the symbol V.
The relationship between specific bit positions for normalized numbers and the names given to them is shown in FIG. Here, the mantissa precision (the number of significant digits) is represented by n. According to the IEEE754 standard, the M bits in the normalized number are hidden in the representation, but this is not the case in the internal representation in the floating-point adder / subtractor.

The following terms will be defined in the following description. A floating point number is assumed to be composed of a sign, an exponent part, and a mantissa part. The term mantissa refers to the entire mantissa, including its hidden most significant bits. As shown in (Table 1), the terms of true addition and true subtraction are
It is defined by the relationship between s _A and s _B and the combination of addition and subtraction. Generally, the processing procedure of the floating-point addition / subtraction device can be roughly divided into the case of true addition and the case of true subtraction. In the mantissa processing, true addition and true subtraction are added and subtracted, respectively.

In the mantissa upper overflow, the sum of the mantissas becomes 2 or more (V bit is 1), and the digit loss is that the absolute value of the difference of the mantissa is less than 1 (M bit is 0). It is defined as becoming. Shift means a logical shift with zero extension. The digit alignment is to shift the mantissa part of the floating-point number with the smaller exponent to the right by the number of bits of the exponent difference, and the normalization is when the digit loss occurs until the most significant bit of the mantissa part becomes 1. Indicates the operation of shifting left and subtracting the shifted number of bits from the exponent value.

[0010]

[Table 1]

A conventional example of the present invention will be described below with reference to the drawings. FIG. 2 shows a configuration diagram of a conventional floating point addition / subtraction device. A source A bus 201 is supplied with a floating point number A. A source B bus 202 is supplied with a floating point number B. A destination bus 203 outputs a result R calculated by the floating point addition / subtraction device.

Reference numeral 204 denotes a code generator which generates a true operation result code from the two floating-point number codes, the operation type, the two exponent magnitude relationships, and the two mantissa magnitude relationships. Determine if addition or true subtraction. An exponent subtractor 205 discriminates the magnitude of the two exponents and obtains the exponent difference.
An index selector 206 selects one of the two indexes which is not smaller.

An exponent corrector 207 reduces the number of post-computation normalized bits predicted in advance from the exponent which is not smaller. Reference numeral 208 denotes an exponent adjuster, which corrects a discrepancy of ± 1 in exponent value prediction related to post-computation normalization. A mantissa comparator 209 determines the magnitude relationship between two mantissas.

210, 211 and 212 are index differences
1 detector Detector, exponent difference 0 detector, exponent difference −1 detector detects that the exponent difference (e _A − e _B ) is 1, 0, −1, respectively. An index difference discriminator 213 has an index difference of 1
, 0, −1 or any other value.

Reference numeral 214 is a right shift encoder, which is an index difference
Calculates the right shift amount in pre-computation normalization by obtaining the absolute value of
To do. 215 is a left shift encoder (digit loss predictor)
Then, the exponent difference discriminator 213 determines that the exponent difference is 1, 0, −1.
Both mantissas f if determined to be either_A， F_B To
Scan from the upper bit, depending on the exponent difference 1, 0, −1
Predict the number of bits that the mantissa loses after the subtraction.

Reference numerals 216 and 217 denote mantissa barrel shifters, which shift the mantissa left or right for digit alignment of both mantissas f _A and f _B or normalization before operation. 218 is S
The bit generator generates S bits when aligning digits. Two
An R bit generator 19 obtains R bits after mantissa digit alignment and pre-operation normalization.

Reference numeral 220 denotes a mantissa exchanger, which exchanges both mantissas which have been digit-aligned or normalized before operation so that the difference becomes positive in the case of true subtraction. Reference numeral 221 denotes a mantissa inverter, which takes the one's complement of the subtraction in the case of true subtraction. Mantissa adders 222 and 223 substantially add and subtract the mantissa part and round it. 224
Is a mantissa selector, and selects one of the two addition / subtraction results, which has been added with 1 for rounding at the correct bit position.

A rounding compensator 225 corrects the least significant 1 bit of the provisionally rounded addition / subtraction result to realize accurate rounding. The operation of the floating point adder / subtractor according to the prior art configured as described above will be described below. The floating-point addition / subtraction device adds / subtracts floating-point numbers to each other by three-stage pipeline processing. Receives two floating-point numbers A and B from source A bus 201 and source B bus 202, adds or subtracts them, and then sums the results (A + B)
Or the difference (A-B) to the destination bus 203
Output to. The outline of the three-stage pipeline processing will be described below.

<First stage> -The magnitude of A and B are compared by the exponent part.・ If the index difference is 0, the magnitudes of A and B are compared using the mantissa. • Predict the number of bits with precision loss when the exponent difference is 1, 0, −1 and true subtraction.

The sign of the two floating point numbers, the magnitude relationship,
The sign of the result is determined according to the type of operation. <2nd stage> ・ Based on the precision cancellation, the mantissa is normalized or aligned before calculation.・ If the index difference is 1, 0, −1 and true subtraction, the index value is adjusted based on the precision loss.

<Third stage> -Substantially adding and subtracting mantissa and rounding. -Corrects only one bit and then normalizes it to correct the exponent and mantissa. When adding and subtracting floating point numbers A and B by this conventional example,
The specific operation of the conventional example will be described below separately for the case of true addition and the case of true subtraction. In the following explanation of the operation, keep in mind the actual operation of the circuit, and the logic of each part is don't
Even if it was care or nothing was done, it was clearly stated. In the operation logic of each functional block, when the difference of the mantissa is 0, there are some options for the operation and are omitted here.

1. In the case of true addition: Occurrence of overflow of the mantissa can be determined by setting the V bit of the sum obtained by the first mantissa adder 118 to 1. Exponent difference in <First stage> (1.1) Index subtractor 205 (e _A - e _B) is calculated. (1.2) the absolute value of the exponent difference in right shift encoder 214 | e _A - e _B | is calculated. (1.3) As a result of comparing the exponents, e
Select not smaller of _A and _{e B, max (e A,} e B)
Is output. (1.4) The mantissa comparator 209 compares the magnitudes of both mantissas f _A and f _B. (1.5) The code generator 204 determines the resulting code s _R based on (Table 2). Where the sign of the sum is s _A. (1.6) Index difference 1 detector 210, index difference 0 detector 211,
The exponent difference −1 detector 212 has exponent differences of 1, 0,
-1 is detected. (1.7) The exponent difference selector 213 selects whether the exponent difference is 1, 0, −1 or other.

<Second Stage> (2.1) The left shift encoder 215 does not operate effectively here. (2.2) Based on (Table 3), the first mantissa barrel shifter 216
Thus, if the exponent e _B is greater than the exponent e _{A, the} mantissa f _A is aligned, otherwise the mantissa f _{A is} passed through. Denote this output by f _A '. (2.3) Second mantissa barrel shifter 217 based on (Table 3)
Thus, if the exponent e _A is greater than the exponent e _{B, the} mantissa f _B is shifted to the right by the number of bits of the absolute value of the exponent difference (digit matching), otherwise the mantissa f _{B is} passed through. Denote this output by f _B '. (2.3) Second mantissa barrel shifter 217 based on (Table 3)
Thus, if the exponent e _B is greater than the exponent e _{A, the} mantissa f _A is aligned, otherwise the mantissa f _{A is} passed through. Denote this output by f _A '. (2.4) The S bit generator 218 takes the logical sum of all the bits spilled to the right from the R bits of the mantissa at the time of the above digit alignment, and sets this as the S bit. (2.5) The R bit generator 219 obtains the R bits of the digit-matched mantissa part. (2.6) The index corrector 207 passes the values max (e _A , e _B ). This output is represented by e _norm . (2.7) Based on (Table 4), the mantissa exchanger 220 selects one of the two mantissa parts f _A 'and f _B ', outputs it as f _s , and outputs the other as f _l . (2.8) Based on (Table 5), the mantissa inverter 221 calculates the addend f _s
And let this output be represented by f _s '.

<Third stage> By the second mantissa adder 223 based on (3.1) (Table 7)
Rounds f _l and f _s ' and 1 for L bits at the same time. (3.2) By the first mantissa adder 222 based on (Table 6)
Rounds f _l and f _s ' and 1 for G bits at the same time. If mantissa upper overflow occurs, jump to (3.5), otherwise proceed to the next. (3.3) Based on (Table 8), the mantissa selector 224 selects the sum obtained by the first mantissa adder 222. (3.4) Value in the index adjuster 208 based on (Table 8)
Let e _norm pass and let this value be e _R. Go to (3.7). (3.5) Based on (Table 8), the mantissa selector 224 selects a value obtained by shifting the sum obtained by the second mantissa adder 223 by 1 bit to the right. (3.6) Value in the index adjuster 208 based on (Table 8)
_Let e _R be the value obtained by incrementing e _norm by 1. (3.7) The rounding corrector 225 corrects the L bit of the sum for rounding based on (Table 9). (End) 2. Case of True Subtraction The series of processing in the second stage of the pipeline is generally called pre-operation normalization. Since prediction of the number of precision loss bits in the left shift encoder 215 causes a prediction error of 1 bit at the maximum, when the prediction fails, the mantissa selector 224 and the exponent adjuster 208 respectively correct the exponent part and the mantissa part by 1 bit.

<First Stage> (1.1) The exponent subtractor 205 calculates the exponent difference (e _A -e _B ). (1.2) the absolute value of the exponent difference in right shift encoder 214 | e _A - e _B | is calculated. (1.3) As a result of comparing the exponents, e
Select _A or e _B , whichever is not smaller, and output max (e _A , e _B ). (1.4) The mantissa comparator 209 compares the magnitudes of both mantissas f _A and f _B. (1.5) In the code generator 204, based on (Table 2) s _A
And s _B and the sign of the difference s _R is determined from the signs of (e _A − e _B ) and (f _A − f _B ). (1.6) Index difference 1 detector 210, index difference 0 detector 211,
The exponent difference −1 detector 212 has exponent differences of 1, 0,
-1 is detected. (1.7) The exponent difference selector 213 selects whether the exponent difference is 1, 0, −1 or other. Index difference
If it is 1, 0 or -1, jump to (2.9), otherwise proceed to the next.

<Second Stage> (2.1) The left shift encoder 215 does not operate effectively here. (2.2) Based on (Table 3), the first mantissa barrel shifter 216
Thus, if the exponent e _B is greater than the exponent e _{A, the} mantissa f _A is aligned, otherwise the mantissa f _{A is} passed through. Denote this output by f _A '. (2.3) Second mantissa barrel shifter 217 based on (Table 3)
Thus, if the exponent e _A is greater than the exponent e _{B, the} mantissa f _B is shifted to the right by the number of bits of the absolute value of the exponent difference (digit matching), otherwise the mantissa f _{B is} passed through. Denote this output by f _B '. (2.4) The S bit generator 218 takes the logical sum of all the bits spilled to the right from the R bits of the mantissa at the time of the above digit alignment, and sets this as the S bit. (2.5) The R bit generator 219 obtains the R bits of the digit-matched mantissa part. (2.6) The index corrector 207 passes the values max (e _A , e _B ). This output is represented by e _norm . (2.7) Based on (Table 4), the mantissa exchanger 220 selects one of the two mantissa parts f _A 'and f _B ', outputs it as f _s , and outputs the other as f _l . (2.8) Based on (Table 5), the mantissa inverter 221 calculates the addend f _s
And let this output be represented by f _s '.

<Third stage> By the second mantissa adder 223 based on (3.1) (Table 7)
f _l and f _s ' and 1 for complementing 1 and 2 for R bits are added together and rounded. (3.2) By the first mantissa adder 222 based on (Table 6)
Rounds f _l and f _s ' and 1 for complementing 1 and 2 for G bits at the same time. If a 1-bit precision loss occurs, jump to (3.5), otherwise proceed to the next. (3.3) Based on (Table 8), the mantissa selector 224 selects the difference calculated by the first mantissa adder 222. (3.4) Value in the index adjuster 208 based on (Table 8)
Let e _norm pass and let this value be e _R. Go to (3.7). (3.5) Based on (Table 8), the mantissa selector 224 selects a value obtained by shifting the difference obtained by the second mantissa adder 223 by 1 bit to the left. (3.6) Value in the index adjuster 208 based on (Table 8)
_Let e _R be the value obtained by reducing e _norm by 1. (3.7) The rounding corrector 225 corrects the L bit of the difference regarding rounding based on (Table 9). (End) <Branch of (1.7) (when the index difference is 1, 0, or -1)> (2.9) The left shift encoder 215 uses both mantissas f _A , f.
The upper bit of _B is scanned, and the number of bits to be lost after mantissa subtraction is predicted according to the exponent difference of 1, 0, −1. Based on (2.10) (Table 3), the first mantissa barrel shifter 216
Shifts the mantissa f _B to the left by the expected number of precision loss bits (pre-operation normalization), and the exponent e _A becomes the exponent e _B
If it is larger, shift 1 bit to the right (digit alignment).
This output is represented by f _B '. Second mantissa barrel shifter 217 based on (2.11) (Table 3)
, The mantissa f _A is normalized before the operation, and if exponent e _B is greater than exponent e _A, shift 1 bit to the right (digit alignment)
To do. Represent this output as f _A '. (2.12) The S bit generated by the S bit generator 218 is 0. (2.13) The R bit generated by the R bit generator 219 is 0. (2.14) In the exponent corrector 207, the number of precision loss bits is reduced from the value max (e _A , e _B ). This output is represented by e _norm . Based on (2.15) (Table 4), of the two mantissa parts f _A 'and f _B ', the mantissa exchanger 220 selects the mantissa part with the smaller exponent and outputs it as f _s. Select the mantissa part of and output it as f _l . Two exponential values e
_{If A} and e _B are equal, then the smaller of f _A '(here equal to f _A ) and f _B ' (here equal to f _B )
The larger one is output as f _l as f _s . Go to (2.8).

[0028]

[Table 2]

[0029]

[Table 3]

[0030]

[Table 4]

[0031]

[Table 5]

[0032]

[Table 6]

[0033]

[Table 7]

[0034]

[Table 8]

[0035]

[Table 9]

[0036]

However, the conventional floating point adder / subtractor has a problem that the circuit scale increases. Specifically, in order to avoid normalization after the operation, a circuit for predicting cancellation of digits in the first stage (exponent difference 1,0, -1 detector, left shift encoder), if the subtraction result is negative It is necessary to take the two's complement,
The circuit scale is increased by providing a circuit (mantissa comparator) for comparing the magnitudes of both mantissa parts in the first stage in order to always make the subtraction result positive and to avoid 2's complementation. This is because these circuits are generally very large.

Further, there has been a problem that the number of gate stages is increased due to the increase of the circuit scale and the processing speed is slowed down. In view of these problems, an object of the present invention is to provide a novel floating point addition / subtraction device that has a function equivalent to that of a conventional floating point addition / subtraction device and that is faster and requires less hardware.

[0038]

In order to solve the above-mentioned problems, a floating-point addition / subtraction device of the present invention calculates a sum or difference of two floating-point numbers represented by a sign, an exponent, and a mantissa. And the digit-matching unit that aligns digits by shifting the mantissa of the floating-point number with the smaller exponent to the lower side (hereinafter referred to as right) by the exponent difference, and adds the digit-matched mantissa and the other mantissa. Alternatively, if the exponent difference is 0, the addition / subtraction unit that subtracts the other mantissa from the one mantissa and simultaneously subtracts one from the other at the time of the subtraction, and the number of bits with which the mantissa has been subtracted And a normalization unit for normalizing by shifting the mantissa to the upper side by the number of bits and subtracting the number of bits from the exponent, and the digit matching unit subtracting the exponent of two numbers in floating point format, Both Select an exponent subtractor that determines the absolute value of the exponent difference and determine the mantissa of the floating-point number with the smaller exponent of the two floating-point numbers, or set the difference between the exponents of two numbers to 0. If so, a small mantissa selecting means for selecting one of the mantissas, a large mantissa selecting means for selecting the other mantissa part different from the selection of the small mantissa selecting means, and a mantissa selected by the small mantissa selecting means for the absolute difference of exponents. The mantissa right shift means logically shifts to the right by a value, and the addition / subtraction unit subtracts two numbers having the same sign or adds two numbers having different signs (hereinafter abbreviated as true subtraction). If the addition of two numbers with the same sign or the subtraction of two numbers with different signs (hereinafter abbreviated as true addition) is performed, the first mantissa inverting means for passing the output of the mantissa right shift means through And subtraction of exponent is not 0, the mantissa right shift Second mantissa inverting means for inverting the output of the output means and passing through otherwise, and inverting the output of the large mantissa selecting means in the case of true subtraction and when the exponent difference is 0, In the other cases, the third mantissa inverting means for passing through, the output of the first mantissa inverting means and the output of the large mantissa selecting means in the case of true addition are added, and the first mantissa in the case of true subtraction. First mantissa adding means for adding the output of the inverting means and the output of the large mantissa selecting means together with 1 for 2's complement, and the output of the second mantissa inverting means and the third mantissa inversion in the case of true addition. The outputs of the means are added, and in the case of true subtraction, the outputs of the second mantissa inversion means and the third
Second mantissa adding means for adding the output of the mantissa inverting means of 1 together with 1 for the two's complement, and first and second mantissa addition in the case of true subtraction and when the exponent difference is 0. And a subtraction result selecting unit that selects a positive value from two positive and negative subtraction results obtained from the unit, and the normalization unit obtains the number of precision loss bits for the output of the addition and subtraction unit in the case of true subtraction. It is composed of leading 1 detection means and mantissa left shifting means for shifting the output of the addition / subtraction unit to the left based on the number of bits obtained by the detection result of the leading 1 detection means.

A floating-point addition / subtraction device for calculating the sum or difference of two floating-point numbers represented by a sign, an exponent, and a mantissa, in which the floating-point mantissa having a smaller exponent is moved to the right by the exponent difference. The digit alignment unit that performs digit alignment by shifting, and the digit-matched mantissa and the other mantissa are added or subtracted, and if the exponent difference is 0, the other mantissa is subtracted from one mantissa at the time of subtraction, and at the same time from the other. An adder / subtractor that subtracts one, and a normalizer that normalizes by finding the number of bits that have been dropped for the subtracted mantissa, shifting the mantissa to the upper side by that number, and subtracting that number from the exponent The digit aligning unit determines the magnitude relationship between two exponents by subtracting two exponents in floating-point format, and an exponent subtractor that obtains the absolute value of the exponent difference; and two floating-point numbers. Out of A small mantissa selecting means for selecting a mantissa of a floating point number having a smaller number, or for selecting one of the mantissas if the difference between the exponents of two numbers is 0, and another mantissa part different from the selection of the small mantissa selecting means. A large mantissa selecting means for selecting
The mantissa right shift means logically shifts the mantissa selected by the small mantissa selection means to the right by the absolute value of the exponent difference. The adder / subtractor unit shifts the mantissa right when the subtraction is true and the exponent difference is not zero. The first mantissa reversing means for inverting the output of the shift means, and passing through otherwise, and the output of the large mantissa selecting means for true subtraction and an exponent difference of 0, and In the case other than the above, the second mantissa inverting means for passing through and the third mantissa for inverting the output of the mantissa right shifting means in the case of true subtraction and passing the output of the mantissa right shifting means in the case of true addition. The output of the first mantissa inversion means and the output of the second mantissa inversion means are added in the case of true addition, and the output of the first mantissa inversion means and the second mantissa in the case of true subtraction The output of the inverting means is 1 for 2's complement
Together with the first mantissa adding means, the output of the third mantissa inverting means and the output of the large mantissa selecting means in the case of true addition, and the output of the third mantissa inverting means in the case of true subtraction And second mantissa adding means for adding the output of the large mantissa selecting means together with 1 for 2's complement, and the first and second mantissas in the case of true subtraction and the exponent difference being 0. And a subtraction result selection unit that selects a positive value from the two positive and negative subtraction results obtained from the addition unit, and the normalization unit determines the number of precision loss bits for the output of the addition and subtraction unit in the case of true subtraction. It may be configured by the leading 1 detection means to be obtained and the mantissa left shifting means for shifting the output of the addition / subtraction unit to the left based on the number of bits obtained by the detection result of the leading 1 detection means.

The first mantissa adding means adds 1 for rounding to the bit one digit lower than the least significant bit in advance at the time of addition, and the second mantissa adding means adds in the case of true addition. Sometimes, a rounding 1 is added in advance to the bit one digit higher than the first mantissa adding means, and in the case of true subtraction, a rounding 1 is set to the one digit lower bit from the first mantissa adding means at the time of addition. In addition, the addition / subtraction unit may further include rounding correction means for obtaining a correctly rounded addition / subtraction result by correcting the least significant bit of the output of the addition / subtraction result selection means.

Further, the first and second mantissa adding means are M bits for the most significant bit of the mantissa part, and 1 from M bits.
The upper bit of the digit is V bit, the lower bit of M bit is U bit, the least significant bit is L bit, the lower bit of L digit is G bit, and the lower digit of G bit is R bit. In this case, the bit widths from V bits to R bits are added, and the digit alignment unit further
The first mantissa adding means is provided with S-bit generating means for obtaining a logical sum (hereinafter referred to as S bits) of all bits of the mantissa protruding below the R bits when the digits are aligned by the right shift means. In this case, add 1 for rounding to G bit,
In the case of true subtraction and when the exponent difference is not 0, 1 for rounding is added to G bits, and S is set as 1 for 2's complementing.
The logical negation of the bits is added to the R bits, and in the case of true subtraction and the exponent difference is 0, 1 for rounding is not added and 2
The S-bit logical negation value is added to the R bit as 1 for complementation of, and the second mantissa adding means adds 1 for rounding to the L bit in the case of true addition, and in the case of true subtraction. And when the exponent difference is not 0, 1 for rounding is added to the R bit, the logical negation of S is added to the R bit as 1 for 2's complementing, and true subtraction and the exponent difference is 0 No rounding 1 is added to the R bit, and a logical negation value of S bit is added to the R bit as 1 for 2's complementation, and the addition / subtraction result selection means is the calculation result of the first mantissa addition means (hereinafter abbreviated as A). ),
The operation result of the second mantissa adding means (hereinafter abbreviated as “B”) and the 1-bit left-shifted B (hereinafter abbreviated as “B”) are input,
In the case of true addition, if it does not overflow from M bits (if V is 0), select instep A; if it overflows from M bits (if V is 1), select 丙. , And the exponent difference is not 0, M
If there is no loss of digits (if M is 1), select A, and if there is 1 loss of digits (M is 0 and U is 1)
If it is), select B, and if it has more than 2 bits of digits missing (if M is 0 and U is 0), select A. If true subtraction and the exponent difference is 0, If the instep is positive, the instep is selected, and if the instep is a value, the instep is selected. If the instep is 1 or more based on the S bit and the instep, the rounding correction means (M
Is 1), the L-bit of the output (hereinafter abbreviated as "D") of the addition / subtraction result selecting means is corrected, and the instep is 1/2 or more 1
If it is less than (when M is 0 and U is 1), the G bit of the Ding is corrected, and if neither, the Ding may be passed through.

When correcting the L bit, the rounding correction means sets the L bit to 0 when the L bit is 1 and the logical sum of the values of the G bit, the R bit and the S is 0.
When the G bit is corrected, the G bit may be 0 if the logical sum of the R bit and the S value is 0.

[0043]

In the floating point adder / subtractor of the present invention having the above-mentioned configuration, in the case of true addition, the mantissa part of the floating point number having the smaller exponent is digitized by the small mantissa selecting means and the mantissa right shifting means, and the large mantissa is obtained. The mantissa part of the floating-point number having the larger exponent is selected by the selecting means, and the mantissa addition and rounding are performed at the same time by the first mantissa adder so that the mantissa digit overflow does not occur, and the second mantissa adder is used. Mantissa addition and rounding that assume overflow are performed at the same time, and the rounding 1 is added to the correct bit position of the two mantissa addition results by the addition / subtraction result selection means (the first mantissa adder when there is no overflow). As a result of addition, if a digit overflow occurs, the second
(The addition result of the mantissa adder) is selected, and the L bit of the sum is corrected by the rounding correction means.

In the case of true subtraction and the exponent difference is not 0, the small mantissa selecting means and the mantissa right shifting means align the digits of the mantissa part of the floating-point number having the smaller exponent, and the large mantissa selecting means increase the exponent. The mantissa part of one of the floating-point numbers is selected, and mantissa subtraction and rounding are performed at the same time so that precision cancellation does not occur by the first mantissa inverting means and the first mantissa adder. The mantissa adder of 2 simultaneously performs mantissa subtraction assuming rounding of 1 bit and rounding, and the addition / subtraction result selecting means selects one of the two mantissa subtraction results to which the rounding 1 is added at the correct bit position, If the rounding correction means does not cause cancellation of the sum, L
If a bit loss of 1 bit occurs, the G bit is corrected for rounding, and if a digit loss of 1 bit or more occurs by the normalizing means, post-operation normalization is performed.

In the case of true subtraction and when the exponent difference is 0, the small mantissa selecting means and the large mantissa selecting means respectively select different mantissa parts of the floating point number, and the first mantissa inverting means and the first mantissa inverting means. The mantissa adder subtracts the output of the small mantissa selection means from the output of the large mantissa selection means, and conversely the second mantissa inversion means, the third mantissa inversion means, and the second mantissa adder subtracts the output of the small mantissa selection means. After subtracting the output of the large mantissa selection means, the addition / subtraction result selection means selects one of the absolute values of the two mantissas which is the absolute value of them, and the normalization means performs calculation when a digit loss of 1 bit or more occurs. Apply normalization.

As described above, it is possible to calculate the sum or difference between the correctly rounded floating point numbers.

[0047]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the floating point addition / subtraction device of this embodiment. A source A bus 101 is a source of the floating point number A 1. For floating-point numbers on the bus, the sign part s _A is 1 bit, the exponent part e _A is the so-called gettering representation, and the exponent part of the IEEE standard has a predetermined bit length, and the mantissa part f _A is from U bits to L bits. It is represented by the bit length (M bits are hidden). However, in the floating floating point addition / subtraction device according to the present embodiment, V, M, G, R bits are added and V, M, U to L, G, R, bits are collectively handled.

A source B bus 102 is a floating point number B
Is the supplier. The bit length is the same as the source A bus 101. A destination bus 103 outputs an addition / subtraction result R of the floating point addition / subtraction device. The bit length is the same as the source A bus 101. Reference numeral 104 denotes a code generator, which generates a tentative calculation result code from the relationship between the two floating-point number codes, the operation type, and the two exponent magnitudes, and determines whether it is true addition or true subtraction. To do.

Reference numeral 105 denotes a sign inverter, which determines the sign of the true operation result from the magnitude comparison of two mantissas. An exponent subtractor 106 subtracts two exponents to discriminate the magnitude relationship between the two exponents and obtain an exponent difference. An exponent difference absolute value converter 107 obtains the absolute value of the exponent difference.

An exponent selector 108 selects one of the two exponents which is not smaller. An exponent incrementer 109 adds 1 to the exponent value. Reference numeral 110 denotes an exponent corrector, which subtracts the post-computation normalization correction value from the exponent value. Reference numeral 111 denotes a first mantissa selector (small mantissa selecting means) which selects a mantissa of a floating-point number having a smaller exponent, or selects one of the mantissas if the difference between the exponents of the two numbers is zero.

A second mantissa selector 112 (large mantissa selecting means) 112 selects a mantissa part different from the selection of the first mantissa selector. A mantissa right shifter 113 logically shifts the mantissa selected by the first mantissa selection unit to the lower side (hereinafter referred to as right) by the absolute value of the exponent difference. Reference numeral 114 is an S-bit generator, which is means for generating S-bits at the time of digit alignment.

Reference numeral 115 denotes a first mantissa inverting means which inverts the output of the mantissa right shift means in the case of true subtraction and passes the output of the mantissa right shift means in the case of true addition. 11
The second mantissa inverting means 6 inverts the output of the mantissa right shift means in the case of true subtraction and when the exponent difference is not 0, and passes it through in other cases. Reference numeral 117 denotes a third mantissa inverting means which inverts the output of the large mantissa selecting means in the case of true subtraction and when the exponent difference is 0, and passes it through in other cases.

Reference numeral 118 denotes a first mantissa adding means, which adds the output of the first mantissa inverting means and the output of the large mantissa selecting means in the case of true addition, and the first mantissa inversion means in the case of true subtraction. And the output of the large mantissa selecting means are added together with 1 for 2's complement conversion. At this time, at the same time, a rounding 1 is added to the bit one digit lower than the least significant bit. A second mantissa adding unit 119 adds the output of the second mantissa inverting unit and the output of the third mantissa inverting unit in the case of true addition, and the second mantissa inverting unit in the case of true subtraction. The output and the output of the third mantissa inverting means are added together with 1 for 2's complement conversion. At this time, in the case of true addition, a rounding 1 is added in advance to a bit one digit higher than the first mantissa adding means in the case of addition, and in the case of true subtraction, a rounding 1 is added in the first digit. 1 from the mantissa adding means
It is added to the lower bits of the digit beforehand.

Reference numeral 120 denotes a third mantissa selector which selects one of the two addition / subtraction results with a correct bit position added with a 1 for rounding, or a true subtraction and an exponent difference of 0. Is a means for selecting a positive mantissa difference. 121
Is a rounding corrector, which is the lowest 1 of the temporarily rounded addition / subtraction result
It is a means to correct bits and realize accurate rounding.

Reference numeral 122 denotes a leading one detector, which is a means for detecting the number of bits in which the mantissa difference has been canceled in the case of true subtraction.
A mantissa left shifter 123 is a means for normalizing the mantissa part when a digit loss occurs. The operation of the floating point addition / subtraction device according to the present embodiment configured as described above will be described below. In this embodiment, floating point numbers are added and subtracted by a three-stage pipeline process. In this embodiment, two floating-point numbers A are supplied from the source A bus 101 and the source B bus 102.
And B, and after adding or subtracting them, the result sum (A + B) or difference (A-B) is output to the destination bus 103. The outline of the three-stage pipeline processing will be described below.

<First stage> -The magnitudes of A and B are compared by the exponent part, and the mantissa part of the smaller one is aligned. -Temporarily determine the sign of the result based on the sign of the two floating-point numbers, the magnitude relationship, and the type of operation.

<Second stage> -Substantially adding and subtracting mantissa and rounding. In the case of true subtraction and if the exponent difference is 0, the final sign is determined by the mantissa magnitude judgment. <Third stage> ・ If a digit is lost, the mantissa part and the exponent part are normalized.

When the floating point numbers A and B are added or subtracted according to the present embodiment, the specific operation of the present embodiment will be described below separately for the case of true addition and the case of true subtraction. The rounding algorithm of the floating point addition / subtraction device of this embodiment is the same as that of the conventional example. In the following explanation of the operation, the actual operation of the circuit is kept in mind, and the fact is clearly stated even if the logic of each part is don't care or nothing is done. 1. In the case of true addition: Occurrence of overflow of the mantissa can be determined by setting the V bit of the sum obtained by the first mantissa adder 118 to 1. The third stage does not work in the case of true addition, and the sign, exponent,
The mantissa part passes through the third stage. Exponent difference in <First stage> (1.1) Index subtractor 106 (e _A - e _B) is calculated. (1.2) The absolute value of the index difference | e _A −e _B | is calculated in the index difference absolute value converter 107. (1.3) As a result of comparing the indices, the index selector 108
Select not smaller of _A and _{e B, max (e A,} e B)
Is output. (1.4) The code generator 104 determines a code based on (Table 2). Where the sign of the sum is s _A. (1.5) Of the two mantissa parts f _A and f _B , the first mantissa selector 111 selects the mantissa part with the smaller exponent, and selects it.
Let f _s . When the two exponent values e _A and e _B are equal, the first mantissa selector 111 may select any mantissa part, but selects a different one from the second mantissa selector 112. (1.6) Of the two mantissa parts f _A and f _B , the second mantissa selector 112 selects the mantissa part having the larger exponent, and selects it.
Let f _l . When the two exponent values e _A and e _B are equal, the second mantissa selector 112 may select any mantissa part, but as described in (1.5), the first mantissa selector 111 is Choose another one. (1.7) The mantissa right shifter 113 shifts f _s to the right by | e _A − e _B | bits. This is called digit alignment, representing a digit alignment has been f _s at f _s'. (1.8) The S-bit generator 114 takes the logical sum of all the bits spilled to the right of the R-bit of the mantissa at the time of the digit alignment and sets this as the S-bit. (1.9) Three mantissa bit inverters 11 based on (Table 10)
5,116,117 are passed through. <Second Stage> Based on (2.1) (Table 12), the second mantissa adder 119 simultaneously adds f _l and f _s ' and 1 for the L bit and rounds. (The bit position for adding 1 for complementing 2 will be described later.) (2.2) Based on (Table 11), the first mantissa adder 118 simultaneously adds 1 for f _l and f _s ' and G bits. And then round. If mantissa upper overflow occurs, jump to (2.5), otherwise proceed to the next. (2.3) Based on (Table 13), the third mantissa selector 120 selects the sum obtained by the first mantissa adder 118. (2.4) In the exponent incrementer 109 based on (Table 13),
Pass the value max (e _A , e _B ). Go to (2.7). (2.5) Based on (Table 13), the third mantissa selector 120 selects a value obtained by shifting the sum obtained by the second mantissa adder 119 by 1 bit to the right. (2.6) In the exponent incrementer 109 based on (Table 13),
Increase max (e _A , e _B ) by 1. (2.7) The rounding corrector 121 corrects the sum L bit for rounding based on (Table 14). (2.8) The code inverter 105 passes through the code determined in the first stage and sets it as s _R. <Third stage> (3.1) The leading 1 detector 122 scans to the right from the M bits of the rounded sum to search for the bit position where bit 1 first appears, and finds the distance between the bit position and the M bit. Two
Encode to a base number. In true addition, this distance is zero. (3.2) The mantissa left shifter 123 shifts the sum to the left by the number of bits obtained by the preceding 1 detector 122, thereby calculating the sum.
Adjust the mantissa so that the M bit is 1. Let f _R be the shifted mantissa. In true addition, the M bits of the mantissa are already 1, so no shift is performed. (3.3) In the exponent corrector 110, the difference obtained by subtracting the encoded left shift number from the corrected exponent part is taken as e _R. 0 for the number of left shifts encoded in true addition
Reduce. (End) 2. Case of True Subtraction The series of processing in the third stage of the pipeline is generally called post-operation normalization. Exponent difference in <First stage> (1.1) Index subtractor 106 (e _A - e _B) is calculated. (1.2) The absolute value of the index difference | e _A −e _B | is calculated in the index difference absolute value converter 107. If the index difference is 0, skip to (1.10), otherwise proceed to the next step. (1.3) As a result of comparing the indices, the index selector 108
Select whichever larger of _A and e _B, and outputs the _{max (e A, e B)} . (1.4) In the code generator 104, based on (Table 2) s _A
And s _B and the sign of (e _A − e _B ) determines the sign of the difference. (1.5) Of the two mantissa parts f _A and f _B , the first mantissa selector 111 selects the mantissa part with the smaller exponent, and selects it.
Let f _s . (1.6) Of the two mantissa parts f _A and f _B , the second mantissa selector 112 selects the mantissa part having the larger exponent, and selects it.
Let f _l . (1.7) Digitization of f _s is performed by the mantissa right shifter 113.
The digit alignment has been f _s represented by f _s'. (1.8) The S-bit generator 114 takes the logical sum of all the bits spilled to the right of the R-bit of the mantissa at the time of the digit alignment and sets this as the S-bit. (1.9) Based on (Table 10), the mantissa bit inverter 115,1
Invert all bits of f _s ' by 16. Bit inverted 'the! F _s' f _s represented by. Mantissa bit inversion 117 passes through all bits of f _l . <Second Stage> Based on (2.1) (Table 12), the second mantissa adder 119 simultaneously adds f ₁ and! F _s ' and 1 for complementing 1 and 2 for the R bit and rounds. (2.2) Based on (Table 11), the first mantissa adder 118 simultaneously adds f ₁ and! F _s ' and 1 for complementing 1 and 2 for G bits and rounds them. (2.3) On the basis of (Table 13), in the third mantissa selector 120, if the difference found in the first mantissa adder 118 has a precision loss, the difference found in the second mantissa adder 119 is selected. , Otherwise select the difference determined by the first mantissa adder 118. (2.4) In the exponent incrementer 109 based on (Table 13),
Pass the value max (e _A , e _B ). (2.5) The rounding corrector 121 corrects the difference L bit or G bit for rounding based on (Table 14). (2.6) The code inverter 105 passes through the code determined in the first stage and sets it as s _R. <Third Stage> (3.1) The leading 1 detector 122 scans to the right from the M bits of the rounded difference to search for the bit position where bit 1 first appears, and finds the distance between the bit position and M bits. Two
Encode to a base number. (3.2) The mantissa left shifter 123 adjusts the mantissa part so that the most significant bit of the difference becomes 1 by shifting the difference to the left by the number of bits obtained by the leading 1 detector 122. Let f _R be the shifted mantissa. (3.3) In the exponent corrector 110, the difference obtained by subtracting the encoded left shift number from the corrected exponent part is taken as e _R. (End) <Continuation of (1.2) (when index difference is 0)> (1.10) Either e _A or e _B is selected by the index selector 108 and output. (1.11) In the code generator 104, based on (Table 2) s _A
And s _B determine the sign of the difference. (1.12) Of the two mantissa parts f _A and f _B , the first mantissa selector 111 may select any mantissa part, but it selects a different one from the second mantissa selector 112. . (1.13) Of the two mantissa parts f _A and f _B , the second mantissa selector 112 may select any mantissa part, but as described in (1.11), the first mantissa selector 111 Choose a different one from. (1.14) to align digits the f _s by the temporary number right shifter 113.
Here, the shift number is 0. (1.15) In the S bit generator 114, the S bit, which is 0 in this case, is generated. Based on (1.16) (Table 10), the mantissa bit inverter 115 inverts all bits of f _s . Mantissa bit inverter 11
Invert all bits of f _l by 7. Bit inverted the f _s! At f _s, representing bit inverted the f _l at! F _l.
The mantissa bit inverter 116 allows all bits of f _s to pass through.

<Second Stage> (2.7) Based on (Table 11), the first mantissa adder 118 simultaneously adds f _s , f _l, and ₁ for 2's complement. (2.8) Based on (Table 12), the second mantissa adder 119 simultaneously adds f _s , f _l, and 1 for complementing 2. (2.9) Based on (Table 13), in the third mantissa selector 120, if the difference obtained by the first mantissa adder 118 is positive (positive when the V bit is 1), the first mantissa adder 118
If the difference obtained in step 1 is negative (negative when the V bit is 0), the difference obtained in the second mantissa adder 119 is selected. In the exponent incrementer 109 based on (2.10) (Table 13),
Exceed the value max (e _A , e _B ). Based on (2.11) (Table 14), the rounding compensator 121
Pass the selected difference. (2.12) If the difference obtained by the second mantissa adder 119 is negative, the sign inverter 105 inverts the sign determined in the first stage, otherwise the sign inverter 105 determines the sign determined in the first stage. And let this be s _R. Or later,
Continue to (3.1).

[0060]

[Table 10]

[0061]

[Table 11]

[0062]

[Table 12]

[0063]

[Table 13]

[0064]

[Table 14]

[0065]

[Table 15]

[0066]

[Table 16]

[0067]

[Table 17]

The validity of the floating point arithmetic method of the above embodiment according to the present invention will be mathematically examined. As an example, consider the legitimacy of the rounding logic for the case of the RN rounding mode of the previous embodiment. For two floating-point numbers A and B, 1 ≤ f _A <2 1 ≤ f _B <2 (Equation 1) 1 ≤ f _s <2 1 ≤ f _l <2. If f _s ' is the value after f _s is aligned, (Equation 2) 0 ≤ f _s '<2 where f _s ' = 0, all the valid bits of f _s are lost. That is the case. In the true addition of the two floating-point numbers A and B, 1 ≦ f _l + f _s ′ <4 from (Equation 1) and (Equation 2). First, when the sum of mantissas f _l + f _s 'is 1 ≤ f _l + f _s '<2, post-operation normalization is not necessary. Also, 1 for rounding is G
Is added to the bits. Secondly, in the case of 2 ≤ f _l + f _s '<4, the mantissa part overflows the mantissa, so the mantissa part is shifted to the right by 1 bit and 1 is added to the exponent. A 1 for rounding is added to the L bit beforehand. (Table 18)
As shown in, the mantissa upper overflow can be identified by the V bit.

Next, the basic procedure for the true subtraction of the two floating point numbers A and B will be described. First, it inverts all bits of the divisor (takes the complement of 1). Second, add the minuend, the bit-reversal number of the above-mentioned subtrahend, 1 for rounding, and 1 for 2's complement. The true subtraction algorithm greatly differs depending on whether the exponent difference is 0 or not. First, when the exponent difference is 0, -1 <f _l - a f _s <1. In this case, rounding is not necessary as an accurate difference is obtained. In the second step above, the rounding 1's are not added, but the 2's complementing 1's are added to the L bits.

In the case of −1 <f _l −f _s <0, in the second mantissa adder 119 in this embodiment.
Since f _s − f _l has been calculated, selecting it yields | f _l − f _s |. On the other hand, when 0 ≦ f _l −f _s <1, in the present embodiment, the first mantissa adder 118
Since f _l − f _s has been calculated, selecting it yields | f _l − f _s |.

[0071]

[Table 18]

Next, consider the case where the index difference is not zero. In this case 0 ≦ f _s '<range of 1 So _{differences, 0 <f l - f s} ' is <2. This range is divided into the following three parts. _{(1) 0 <f l -} f s'< can only occur if 1/2 exponent difference is 0 or 1. Since there is no need for rounding, it is the same as when the index difference is 0. (2) 1/2 ≤ f _l − f _s '<1 After adding 1 for rounding to the bit R of the mantissa difference, shift the mantissa part 1 bit to the left and subtract 1 from the exponent to normalize. The difference of the mantissa is obtained. This is the same as the addition of 1 for rounding to the bit G of the mantissa difference which is shifted to the left by 1 bit. (3) 1 ≤ f _l − f _s '<2 It is sufficient to add 1 for rounding to the bit G of the mantissa difference.

Consider further rounding and 2's complementing of the subtrahend in the case of true subtraction. After the reduction f _s is aligned,
All the bits are inverted by the first and second mantissa inverters 115 and 116. For subtraction, the minuend is reduced to f
'and the one's complement of meiotic f _{s' s} adds one of three parties in the LSB of. That is, to take the two's complement of the divisor f _s ' 1
You must add 1 to the LSB of the complement of. The problem is that some of the lower bits are lost because the divisors have been aligned. So we cannot add one to the LSB of the one's complement of the digitized fraction f _s '.

This problem can be solved by using the S bit of the reduction. (Fig. 4 (a)), (Fig. 4 (b)), (Fig. 5 (a)),
FIG. 5 (b) shows the mechanism of true subtraction in the mantissa part in the case where the difference range is the above (3), and description will be given along this line. In Fig. 4 (a), the minuend f _l is a normalized positive number, and the minuend f _s ' is a positive number already aligned, and its L
Bits that are virtually spilled to the right of the bits are shown, and these are actually the information that has already disappeared. First, considering the case where the difference range is (3) above, the difference
1 is added to the G bit.

Next, the 1's complement of the subtraction f _s 'is taken, and 1 is virtually added to the LSB of the subtraction f _s ' to obtain the 2's complement (FIG. 4 (b)). Although it is not possible to actually add 1 to the virtual LSB, it is possible to determine whether or not the carry by that virtual propagates up to the actual LSB as a result of adding the virtual 1 . This actual LSB is assumed to be R bits in consideration of the mantissa range (2) to be considered next. When the carry propagates from the 1's digit for 2's complement to the R bit, the digit is adjusted to the L of the reduction f _s '.
Only when the inversion of all bits z ₃ , z ₄ ... z _r spilled to the right of the bit is 1.

[0076] (number _{3)! Z 3! Z 4} ‥‥! Z r = 11 ‥‥ 1 Therefore _{z 3 z 4 ‥‥ z r =} 00 ‥‥ 0 ( FIG. 5 (a)) than all of the z _i ( The logical sum of i = 3,4, ..., r−1, r) is S, so S = 0 Therefore, if 1 is added to the actual LSB only when S is 0, the correct digit 2 The complement of is obtained. This condition is equivalent to adding! S to the actual LSB. At the same time, add 1 for rounding to the G bit (Fig. 5 (a)). After all
You can add 1 and! S to the G and R bits at the same time (Fig. 5 (b)).

From the same consideration, when the difference range is (2), true subtraction rounding can be realized by the logic shown in FIG. 6 (a). Adding! S and 1 for rounding to the R bit at the same time is equivalent to adding S and! S to the G bit and R bit at the same time (Fig. 6 (b)). (Table 19)
The bit positions for adding bits for rounding and 2's complementation in the two mantissa adders and the logical values based on those S bits are summarized.

[0078]

[Table 19]

In this embodiment, since processing is carried out in a three-stage pipeline, the processing proceeds while synchronizing the sign / exponent part / mantissa part of the floating-point number for each pipeline stage as described in the above operation. . Several combinations of timings for processing the three parts of the sign, exponent part, and mantissa part in each stage of the pipeline processing are conceivable in addition to the above. However, regarding the present invention, the processing timings in this embodiment and each stage thereof will be described. There is essentially no difference from the modified version of this embodiment. In this embodiment, the structure was designed with the intention that the circuit delays of the respective stages of the pipeline are as uniform as possible, but there may be different stage divisions according to other circuit configuration methods. The number of pipeline stages does not necessarily have to be 3, and the pipeline configuration of this embodiment is merely one implementation example of the algorithm of the present invention.

Here, only the situation where the normalized numbers are added or subtracted to obtain the sum or difference of the normalized numbers has been described. However, when one of the operands is a denormalized number or 0, or the operation result is non- It is clear that even if the number is a normalized number or 0, the calculation can be performed correctly without changing the above-mentioned arithmetic method.
However, it is necessary to add some circuits such as the exponent lower overflow detection mechanism.

The present embodiment will be compared in detail with the conventional floating point addition / subtraction device. The second stage of the embodiment is equivalent to the third stage of the conventional example, and the first stage of the embodiment is substantially equivalent to the second stage of the conventional example. Since the third stage of the embodiment and the first stage of the conventional example are portions for realizing processing unique to each other, an attempt is made to compare the circuit scales of the individual functional components at these different points. First, although two mantissa shifters are provided in both the embodiment and the conventional example, the mantissa shifter in the embodiment shifts only in one direction, left or right, whereas that in the conventional example shifts in both left and right directions. Secondly, the two mantissa selectors of the embodiment have the same scale as the conventional mantissa exchanger. Thirdly, the left shift encoder of the conventional example has a function larger than that of the preceding one detector because it includes the function of the preceding one detector of the embodiment and also has the function of the mantissa subtractor. Fourthly, the embodiment has two mantissa inverters which are not present in the prior art, but these are composed of only one stage of exclusive OR gates.
On the other hand, fifthly, the conventional example has a special exponent difference detection mechanism and a mantissa comparator comparable to the scale of the mantissa adder, which are not in the embodiment. From the above examination, it is proved that the embodiment significantly reduces the circuit scale as compared with the conventional example. Also, when actually designing the circuit, the third stage of the embodiment can be operated at a higher speed than the first stage of the conventional example. As a whole, according to the arithmetic method of this embodiment, a circuit configuration in which the critical path of the conventional example is greatly shortened can be realized.

As described above, in the case of floating point addition / subtraction, conventionally, a lot of hardware had to be put in order to predict post-computation normalization and post-computation 2's complementation of the mantissa before computation. According to the floating-point addition / subtraction device of this embodiment, the amount of hardware can be significantly reduced as compared with the conventional method, and as a result, the critical path of the circuit can be relaxed and the circuit can be operated at high speed.

[0083]

According to the floating point adder / subtractor of the present invention, a large number of arithmetic circuits had to be put in the first stage to predict the sign cancellation and the sign of the operation result. The prediction mechanism can be eliminated. Therefore, there is an effect that it is possible to integrate the floating point addition / subtraction processing equivalent to the conventional one with a very small circuit scale.

Moreover, in order to shorten the critical path as compared with the conventional floating point adder / subtractor, even if the number of pipeline stages is the same, there is an effect that a faster operation is possible by improving the clock frequency. The present invention realizes the conventional floating point adder / subtractor at a lower cost and at a higher speed, and therefore has a great practical effect.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional example.

FIG. 3 is a schematic diagram for explaining names of bit positions of a mantissa part.

FIG. 4 is a schematic diagram illustrating a nearest-value rounding method in true subtraction.

FIG. 5 Same as above (continued from FIG. 4).

FIG. 6 is a schematic diagram illustrating a nearest-value rounding method in true subtraction.

[Explanation of symbols]

 101 Source A Bus 102 Source B Bus 103 Destination Bus 104 Code Generator 105 Sign Inverter 106 Exponent Subtractor 107 Exponential Difference Absolute Quantizer 108 Exponent Selector 109 Exponent Incrementer 110 Exponent Corrector 111, 112, 120 Mantissa Selection Unit 113 Mantissa Right Shifter 114 S Bit Generator 115, 116, 117 Mantissa Inverter 118, 119 Mantissa Adder 121 Rounding Corrector 122 Preceding 1 Detector 123 Mantissa Left Shifter

Claims (5)

[Claims] 1. A floating-point addition / subtraction device for calculating the sum or difference of two floating-point numbers represented by signs, exponents, and mantissas, wherein the floating-point mantissa with the smaller exponent is on the lower side by the exponent difference. (Hereinafter referred to as the right), the digit alignment unit that aligns digits by shifting to, and the addition or subtraction of the digit-matched mantissa and the other mantissa,
If the exponent difference is 0, the addition / subtraction unit that subtracts the other mantissa from the other mantissa and simultaneously subtracts one from the other when subtraction is performed, and the number of bits that have been omitted for the subtracted mantissa is calculated. And a normalization unit that normalizes by subtracting the number of bits from the exponent, and the digit alignment unit subtracts two exponents in floating-point format,
Select the exponent subtracter that determines the absolute value of the exponent difference and the mantissa of the floating-point number with the smaller exponent of the two floating-point numbers, or select the exponent difference between the two numbers is 0. Then, a small mantissa selecting means for selecting one of the mantissas, a large mantissa selecting means for selecting the other mantissa different from the selection of the small mantissa selecting means, and a mantissa selected by the small mantissa selecting means are obtained by an exponent subtractor. And a mantissa right shift means for logically right-shifting the absolute value of the calculated exponent difference. The addition / subtraction unit subtracts two numbers with the same sign or adds two numbers with different signs (hereinafter abbreviated as true subtraction). In this case, the output of the mantissa right shift means is inverted, and the output of the mantissa right shift means is passed through in the case of addition of two numbers with the same sign or subtraction of two numbers with different signs (hereinafter abbreviated as true addition). Mantissa inversion means and in case of true subtraction and exponent difference If not, the second mantissa inverting means for inverting the output of the mantissa right shift means and passing through otherwise, and the output of the large mantissa selecting means for true subtraction and when the exponent difference is 0 A third mantissa inverting means for inverting, and otherwise passing through, and for true addition, adding the output of the first mantissa inverting means and the output of the large mantissa selecting means, and for true subtraction First mantissa adding means for adding the output of the first mantissa inverting means and the output of the large mantissa selecting means together with 1 for the 2's complement, and the output of the second mantissa inverting means in the case of true addition. A second mantissa that adds the outputs of the third mantissa inverting means and, in the case of true subtraction, adds the outputs of the second mantissa inverting means and the outputs of the third mantissa inverting means together with 1 for 2's complement conversion. In the case of true subtraction and the exponent difference is 0, the addition means The addition / subtraction result selection means for selecting a positive value from the two positive / negative subtraction results obtained from the mantissa addition means, and the normalization unit outputs a precision loss bit for the output of the addition / subtraction unit in the case of true subtraction. Based on the leading 1 detection means for obtaining the number and the number of bits obtained by the detection result of the leading 1 detection means,
A mantissa left shift means for shifting the output of the adder / subtractor to the left,
A floating-point adder / subtractor characterized by comprising. 2. A floating-point addition / subtraction device for calculating the sum or difference of two floating-point numbers represented by a sign, exponent, and mantissa, wherein the floating-point mantissa with the smaller exponent is on the lower side by the exponent difference. (Hereinafter referred to as the right), the digit alignment unit that aligns digits by shifting to, and the addition or subtraction of the digit-matched mantissa and the other mantissa,
If the exponent difference is 0, the addition / subtraction unit that subtracts the other mantissa from the other mantissa and simultaneously subtracts one from the other when subtraction is performed, and the number of bits with which the mantissa is subtracted is calculated. And a normalization unit that normalizes by subtracting the number of bits from the exponent, and the digit alignment unit subtracts two exponents in floating-point format,
Select the exponent subtracter that determines the absolute value of the exponent difference and the mantissa of the floating-point number with the smaller exponent of the two floating-point numbers, or select the exponent difference between the two numbers is 0. Then, a small mantissa selecting means for selecting one of the mantissas, a large mantissa selecting means for selecting the other mantissa different from the selection of the small mantissa selecting means, and a mantissa selected by the small mantissa selecting means are obtained by an exponent subtractor. And a mantissa right shift means that logically shifts to the right by the absolute value of the exponent difference, wherein the addition / subtraction unit inverts the output of the mantissa right shift means when true subtraction and when the exponent difference is not 0, In the other cases, the first mantissa inverting means for passing through, and in the case of true subtraction and when the exponent difference is 0, the output of the large mantissa selecting means is inverted, and in the other cases, for passing through. 2 mantissa inverting means and true subtraction In the case of inverting the output of the mantissa right shift means,
A third mantissa inverting means for passing the output of the mantissa right shift means through in the case of true addition, and an output of the first mantissa inverting means and an output of the second mantissa inversion means for the case of true addition, A first mantissa adding means for adding the output of the first mantissa inverting means and the output of the second mantissa inverting means together with a 1 for 2's complementation in the case of true subtraction, and a third mantissa in the case of true addition Output of the mantissa inverting means and the output of the large mantissa selecting means are added, and in the case of true subtraction, the output of the third mantissa inverting means and the output of the large mantissa selecting means are added together with 1 for 2's complement. In the case of true subtraction and the exponent difference is 0, the mantissa addition means of 2 is selected from the positive and negative subtraction results obtained from the first and second mantissa addition means. The normalization unit outputs the output of the addition / subtraction unit in the case of true subtraction. A leading one detector means for determining the number of canceling bits with the detection result of the leading one detection means based on the number of bits determined,
A mantissa left shift means for shifting the output of the adder / subtractor to the left,
A floating-point adder / subtractor characterized by comprising. 3. The first mantissa adding means adds 1 for rounding to the bit one digit lower than the least significant bit in advance at the time of addition, and the second mantissa adding means in the case of true addition. When adding, a rounding 1 is added in advance to a bit one digit higher than the first mantissa adding means, and in the case of true subtraction, a rounding 1 is added by one digit lower than the first mantissa adding means when adding. The addition / subtraction unit is further provided in advance, and the addition / subtraction unit further comprises rounding correction means for obtaining a correctly rounded addition / subtraction result by correcting the least significant bit of the output of the addition / subtraction result selection means. 1. The floating point addition / subtraction device according to 1 or 2. 4. The first and second mantissa adding means are: M bits for the most significant bit of the mantissa, V bits for a bit one digit higher than M bits, and U bits for a bit one digit lower than M bits. , Least significant bit is L bit, 1 from L bit
When the lower bit of the digit is G bit and the bit lower by one digit than the G bit is R bit, the bits are added with a bit width from V bit to R bit, and the digit aligning unit further performs digit aligning by the right shift means. Occasionally, the logical sum of all bits of the mantissa protruding below the R bit (hereinafter referred to as S bit)
The first mantissa adding means adds 1 for rounding to G bits in the case of true addition, and rounds in the case of true subtraction and if the exponent difference is not 0 1 of G is added to G bits, and S is used as 1 for complementing 2
The logical negation value of R bit is added to the R bit, and in the case of true subtraction and when the exponent difference is 0, 1 for rounding is not added and the logical negation value of S bit is set as R bit as 1 for complementing 2 In addition, the second mantissa adding means adds 1 for rounding to L bits in case of true addition, and 1 for rounding in case of true subtraction and exponent difference is not 0 to R bits. Add and add S as 1 for 2's complement
The logical negation value of the bit is added to the R bit, the 1 for rounding is not added in the case of true subtraction and the exponent difference is 0, and the logical negation value of the S bit is set as 1 for complementing 2 In addition to the bits, the addition / subtraction result selection means is configured to calculate the calculation result of the first mantissa addition means (hereinafter abbreviated as “step A”),
The calculation result of the mantissa adding means (hereinafter, abbreviated as “B”) and 1-bit left-shifted “B” (hereinafter abbreviated as “B”) are input, and in the case of true addition, if M bits do not overflow (V is If it is 0, select A, if it overflows from M bits, select V (if V is 1), and if true subtraction and the exponent difference is not 0, the M bits are digits. If it is not dropped (if M is 1), select Instep. If it is dropped by 1-bit digit (If M is 0 and U is 1), select B. If (M
If A is 0 and U is 0), choose A, and if true subtraction and the exponent difference is 0, choose A if A is positive, and choose A if A is negative. The rounding correction means selects if the instep is 1 or more based on the S bit and the instep (M is 1).
If the L-bit of the output of the addition / subtraction result selection means (hereinafter abbreviated as "D") is corrected to 1/2 or more and less than 1 (M is 0 and U is 1) 4. The floating point adder / subtractor according to claim 3, wherein the G bit is corrected, and if it is neither of them, the Ding is passed through. 5. The rounding correction means sets the L bit to 0 when the L bit is 1 and the logical sum of the values of the G bit, the R bit and the S bit is 0 when correcting the L bit. The G bit is set to 0 when the G bit is 1 and the logical sum of the values of the R bit and the S bit is 0 when correcting the G bit. Floating point adder / subtractor.