JPH06349940A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To relax the base of a U-shaped groove provided onto the surface of an SOI substrate in distortion so as to restrain crystal defects from occurring in a semiconductor integrated circuit device wherein the surface of the SOI substrate is isolated by insulation with a U-shaped groove for the formation of an element. CONSTITUTION:When A silicon layer 3 and an epitaxial layer 7 formed on the surface of an SOI substrate are etched for the formation of an element isolating U-shaped groove 17 which reaches a lower silicon oxide film 2, the silicon oxide film 2 on the base of the U-shaped groove 17 is isotropically etched to provide an undercut U to an interface between the silicon oxide film 2 and the silicon layer 3. The undercut U serves to absorb and relax distortions generated at the base of the U-shaped groove 17 when a silicon oxide film is formed on the side face of the U-shaped groove 17 by thermally treating the SOI substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device having an SOI (Silicon on insulator) structure.

[0002]

2. Description of the Related Art In recent years, integrated circuits have been formed using an SOI substrate in order to improve device characteristics such as reduction of parasitic capacitance of devices and improvement of α-ray soft error resistance aiming at higher speed and higher integration of semiconductor integrated circuits. The technology to do so is being put to practical use.

An example in which a bipolar integrated circuit device is constructed using this SOI substrate is, for example, "ECS (Electro C
hemical Society) '91 Fall Meeting 'Extended Ab
stract, P.744. In this bipolar type integrated circuit device, as shown in FIG. 17, a silicon oxide film 2 to be an insulating film is formed on the surface of a lower silicon substrate 1 to be a supporting substrate, and a single crystal silicon layer 3 is further formed thereon. The formed one is used as an SOI substrate.

The silicon layer 3 is formed as a buried layer into which n-type impurities are introduced. Elements such as a bipolar transistor are formed on the surface of the epitaxial layer 7 grown on the silicon layer 3 and are insulated from each other by a deep U groove 17 reaching the silicon oxide film 2.
A polycrystalline silicon film is buried in the U groove 17 via a silicon oxide film (thermal oxide film) formed by thermal oxidation.

[0005]

However, the above-mentioned prior art in which the surface of the SOI substrate is insulated and separated by the U groove to form the element has the following problems.

To form a U groove in an SOI substrate, the epitaxial layer and the underlying silicon layer are etched to form a deep groove reaching the silicon oxide film, and then a thermal oxide film is formed on the side surface of this groove. Then, a method is used in which a polycrystalline silicon film is embedded in the groove, the surface thereof is flattened by etching back, and finally a thermal oxide film is formed on the surface of the polycrystalline silicon film.

However, as shown enlarged in FIG.
When the thermal oxide film 4 is formed on the side surface of the U groove 17, the interface between the silicon oxide film 2 at the bottom of the groove and the silicon layer 3 above it (the area indicated by the arrow in the figure) is oxidized in a so-called bird's beak shape. Since the volume expands, strain occurs in this region and crystal defects such as dislocations occur, which causes leakage in the device and reduces device reliability and manufacturing yield.

In this case, it is possible to reduce the strain by suppressing the film thickness of the thermal oxide film on the side surface of the U groove and suppress the generation of crystal defects. However, since the parasitic capacitance between the polycrystalline silicon film and the surrounding silicon layer or epitaxial layer increases, the operating speed of the device decreases.

If the material for filling the U groove is replaced with an insulating material such as a silicon oxide film instead of the polycrystalline silicon film, increase in parasitic capacitance can be prevented without forming a thermal oxide film on the side surface of the U groove. However, in this case, since the thermal expansion coefficient between the silicon oxide film embedded in the U groove and the surrounding silicon layer or epitaxial layer is significantly different, if a high temperature heat treatment is performed in the subsequent process. There is a problem that crystal defects occur.

An object of the present invention is to reduce crystal defects in the U groove without deteriorating the characteristics of the element in a semiconductor integrated circuit device in which the surface of an SOI substrate is insulated and separated by a U groove to form an element. To provide the technology.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) According to the first aspect of the invention, when the silicon layer of the SOI substrate is etched to open a U groove for element isolation which reaches the silicon oxide film below the SOI layer, the bottom of the U groove is formed. The silicon oxide film is undercut.

(2) In the invention according to claim 4, after the silicon oxide film on the bottom of the U groove is undercut, a second silicon oxide film is embedded inside the U groove to form a first silicon oxide film on the bottom of the U groove. Cavities are formed in the second silicon oxide film.

(3) The invention according to claim 5 is to form an oxidation resistant film between the silicon substrate of the SOI substrate and the silicon oxide film.

(4) According to the invention of claim 6, after etching the silicon layer of the SOI substrate to open a U-shaped groove having an inverse taper shape that reaches the silicon oxide film below it, the U-shaped groove is formed inside the U-shaped groove. The second silicon oxide film is buried to form a cavity in the second silicon oxide film at the bottom of the U groove.

[0017]

According to the above-mentioned means (1), the silicon oxide film at the bottom of the U groove is undercut, and thereafter,
When a thermal oxide film is formed on the side surface of the U-groove, the interface between the silicon oxide film at the bottom of the U-groove and the silicon layer above the U-groove expands in volume in the space direction caused by the undercut.
The strain in this region is relaxed, and the generation of crystal defects such as dislocations is suppressed.

Even when an insulating film such as a silicon oxide film is buried in place of the means for forming the thermal oxide film on the side surface of the U groove, the heat between the insulating film and the surrounding silicon layer or epitaxial layer is increased. Since the strain caused by the difference in the expansion coefficient is relaxed by the existence of the space generated by the undercut, the generation of crystal defects is suppressed.

According to the above-mentioned means (2), the cavity formed in the silicon oxide film at the bottom of the U groove is caused by the difference in the coefficient of thermal expansion between the silicon oxide film and the surrounding silicon layer or epitaxial layer. Since the generated strain is absorbed and relaxed, the generation of crystal defects is suppressed.

According to the above means (3), by providing an oxidation resistant film between the silicon substrate of the SOI substrate and the silicon oxide film, the surface of the silicon substrate is oxidized at the bottom of the U groove and the volume is increased. Since expansion does not occur, it is possible to prevent the occurrence of strain due to this volume expansion.

According to the above-mentioned means (4), the U-groove is opened in a reverse taper shape so that the second oxide embedded in the U-groove can be formed without undercutting the silicon oxide film at the bottom of the U-groove. A cavity can be easily formed at the bottom of the silicon film.

[0022]

Embodiments of the present invention will now be described in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of an essential part of an SOI substrate showing an example of a bipolar integrated circuit device manufactured according to this embodiment.

The SOI substrate is composed of a lower silicon substrate 1 serving as a support substrate, a silicon oxide film 2 having a film thickness of about 1 μm formed on the surface thereof, and a silicon layer 3 formed thereon. There is. The silicon layer 3 is made of single crystal silicon doped with n-type impurities, and a part of the silicon layer 3 constitutes the n ⁺ buried layer 6 of the bipolar transistor. On this n ⁺ buried layer 6, an n type epitaxial layer 7 forming the collector region of the bipolar transistor is formed.

In the silicon layer 3 and the epitaxial layer 7, a deep U for element isolation reaching the silicon oxide film 2 is formed.
The groove 17 is formed. A thin silicon oxide film (thermal oxide film) 4 having a film thickness of about 100 nm is formed on the inner side surface of the U groove 17, and a polycrystalline silicon film 5 is embedded inside the thin silicon oxide film (thermal oxide film) 4. The surface of this polycrystalline silicon film 5 (U
A thin silicon oxide film (thermal oxide film) 18 is formed in the opening of the groove 17. The U groove 17 of this embodiment is characterized in that the silicon oxide film 2 on the bottom thereof is undercut by a method described later.

A p-type semiconductor region 8 forming a base region of a bipolar transistor is formed on the surface of the epitaxial layer 7 surrounded by the U groove 17, and a part of the surface of the p-type semiconductor region 8 is formed. Has an n-type semiconductor region 9 forming the emitter region of the bipolar transistor.

An n-type polycrystalline silicon film (emitter extraction electrode) 12 is connected to the n-type semiconductor region 9 through a connection hole 11 formed by opening an insulating film 10. A metal wiring 15 is connected to the n-type polycrystalline silicon film 12 through a connection hole 14 formed by opening an insulating film 13. Similarly, p forming the base region
The metal wiring 2 is formed in each of the epitaxial layer 7 forming the type semiconductor region 8 and the collector region through the connection holes 19 and 20 formed by opening the insulating films 10 and 13, respectively.
1, 22 are connected.

Next, a method of manufacturing the U groove 17 according to this embodiment will be described with reference to FIGS.

First, the silicon substrate 1 and the silicon oxide film 2
And a silicon layer 3 are prepared, an n type impurity is introduced into the silicon layer 3 of the SOI substrate to form an n ⁺ buried layer 6, and then an n type epitaxial layer 7 is formed thereon. Grow. Next, the epitaxial layer 7 and the silicon layer 3 are sequentially etched to form a U groove 17 reaching the silicon oxide film 2. At this time, at the final stage of etching, that is, when the silicon oxide film 2 starts to be exposed at the bottom of the U groove 17, the surface of the silicon oxide film 2 is isotropically etched using an isotropic etching solution such as hydrofluoric acid. Etching is performed to form an undercut portion U (a portion indicated by an arrow in FIG. 2) at the interface between the silicon oxide film 2 and the silicon layer 3 at the bottom of the U groove 17.

Next, as shown in FIG. 3, the SOI substrate is heat-treated to form a silicon oxide film 4 on the side surface of the U groove 17. The silicon oxide film 4 has a thickness of, for example, 1 to prevent the parasitic capacitance between the polycrystalline silicon film 5 embedded in the U groove 17 and the surrounding silicon layer 3 and epitaxial layer 7 from increasing.
It is formed with a film thickness of 00 nm or more. The undercut amount of the undercut portion U is preferably as large as the film thickness of the silicon oxide film 4 in order to alleviate strain at the bottom of the U groove 17, but practically equal to or more than that, and preferably Is preferably twice (200 nm) or more.

However, if the amount of this undercut is too large, the silicon oxide film 2 (the portion shown by the arrow in FIG. 3) at the bottom of the U groove 17 is etched more than necessary and the film thickness becomes thin, so that the SOI substrate When the silicon oxide film 4 is formed on the side surface of the U groove 17 by heat treatment, the surface of the silicon substrate 1 is oxidized at the bottom of the U groove 17 to cause volume expansion and distortion occurs.

Therefore, the film thickness of the silicon oxide film 2 remaining on the bottom of the U groove 17 after undercut is approximately twice (200 nm) the film thickness of the silicon oxide film 4 on the side surface of the U groove 17.
It is desirable to set as above (800 nm in this embodiment). Alternatively, as shown in FIG. 4, the silicon nitride film 1 is formed between the silicon substrate 1 and the silicon oxide film 2.
An SOI substrate provided with an oxidation resistant film such as 6 may be used. When such an SOI substrate is used, even if the undercut amount of the silicon oxide film 2 is increased, the silicon nitride film 1
Since 6 is not etched, the surface of silicon substrate 1 is not oxidized at the bottom of U groove 17.

Next, as shown in FIG. 5, a polycrystalline silicon film 5 is deposited on the epitaxial layer 7 by the CVD method to form U.
After embedding in the groove 17, the surface of the polycrystalline silicon film 5 is flattened by etching back as shown in FIG. 6, and further, as shown in FIG.
By forming the silicon oxide film 18 on the surface of the polycrystalline silicon film 5 in the opening of No. 7, the U trench 17 for element isolation is completed.

After that, the bipolar transistor shown in FIG. 1 is formed in the active region of the epitaxial layer 7 surrounded by the U groove 17 according to a normal manufacturing process of a bipolar integrated circuit.

(Embodiment 2) A method of manufacturing a U groove according to this embodiment will be described with reference to FIGS.

First, an SOI substrate similar to that of the first embodiment is prepared, an epitaxial layer 7 is formed on the silicon layer 3, and then the epitaxial layer 7 and the silicon layer 3 are sequentially etched as shown in FIG. Then, a U groove 17 reaching the silicon oxide film 2 is formed. At this time, the undercut portion U is formed at the interface between the silicon oxide film 2 and the silicon layer 3 at the bottom of the U groove 17 by the same method as in the first embodiment.

Next, a silicon oxide film 23 is deposited on the epitaxial layer 7 and buried in the U groove 17, and then the surface of the silicon oxide film 23 is flattened by etching back, as shown in FIG. At this time, the silicon oxide film 23
Is deposited by a low pressure CVD method to form a cavity 24 which is not filled with the silicon oxide film 23 at the bottom of the U groove 17. Then, as in the case of the first embodiment, a bipolar transistor is formed in the active region of the epitaxial layer 7 surrounded by the U groove 17 according to a normal manufacturing process of a bipolar integrated circuit.

In order to satisfactorily form the cavity 24, it is desirable that the undercut amount of the silicon oxide film 2 be equal to or larger than the inner diameter of the U groove 17. Alternatively, FIG.
As shown in FIG. 0, the silicon oxide film 2 is anisotropically etched to deeply form the U groove 17, and thereafter, the undercut portion U is formed by isotropic etching as shown in FIG. The cavity 24 can be satisfactorily formed without increasing the cut amount.

As described above, in the present embodiment, since the thermal oxide film is not formed on the side surface of the U groove 17, it is possible to prevent the generation of strain due to the formation of the thermal oxide film, and the inside of the U groove 17 can be prevented. Since the insulating film (silicon oxide film 23) is embedded in the
It is possible to prevent an increase in parasitic capacitance and realize high-speed operation of the element.

Further, the silicon oxide film 23 buried in the U groove 17 and the silicon layer 3 and the epitaxial layer 7 around it are formed.
Since the cavities 24 can alleviate the strain caused by the difference in the coefficient of thermal expansion between and, crystal defects are less likely to occur even if high-temperature heat treatment is performed in the subsequent step.

(Embodiment 3) In this embodiment, the above-mentioned embodiment 1 is used.
An SOI substrate similar to the above is prepared, and the U layer 17 reaching the silicon oxide film 2 is formed by etching the silicon layer 3 and the epitaxial layer 7. At this time, as shown in FIG. Etching is performed under the condition that the taper shape (overhang shape) is reversed.

Thereafter, as in the second embodiment, the silicon oxide film 23 is deposited by the low pressure CVD method to form a cavity 24 which is not filled with the silicon oxide film 23 at the bottom of the U groove 17, as shown in FIG. .

According to this embodiment, since the U groove 17 is formed in the reverse taper shape, the cavity 24 can be easily formed without providing the undercut portion in the silicon oxide film at the bottom thereof. The same effect as that of the second embodiment can be obtained with fewer manufacturing steps.

(Fourth Embodiment) In the first to third embodiments, an example in which the method is applied to a method of manufacturing a bipolar integrated circuit device has been described, but the present invention is not limited to this, and U of the SOI substrate is not limited to this.
It can also be applied to a method of manufacturing a MOS type integrated circuit or a bipolar-CMOS type integrated circuit in which an element is formed in an active region surrounded by a groove.

As an example, an example in which the present invention is applied to a method for manufacturing a MOS type integrated circuit will be described with reference to FIGS.

First, as shown in FIG. 14, it is composed of a lower silicon substrate 1 to be a supporting substrate, a silicon oxide film 2 formed on the surface thereof, and a silicon layer 3 formed thereon. An SOI substrate is prepared and the silicon layer 3 is etched to form a U groove 17 reaching the silicon oxide film 2. At this time, similarly to the first embodiment, the surface of the silicon oxide film 2 is isotropically etched using an isotropic etching solution such as hydrofluoric acid, so that the silicon oxide film 2 and the silicon layer at the bottom of the U groove 17 are etched. An undercut portion U is formed at the interface with 3.

Next, as shown in FIG. 15, the SOI substrate is heat-treated to form the silicon oxide film 4 on the side surface of the U groove 17, and then the silicon oxide film 23 is formed inside the U groove 17 by the CVD method. Embedding and flattening the surface by etch back.

Thereafter, as shown in FIG. 16, a semiconductor region (source region, drain region) 25 of the MOSFET is formed in the active region of the silicon layer 3 surrounded by the U groove 17 according to a normal manufacturing process of a MOS type integrated circuit. Then, the gate insulating film 26 and the gate electrode 27 are formed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

[0050]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the present invention, by undercutting the silicon oxide film at the bottom of the U-groove, U
When the thermal oxide film is formed on the side surface of the groove, the interface between the silicon oxide film at the bottom of the U groove and the silicon layer above the U groove expands in volume in the space direction caused by the undercut, and strain in this region is relaxed. The generation of crystal defects such as dislocations is suppressed.

Even when an insulating film such as a silicon oxide film is buried in place of the means for forming the thermal oxide film on the side surface of the U groove, the heat between the insulating film and the surrounding silicon layer or epitaxial layer is increased. Since the strain caused by the difference in the expansion coefficient is relaxed by the existence of the space generated by the undercut, the generation of crystal defects is suppressed.

(2) According to the present invention, by forming a cavity at the bottom of the insulating film embedded in the U-groove, the strain generated in the U-groove is absorbed and relaxed by this cavity. The effect can be obtained.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of an SOI substrate showing an example of a bipolar integrated circuit device manufactured according to the present invention.

FIG. 2 is a sectional view of an essential part of an SOI substrate showing a method of manufacturing a U-groove that is an embodiment of the present invention.

FIG. 3 is a cross-sectional view of an essential part of an SOI substrate showing a method of manufacturing a U-groove that is an embodiment of the present invention.

FIG. 4 is a cross-sectional view of an essential part of an SOI substrate showing a method of manufacturing a U-groove that is an embodiment of the present invention.

FIG. 5 is a cross-sectional view of an essential part of an SOI substrate showing a method of manufacturing a U groove that is an embodiment of the present invention.

FIG. 6 is a cross-sectional view of an essential part of an SOI substrate showing a method of manufacturing a U groove that is an embodiment of the present invention.

FIG. 7 is a cross-sectional view of an essential part of an SOI substrate showing a method of manufacturing a U-groove that is an embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 10 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 11 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of an SOI substrate showing a method of manufacturing a U-groove that is another embodiment of the present invention.

FIG. 14 is a fragmentary cross-sectional view of an SOI substrate showing an example of a method of manufacturing a MOS integrated circuit device to which a U groove of the present invention is applied.

FIG. 15 is a fragmentary cross-sectional view of an SOI substrate showing an example of a method of manufacturing a MOS integrated circuit device to which a U groove of the present invention is applied.

FIG. 16 is a fragmentary cross-sectional view of the SOI substrate showing an example of the method of manufacturing the MOS type integrated circuit device to which the U groove of the present invention is applied.

FIG. 17 is a main-portion cross-sectional view of an SOI substrate showing a conventional bipolar integrated circuit device using a U groove.

FIG. 18 is an enlarged cross-sectional view of the main parts of FIG.

[Explanation of symbols]

1 Silicon Substrate 2 Silicon Oxide Film 3 Silicon Layer 4 Silicon Oxide Film (Thermal Oxide Film) 5 Polycrystalline Silicon Film 6 n ⁺ Buried Layer 7 Epitaxial Layer 8 p-type Semiconductor Region (base Region) 9 n-type Semiconductor Region (emitter Region) DESCRIPTION OF SYMBOLS 10 Insulating film 11 Connection hole 12 n-type polycrystalline silicon film (emitter extraction electrode) 13 Insulating film 14 Connection hole 15 Metal wiring 16 Silicon nitride film 17 U groove 18 Silicon oxide film (thermal oxide film) 19 Connection hole 20 Connection hole 21 Metal wiring 22 Metal wiring 23 Silicon oxide film 24 Cavity 25 Semiconductor region (source region, drain region) 26 Gate insulating film 27 Gate electrode U Undercut part

Claims (6)

[Claims] 1. A U-groove is formed in the silicon layer of an SOI substrate in which a silicon layer is formed on a silicon substrate via a silicon oxide film, and a semiconductor device is formed in an active region of the silicon layer which is insulated and separated by the U-groove. A method of manufacturing a semiconductor integrated circuit device, comprising: etching a silicon layer to open a U-groove reaching the silicon oxide film below the silicon layer; and undercutting the silicon oxide film at the bottom of the U-groove. A method for manufacturing a semiconductor integrated circuit device, which comprises cutting. 2. A thermal oxide film is formed on a side surface of the U groove after undercutting the silicon oxide film at the bottom of the U groove, and then a polycrystalline silicon film is embedded inside the U groove. The method for manufacturing a semiconductor integrated circuit device according to claim 1. 3. The semiconductor integrated device according to claim 2, wherein the undercut amount of the silicon oxide film is equal to or more than twice the film thickness of the thermal oxide film formed on the side surface of the U groove. Method of manufacturing circuit device. 4. The undercut of the silicon oxide film at the bottom of the U-groove, followed by burying a second silicon oxide film inside the U-groove, in the second silicon oxide film at the bottom of the U-groove. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a cavity is formed in the semiconductor device. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein an SOI substrate having an oxidation resistant film formed between the silicon substrate and the silicon oxide film is used. . 6. A U-groove is formed in the silicon layer of an SOI substrate in which a silicon layer is formed on a silicon substrate via a silicon oxide film, and a semiconductor device is formed in an active region of the silicon layer which is insulated and separated by the U-groove. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a reverse tapered U groove reaching the silicon oxide film below the silicon layer by etching the silicon layer, and then forming a second groove inside the U groove. 2. A method for manufacturing a semiconductor integrated circuit device, comprising: burying the silicon oxide film of, and forming a cavity in the second silicon oxide film at the bottom of the U groove.