JPH06334064A - Leadless surface mounting hybrid ic - Google Patents
Leadless surface mounting hybrid icInfo
- Publication number
- JPH06334064A JPH06334064A JP21412893A JP21412893A JPH06334064A JP H06334064 A JPH06334064 A JP H06334064A JP 21412893 A JP21412893 A JP 21412893A JP 21412893 A JP21412893 A JP 21412893A JP H06334064 A JPH06334064 A JP H06334064A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- mounting
- hybrid
- leadless
- connection terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明はリードレス面実装型ハイ
ブリッドICおよびその製造方法に係り、さらに詳しく
はマザーボードへの実装に適するよう改良したリードレ
ス面実装型ハイブリッドICに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a leadless surface mount hybrid IC and a method of manufacturing the same, and more particularly to a leadless surface mount hybrid IC improved for mounting on a motherboard.
【0002】[0002]
【従来の技術】電子機器の高密度化、高機能化を達成す
るために、チップタイプ,フラットパッケージタイプな
どの実装部品を、いわゆる配線板の主面に搭載・実装し
て成る実装回路装置が広く実用に供されている。また、
この種の実装回路装置の構成においては、さらなる高機
能化や量産性などを考慮して、配線板面に所定の電子部
品を実装し、一定の回路を形成して成るいわゆるハイブ
リッドICを、マザーボードと称される主配線板の所定
領域に配置・実装する構成も採られている。そして、上
記マザーボードにハイブリッドICを実装する多段的な
実装構成においは、マザーボード面の効率的な利用性、
および実装操作性などの点から、実装するハイブリッド
ICとして、図3に断面的に示すような構成を成すリー
ドレス面実装型ハイブリッドICが注目され、また多く
使用されている。2. Description of the Related Art In order to achieve higher density and higher functionality of electronic equipment, there is a mounting circuit device in which mounting components such as chip type and flat package type are mounted and mounted on the main surface of a so-called wiring board. Widely used for practical use. Also,
In the construction of a mounting circuit device of this type, a so-called hybrid IC in which predetermined electronic components are mounted on a wiring board surface to form a certain circuit in consideration of higher functionality and mass productivity, is used as a mother board. A configuration is also adopted in which the main wiring board is placed and mounted in a predetermined area. Further, in the multi-stage mounting configuration in which the hybrid IC is mounted on the motherboard, the efficient utilization of the motherboard surface,
In terms of mounting operability and the like, as a hybrid IC to be mounted, a leadless surface mounting type hybrid IC having a configuration shown in a sectional view in FIG. 3 has attracted attention and is often used.
【0003】なお、図3において、1はたとえば厚膜配
線基板などの配線板、2はたとえば金属製キャップであ
り、前記配線板1の一主面に実装された所要の電子部
品、たとえば半導体素子,低抗体,コンデンサなどを保
護したり、あるいは電磁シールドの役割を果たしてい
る。3は前記配線板1の裏面側に導出された厚膜パター
ンから成る接続用端子(電極パッド)、4は前記接続用
端子(電極パッド)面に、たとえば印刷・リフローで被
覆・配置した半田コート層である。In FIG. 3, reference numeral 1 is a wiring board such as a thick film wiring board, and 2 is a metal cap, for example, and required electronic components mounted on one main surface of the wiring board 1, for example, a semiconductor element. , Protects low antibodies, capacitors, etc., or acts as an electromagnetic shield. 3 is a connection terminal (electrode pad) formed of a thick film pattern led out to the back surface side of the wiring board 1, and 4 is a solder coat which is coated / disposed on the connection terminal (electrode pad) surface by, for example, printing or reflowing. It is a layer.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上記構
成のリードレス面実装型ハイブリッドICの場合には、
実用上次のような不都合な問題が往々生じる。すなわ
ち、実装用の主配線板(マザーボード)の所定領域面
に、前記リードレス面実装型ハイブリッドICを実装す
る段階において、前記接続用端子3面の半田コート層4
が、全体的に一定の厚さ(高さ)でないうえに突起状を
成しているため、マザーボードの被接続端子(電極)面
に対して、確実な対接状態を保持し難いし、また位置ズ
レなども生じ易いので、信頼性の高い半田付け・接合を
達成し得ないことがしばしば起こる。この点さらに詳述
すると、前記接続用端子3面の半田コート層4は、一般
的に共晶クリーム半田を印刷し、リフローなどにより半
田コートして形成されるため、その半田コートの段階で
溶融した半田が、表面張力によってそれぞれ膨らみを有
する半球状を呈する。そして、この膨らみを有する半球
状化は、高さのバラツキ発生を招来するばかりでなく、
接触面(頂点)も低減化するので信頼性の高い半田つけ
に支障をもたらす恐れが多分にある。However, in the case of the leadless surface mount type hybrid IC having the above configuration,
In practice, the following inconvenient problems often occur. That is, at the stage of mounting the leadless surface-mounting hybrid IC on a predetermined area surface of a mounting main wiring board (motherboard), the solder coat layer 4 on the surface of the connecting terminal 3 is mounted.
However, since it is not a uniform thickness (height) as a whole and has a projection shape, it is difficult to maintain a reliable contact state with the connected terminal (electrode) surface of the motherboard. Positional deviation and the like are likely to occur, so that it often happens that reliable soldering and joining cannot be achieved. More specifically, the solder coat layer 4 on the surface of the connection terminal 3 is generally formed by printing eutectic cream solder and solder-coating it by reflowing. The solder thus formed has a hemispherical shape having bulges due to surface tension. And the hemispherical shape having this bulge not only causes the occurrence of height variations, but also
Since the contact surface (apex) is also reduced, there is a possibility that it will hinder reliable soldering.
【0005】一方、この種のリードレス面実装型ハイブ
リッドICは、マザーボードへの実装に先立って、個別
に(もしくは抜き取り)特性検査を行うが、前記接続用
端子3面上の半田コート層4の厚(高さ)のバラツキや
突起状などに起因して、測定治具(検査装置)の接続端
子との接続不良なども起こり易いので、特性検査の操作
が煩雑化するという問題がある。On the other hand, this type of leadless surface mounting type hybrid IC is subjected to individual (or extraction) characteristic inspection prior to mounting on a mother board, but the solder coat layer 4 on the surface of the connection terminal 3 is used. Due to variations in thickness (height), protrusions, and the like, poor connection with the connection terminals of the measurement jig (inspection device) is likely to occur, which complicates the characteristic inspection operation.
【0006】本発明はこのような事情に対処してなされ
たもので、実装に先立っての特性検査なども高精度に行
い得るとともに、マザーボード面へ実装操作なども大幅
に改善し得るリードレス面実装型ハイブリッドICの提
供を目的とする。The present invention has been made in consideration of such circumstances, and a leadless surface which can perform characteristic inspection prior to mounting with high accuracy and can greatly improve mounting operation on a motherboard surface. The purpose is to provide a mounted hybrid IC.
【0007】[0007]
【課題を解決するための手段】本発明のリードレス面実
装型ハイブリッドICは、少なくとも裏面側に半田コー
トされた接続用端子が導出されて成るリードレス面実装
型ハイブリッドICにおいて、前記裏面側に導出された
接続用端子面の半田コート層が平坦面化されていること
を特徴とする。また、この構成において、要すれば、前
記接続用端子面の半田コート層周辺部に、この半田コー
ト層面と同一面もしくは低面を成すレジスト層を配置し
た構成とすることを特徴とする。The leadless surface-mounting hybrid IC of the present invention is a leadless surface-mounting hybrid IC in which at least a connection terminal solder-coated on the back surface side is led out, and the leadless surface-mounting hybrid IC is formed on the back surface side. It is characterized in that the lead-out solder coating layer on the connection terminal surface is flattened. Further, in this configuration, if necessary, a resist layer that is flush with or lower than the surface of the solder coat layer on the surface of the connection terminal is disposed on the periphery of the solder coat layer.
【0008】本発明において、接続用端子面の半田層
は、この種の電子部品で電気的な接続用に使用されてい
る半田、たとえば63%Sn−37%Pbなど各種の共晶半田の
他に、固相線温度および液相線温度を有する半田などを
用いて形成することも可能である。そして、前記共晶半
田で形成した場合は、単純な溶融・凝固過程および良好
な流動性などの特長を利用し、また固相線温度および液
相線温度を有する半田で形成した場合は、軟化状態もし
くは緩やかな溶融性などによって、高さないし厚さが一
様な平坦面化処理など、より行い易いという特長が利用
される。In the present invention, the solder layer on the connection terminal surface is a solder used for electrical connection in this type of electronic component, such as various eutectic solders such as 63% Sn-37% Pb. In addition, it is also possible to form using solder having a solidus temperature and a liquidus temperature. When the eutectic solder is used, the features such as simple melting and solidification process and good fluidity are utilized, and when it is formed with the solder having the solidus temperature and the liquidus temperature, it is softened. Depending on the state or the gradual melting property, it is easier to perform the flattening process with a uniform thickness.
【0009】なお、前記接続用端子面に被着形成された
半田コート層の平坦面化は、たとえば印刷・付着した半
田を一旦溶融・硬化した後、再度固相線温度から液相線
温度まで熱して軟化してから、あるいは前記固相線温度
と液相線温度との間の温度下で、平板(面)状の治具で
加圧した状態で再硬化することにより、膜(層)厚も一
様な形で達成し得る。そして、前記半田コート層の平坦
面化に当たっては、接続用端子面を除くその隣接周辺部
面に、被着形成する半田コート層を見込んだ厚さのレジ
スト層を設けておくことにより、比較的厚さでかつ均一
な厚さの平坦面化した半田コート層を形成・具備させ得
るし、またマザーボード面への半田付け・実装時におけ
る半田流出などを大幅に解消ないし抑制できる。なお、
ここで半田コート層の厚さを、周辺部に設けたレジスト
層よりやや高めに(レジスト層面より突出させた形)す
ることも可能で、この場合検査治具などに装着し易くな
る。The flattening of the solder coat layer formed on the connecting terminal surface is performed, for example, by once melting and curing the printed / adhered solder, and then again from the solidus temperature to the liquidus temperature. A film (layer) is obtained by heating and softening, or by re-curing under a pressure between flat plate (surface) jigs at a temperature between the solidus temperature and the liquidus temperature, under pressure. The thickness can also be achieved in a uniform manner. Then, in flattening the solder coat layer, by providing a resist layer having a thickness that allows the solder coat layer to be formed on the adjacent peripheral surface except the connection terminal surface, relatively. It is possible to form and provide a flat and uniform solder coat layer having a uniform thickness, and it is possible to substantially eliminate or suppress solder outflow during soldering or mounting on the motherboard surface. In addition,
Here, the thickness of the solder coat layer can be made slightly higher than that of the resist layer provided in the peripheral portion (a shape protruding from the resist layer surface), and in this case, it can be easily mounted on an inspection jig or the like.
【0010】[0010]
【作用】上記リードレス面実装型ハイブリッドICの構
成においては、少なくとも裏面側に導出された接続用端
子面の半田コート層が平坦面化され、かつその厚さもほ
ぼ一様であるため、マザーボード面に面実装するとき、
互いに接続する面同士を高精度に、かつ確実に対接する
ことが可能となるので、信頼性の高い実装が達成され
る。また、リードレス面実装型ハイブリッドIC個々の
特性検査に当たっても、検査治具の接続端子との高精度
で確実な対接が可能なため、信頼性の高い特性検査を容
易に行い得ることになる。In the structure of the leadless surface mounting type hybrid IC described above, at least the solder coat layer on the connection terminal surface led out to the back surface is flattened and the thickness thereof is substantially uniform. When surface mounting to
Since the surfaces to be connected to each other can be brought into contact with each other with high accuracy and reliability, highly reliable mounting is achieved. Further, even in the characteristic inspection of each of the leadless surface mounting type hybrid ICs, highly reliable and reliable contact with the connection terminal of the inspection jig is possible, so that the characteristic inspection with high reliability can be easily performed. .
【0011】[0011]
【実施例】以下図1および図2を参照して本発明の実施
例を説明する。Embodiments of the present invention will be described below with reference to FIGS.
【0012】実施例1 図1は本発明に係るリードレス面実装型ハイブリッドI
Cの一構成例の要部を断面的に示したものである。図1
において、5はたとえば厚膜配線基板などの配線板、6
は前記配線板5の一主面に実装された所要の電子部品、
たとえば半導体素子,低抗体,コンデンサなどである。
また、7は前記配線板5の裏面側に導出された厚膜パタ
ーンから成る接続用端子(電極パッド)、8は前記接続
用端子(電極パッド)面面上に、たとえば63%Sn−37%
Pb半田(共晶半田)クリームを印刷・リフローで被覆・
配置した平坦面化した半田コート層である。Embodiment 1 FIG. 1 shows a leadless surface mount type hybrid I according to the present invention.
It is a cross-sectional view showing the main part of one structural example of C. Figure 1
5 is a wiring board such as a thick film wiring board, 6
Is a required electronic component mounted on one main surface of the wiring board 5,
For example, semiconductor devices, low antibodies, capacitors, etc.
Further, 7 is a connecting terminal (electrode pad) composed of a thick film pattern led out to the back surface side of the wiring board 5, and 8 is 63% Sn-37% on the surface of the connecting terminal (electrode pad).
Printing and reflow coating of Pb solder (eutectic solder) cream
It is the arranged solder coat layer having a flat surface.
【0013】このように構成されている本発明に係るリ
ードレス面実装型ハイブリッドICは、前記接続用端子
7面に被着形成された半田コート層8を平坦面化した以
外は、従来の構成と基本的に変わらないので、その製造
ないし組み立ても半田コート層8の平坦面化処理(工
程)を敢えて施す点を除けば、常套的な手段で成し得
る。 つまり、リードレス面実装型ハイブリッドICを
構成する配線板5の裏面側に導出された厚膜パターンか
ら成る接続用端子7面に、たとえば印刷法,浸漬法,メ
ッキ法などで付着・肉盛りした半田を、一旦溶融・硬化
した後、再度固相点温度まで熱して軟化してから、平板
(面)状の治具で加圧した状態で再硬化する手段を、リ
ードレス面実装型ハイブリッドICの常套的な製造(組
み立て)手段に、付加することにより、膜(層)厚も一
様で平坦面化した半田コート層8を接続用端子7面に備
えたリードレス面実装型ハイブリッドICが得られる。The leadless surface-mounting hybrid IC according to the present invention having the above-described structure has a conventional structure except that the solder coat layer 8 formed on the surface of the connecting terminal 7 is flattened. Since it is basically the same as the above, the manufacturing or assembling can be performed by a conventional means except that the flattening treatment (process) of the solder coat layer 8 is intentionally performed. That is, it is adhered and overlaid on the surface of the connecting terminal 7 composed of the thick film pattern led out to the back surface side of the wiring board 5 constituting the leadless surface mounting type hybrid IC by, for example, a printing method, a dipping method or a plating method. The leadless surface-mount hybrid IC is a means for re-hardening the solder once it has been melted and hardened, then heated again to the solidus temperature to soften it, and then pressed with a flat plate-shaped jig. In addition to the conventional manufacturing (assembling) means, a leadless surface-mounting hybrid IC having a solder coat layer 8 having a uniform film (layer) thickness and a flat surface on the connection terminal 7 surface is provided. can get.
【0014】より具体的には、セラミックス製の厚膜プ
リント配線板5の裏面側に導出させたピッチ間隔2.54mm
程度,直径 1.0mm程度の接続用端子7群の各接続用端子
7面に、メタルマスクを介して、前記共晶半田層を印刷
・被着した後、その半田層をリフロー,硬化させて整形
してから、再度共晶温度に加熱し状態で、平板状のセラ
ミックス板にて、前記各接続用端子7面上の半田層をほ
ぼ一様に加圧したところ、全半田層がほぼ一様な厚さを
呈し、かつ平坦面化したリードレス面実装型ハイブリッ
ドICが最終的に得られた。More specifically, a pitch interval of 2.54 mm led out to the back surface side of the thick film printed wiring board 5 made of ceramics.
The eutectic solder layer is printed / deposited on each connecting terminal 7 surface of the connecting terminal 7 group having a diameter of about 1.0 mm through a metal mask, and then the solder layer is reflowed and cured to be shaped. After that, while being heated to the eutectic temperature again, the solder layer on the surface of each of the connecting terminals 7 is pressed almost uniformly by the flat ceramic plate, and all the solder layers are almost even. A leadless surface-mounting hybrid IC having a uniform thickness and a flat surface was finally obtained.
【0015】さらに、上記において、厚膜プリント配線
板5の裏面側に導出させた接続用端子7領域を除くたの
領域面に、たとえばフォトレジストパターニングによっ
て、前記接続用端子7面上に被着・形成する半田コート
層8の厚さに対応した厚さのレジスト層9を選択的に設
けた他は、上記構成および製造手段に準じて、リードレ
ス面実装型ハイブリッドICを構成した。図2はこのリ
ードレス面実装型ハイブリッドICの要部構成を断面的
に示したもので、厚膜プリント配線板5の裏面側は、接
続用端子7領域を除いて他の配線10部を含む面が全面的
にレジスト層9で被覆され、かつ接続用端子7面に半田
コート層8がレジスト層9とほぼ同一平面を成して埋め
込まれた形態を採っている。そして、この構成において
は、予めパターニングされたレジスト層9によって、精
度よく位置決めされ、かつ容易に平坦化された半田コー
ト層8を形成することが可能である。つまり、前記接続
用端子7が比較的微小で、かつ狭ピッチで配置されてい
る場合でも、前記レジスト層9の側壁面が堰として機能
し、接続用端子7部を区画して露出するため、高精度に
また確実に所要の面が平坦化した半田コート層8を具備
し得ることになり、信頼性の高い電気的な接続・実装を
達成し得る。Further, in the above, the area surface other than the area of the connecting terminal 7 led out to the back surface side of the thick film printed wiring board 5 is adhered on the surface of the connecting terminal 7 by, for example, photoresist patterning. A leadless surface-mount hybrid IC was constructed according to the above configuration and manufacturing method except that the resist layer 9 having a thickness corresponding to the thickness of the solder coat layer 8 to be formed was selectively provided. FIG. 2 is a cross-sectional view showing the structure of a main part of this leadless surface-mount type hybrid IC. The back surface side of the thick film printed wiring board 5 includes 10 parts of other wiring except for the connection terminal 7 region. The entire surface is covered with the resist layer 9, and the solder coat layer 8 is embedded in the surface of the connecting terminal 7 so as to be substantially flush with the resist layer 9. Further, in this configuration, it is possible to form the solder coat layer 8 which is accurately positioned and easily flattened by the previously patterned resist layer 9. That is, even when the connection terminals 7 are relatively minute and arranged at a narrow pitch, the side wall surface of the resist layer 9 functions as a weir, and the connection terminal 7 portion is divided and exposed. The solder coat layer 8 having a required surface flattened with high accuracy and reliability can be provided, and highly reliable electrical connection / mounting can be achieved.
【0016】これらのリードレス面実装型ハイブリッド
ICを、所定の検査治具に装着して特性検査を行ったと
ころ、両者の互いに対応する接続部同士は、位置ズレな
ど起こさず容易にセットすることができ、また電気的な
接続も確実に確保することが可能で、煩雑さを要さずに
特性検査を行い得た。特に、前記において、半田コート
層8をレジスト層9面より若干突出させた構成とした場
合は、前記検査治具に装着・接触し易いので、特性検査
をより容易に行い得た。When these leadless surface-mounting hybrid ICs were mounted on a predetermined inspection jig and a characteristic inspection was performed, it was possible to easily set the corresponding connecting portions of the two without causing misalignment. In addition, the electrical connection can be surely ensured, and the characteristic inspection can be performed without any complexity. In particular, in the above case, when the solder coat layer 8 is configured to slightly project from the surface of the resist layer 9, it is easy to mount and contact with the inspection jig, so that the characteristic inspection can be performed more easily.
【0017】また、前記リードレス面実装型ハイブリッ
ドICを、所要のマザーボード面に実装して実装回路装
置を構成したところ、両者の互いに対応する接続部同士
は、位置ズレなど起こさず容易にセットすることができ
るとともに、電気的な接続も確実に確保することが可能
で、信頼性の高い実装回路装置として機能した。Further, when the leadless surface-mounting hybrid IC is mounted on a required mother board surface to form a mounting circuit device, the corresponding connecting portions of the both are easily set without causing a positional deviation or the like. In addition to being able to ensure the electrical connection, it functioned as a highly reliable mounted circuit device.
【0018】実施例2 実施例1の場合において、セラミックス製の厚膜プリン
ト配線板5の裏面側に導出させたピッチ間隔2.54mm程
度,直径 1.0mm程度の接続用端子7群の各接続用端子7
面に、メタルマスクを介して、たとえば45%Sn−55%Pb
半田、もしくは46%Sn− 8%Bi−46%Pb半田など、固相
線温度および液相線温度を有する半田層を印刷・被着し
た後、 200℃程度もしくは 165℃程度(いずれも固相線
温度と液相線温度との間)に加熱し,軟化させた状態
で、平板状のセラミックス板にて、前記接続用端子7群
の半田層をほぼ一様に加圧したところ、全半田層がほぼ
一様な厚さを呈し、かつ平坦面化したリードレス面実装
型ハイブリッドICを最終的に得た。ここで、各接続用
端子7面に印刷・被着した半田層の平坦面化に当たって
は、半田が適度な軟化状態を呈するため、隣接する接続
用端子7面の半田同士の流出による短絡、あるいは外観
不良など招来することもなく、良好な作業性および歩留
まりを示した。Embodiment 2 In the case of Embodiment 1, each connection terminal of the connection terminal 7 group having a pitch interval of about 2.54 mm and a diameter of about 1.0 mm led out to the back side of the thick film printed wiring board 5 made of ceramics. 7
Surface, through a metal mask, for example, 45% Sn-55% Pb
After printing and depositing a solder layer having a solidus temperature and a liquidus temperature, such as solder or 46% Sn-8% Bi-46% Pb solder, approximately 200 ° C or 165 ° C (both solid phase When the solder layer of the connecting terminals 7 group is pressed almost uniformly by a flat ceramic plate in a state of being heated to a temperature between the line temperature and the liquidus temperature and softened, all solder is Finally, a leadless surface-mount type hybrid IC in which the layers had a substantially uniform thickness and were flattened was obtained. Here, when the solder layer printed / deposited on each connection terminal 7 surface is flattened, the solder exhibits an appropriate softened state, so that a short circuit due to the outflow of solder from the adjacent connection terminal 7 surface, or Good workability and yield were exhibited without causing appearance defects.
【0019】また、前記実施例1の場合と同様に、所定
の検査治具に装着しての特性検査、およびマザーボード
面に実装して構成した実装回路装置の性能評価を、それ
ぞれ行ったところ、信頼性の高い特性検査を達成し得る
とともに、信頼性の高い機能を呈することが確認され
た。Further, as in the case of the first embodiment, the characteristic inspection by mounting on a predetermined inspection jig and the performance evaluation of the mounted circuit device mounted on the mother board surface were carried out. It was confirmed that a reliable characteristic test can be achieved and that a reliable function is exhibited.
【0020】さらに、前記固相線温度および液相線温度
を有する半田として、たとえば90%Sn−10%Pb半田、80
%Sn−20%Pb半田、70%Sn−30%Pb半田、55%Sn−45%
Pb半田、50%Sn−50%Pb半田、40%Sn−60%Pb半田、35
%Sn−65%Pb半田、30%Sn−70%Pb半田、25%Sn−75%
Pb半田などを用いても、同様な結果が認められた。Further, as the solder having the solidus temperature and the liquidus temperature, for example, 90% Sn-10% Pb solder, 80
% Sn-20% Pb solder, 70% Sn-30% Pb solder, 55% Sn-45%
Pb solder, 50% Sn-50% Pb solder, 40% Sn-60% Pb solder, 35
% Sn-65% Pb solder, 30% Sn-70% Pb solder, 25% Sn-75%
Similar results were observed using Pb solder.
【0021】さらに、前記実施例1の場合において、半
田コート層8を形成する半田として、共晶半田を用いる
代わりに、固相線温度および液相線温度を有する半田を
用いて、前記図2の図示と同様の構成を成すリードレス
面実装型ハイブリッドICを構成し、所定の検査治具に
装着しての特性検査、およびマザーボード面に実装して
構成した実装回路装置の性能評価を、それぞれ行ったと
ころ、信頼性の高い特性検査を達成し得るとともに、信
頼性の高い機能を呈することが確認された。Further, in the case of the first embodiment, instead of using the eutectic solder as the solder for forming the solder coat layer 8, solder having a solidus temperature and a liquidus temperature is used. Of a leadless surface-mounting hybrid IC having the same configuration as that shown in FIG. 1 and is mounted on a predetermined inspection jig to perform characteristic inspection, and performance evaluation of a mounted circuit device formed by mounting on a motherboard surface. As a result, it was confirmed that a highly reliable characteristic test could be achieved and that a highly reliable function was exhibited.
【0022】なお、上記では配線板5の裏面側にのみ接
続用端子7が導出した構成を例示したが、たとえば多層
的(多段的)に、前記リードレス面実装型ハイブリッド
ICを実装する場合など、実装電子部品群6側に導出し
た接続用端子面についても同様に、半田コート層を平坦
面化してもよい。In the above description, the connection terminal 7 is led out only on the back surface side of the wiring board 5. However, for example, when the leadless surface mounting type hybrid IC is mounted in a multi-layered (multi-stage) manner, etc. Similarly, the solder coat layer may be flattened on the connection terminal surface led out to the mounted electronic component group 6 side.
【0023】[0023]
【発明の効果】以上説明したように本発明のリードレス
面実装型ハイブリッドICは、少なくとも裏面側に導出
された接続用端子面の半田コート層が平坦面化され、か
つその厚さもほぼ一様であるため、マザーボード面に面
実装するとき、互いに接続する接続部同士を精度よく、
かつ確実に対接することが可能となるので、信頼性の高
い実装を達成し得る。また、リードレス面実装型ハイブ
リッドIC個々の特性検査においても、接続端子部同士
の確実な対接が可能なため、信頼性の高い特性検査を容
易に行い得ることになる。As described above, in the leadless surface mounting type hybrid IC of the present invention, at least the solder coat layer on the connection terminal surface led out to the back surface is flattened and the thickness thereof is also substantially uniform. Therefore, when surface-mounting on the motherboard surface, the connecting parts that connect to each other can be accurately
In addition, since it is possible to reliably contact each other, highly reliable mounting can be achieved. Further, in the characteristic inspection of each leadless surface-mounting hybrid IC, the connection terminal portions can be surely brought into contact with each other, so that the characteristic inspection with high reliability can be easily performed.
【図1】本発明に係るリードレス面実装型ハイブリッド
ICの一構成例の要部を示す断面図。FIG. 1 is a cross-sectional view showing a main part of a configuration example of a leadless surface-mounting hybrid IC according to the present invention.
【図2】本発明に係るリードレス面実装型ハイブリッド
ICの他の構成例の要部を示す断面図。FIG. 2 is a sectional view showing a main part of another configuration example of the leadless surface-mounting hybrid IC according to the present invention.
【図3】従来のリードレス面実装型ハイブリッドICの
構成要部を示す断面図。FIG. 3 is a cross-sectional view showing a main part of a conventional leadless surface mount hybrid IC.
1,5…配線板 2,6…実装電子部品群 3,7
…接続用端子 4,8…半田コート層 9…レジス
ト層1, 5 ... Wiring board 2, 6 ... Mounted electronic component group 3, 7
... Connection terminals 4, 8 ... Solder coat layer 9 ... Resist layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 坂本 和則 東京都品川区東品川四丁目3番1号 東芝 ライテック株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazunori Sakamoto 4-3-1, Higashishinagawa, Shinagawa-ku, Tokyo Inside Toshiba Lighting & Technology Corporation
Claims (4)
続用端子が導出されて成るリードレス面実装型ハイブリ
ッドICにおいて、 前記裏面側に導出された接続用端子面の半田コート層が
平坦面化されていることを特徴とするリードレス面実装
型ハイブリッドIC。1. A leadless surface-mounting hybrid IC in which at least a connection terminal solder-coated on the back surface side is led out, and a solder coat layer on the connection terminal surface led out on the back surface side is flattened. Leadless surface mount hybrid IC.
続用端子が導出されて成るリードレス面実装型ハイブリ
ッドICにおいて、 前記裏面側に導出された接続用端子面の半田コート層が
固相線温度および液相線温度を有する半田で形成され、
かつ平坦面化されていることを特徴とするリードレス面
実装型ハイブリッドIC。2. In a leadless surface-mounting hybrid IC in which at least a back surface side of a connection terminal solder-coated is led out, a solder coat layer of the connection terminal surface led out to the back surface side has a solidus temperature. And formed of solder having a liquidus temperature,
A leadless surface-mounting hybrid IC characterized by being flattened.
続用端子が導出されて成るリードレス面実装型ハイブリ
ッドICにおいて、 前記裏面側に導出された接続用端子面の周辺部にレジス
ト層が設けられ、かつ接続用端子面の半田コート層がレ
ジスト層に合わせ平坦面化されていることを特徴とする
リードレス面実装型ハイブリッドIC。3. A leadless surface mounting type hybrid IC in which at least a connection terminal solder-coated on the back surface side is led out, and a resist layer is provided in the peripheral portion of the connection terminal surface led out on the back surface side. A leadless surface-mount type hybrid IC, wherein the solder coat layer on the connection terminal surface is flattened to match the resist layer.
の平坦面化された半田コート層が隣接するレジスト層面
より突出していることをを特徴とするリードレス面実装
型ハイブリッドIC。4. The leadless surface-mounting hybrid IC according to claim 3, wherein the flattened solder coat layer of the connection terminal surface projects from the adjacent resist layer surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21412893A JPH06334064A (en) | 1993-03-24 | 1993-08-30 | Leadless surface mounting hybrid ic |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6500393 | 1993-03-24 | ||
JP5-65003 | 1993-03-24 | ||
JP21412893A JPH06334064A (en) | 1993-03-24 | 1993-08-30 | Leadless surface mounting hybrid ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06334064A true JPH06334064A (en) | 1994-12-02 |
Family
ID=26406144
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21412893A Withdrawn JPH06334064A (en) | 1993-03-24 | 1993-08-30 | Leadless surface mounting hybrid ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06334064A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0996322A3 (en) * | 1998-10-19 | 2002-01-02 | Alps Electric Co., Ltd. | Electronic circuit unit useful for portable telephones or the like, and a method of manufacturing the same |
JP2009514250A (en) * | 2005-11-01 | 2009-04-02 | アレグロ・マイクロシステムズ・インコーポレーテッド | Flip chip on lead semiconductor package method and apparatus |
-
1993
- 1993-08-30 JP JP21412893A patent/JPH06334064A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0996322A3 (en) * | 1998-10-19 | 2002-01-02 | Alps Electric Co., Ltd. | Electronic circuit unit useful for portable telephones or the like, and a method of manufacturing the same |
US6452112B1 (en) | 1998-10-19 | 2002-09-17 | Alps Electric Co., Ltd. | Electronic circuit unit useful for portable telephone, etc., and a method of manufacturing the same |
JP2009514250A (en) * | 2005-11-01 | 2009-04-02 | アレグロ・マイクロシステムズ・インコーポレーテッド | Flip chip on lead semiconductor package method and apparatus |
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