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JPH06327072A - Digital network synchronization system - Google Patents

Digital network synchronization system

Info

Publication number
JPH06327072A
JPH06327072A JP5115479A JP11547993A JPH06327072A JP H06327072 A JPH06327072 A JP H06327072A JP 5115479 A JP5115479 A JP 5115479A JP 11547993 A JP11547993 A JP 11547993A JP H06327072 A JPH06327072 A JP H06327072A
Authority
JP
Japan
Prior art keywords
phase
station
clock
oscillator
lower station
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5115479A
Other languages
Japanese (ja)
Inventor
Atsushi Imaoka
淳 今岡
Masami Kihara
雅巳 木原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP5115479A priority Critical patent/JPH06327072A/en
Publication of JPH06327072A publication Critical patent/JPH06327072A/en
Pending legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To take countermeasures by specifying the generation part of abnormality when abnormal phase change is generated. CONSTITUTION:A host station 1 is provided with a reference oscillator 3 for generating reference clocks, a transmitter 4 for transmitting signals to a subordinate station 2 in synchronism with the reference oscillator 3 and receiving the signals of the subordinate station, a phase comparing part 5 for detecting a phase difference between the clock components of the signals from the subordinate station and the reference clocks and an information transfer means 6 for transferring phase difference information to the subordinate station. The subordinate station is provided with a phase synchronizing oscillator 7 synchronized with the clock components of the signals of the host station, the transmitter 8 for performing transmission in synchronism with the phase synchronizing oscillator 7 and also performing reception from the host station, the phase comparing part 9 for detecting the phase difference between the clock components of the signals from the host station and phase synchronizing oscillator output and a control part 10 for receiving the phase difference information of the host station and the phase difference information from the phase comparing part of the subordinate station.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はディジタル通信網におい
て、地理的に離れて設置された装置間で同期を行うディ
ジタル網同期方式に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital network synchronization system for synchronizing devices installed geographically apart in a digital communication network.

【0002】[0002]

【従来の技術】ディジタル通信網では、情報信号の時分
割多重や分岐、挿入などの処理を効率的かつ経済的に行
うために、網内のすべての装置を共通の周波数で動作さ
せるディジタル同期方式が主流となっている。このディ
ジタル同期方式では、網内の基準となる発振器から出力
される基準クロック信号を各装置に分配し、各装置は分
配されたクロックに同期して動作するマスタースレーブ
網同期方式が多く採用されている。
2. Description of the Related Art In a digital communication network, a digital synchronization system in which all devices in the network operate at a common frequency in order to efficiently and economically perform processing such as time division multiplexing, branching, and insertion of information signals. Is the mainstream. In this digital synchronization system, a master-slave network synchronization system in which a reference clock signal output from an oscillator serving as a reference in a network is distributed to each device and each device operates in synchronization with the distributed clock is often adopted. There is.

【0003】従来から利用されているマスタースレーブ
同期方式の系構成の例を図3に示す。これは、地理的に
離れた装置間で基準クロックを分配し、網同期を実現す
る方式である。同図において、上位局101と下位局1
02は地理的に離れており、両局間は伝送装置103、
104を介してディジタル伝送路105で結ばれてい
る。
FIG. 3 shows an example of a system configuration of a master-slave synchronization system which has been conventionally used. This is a method of distributing a reference clock among geographically distant devices to realize network synchronization. In the figure, upper station 101 and lower station 1
02 is geographically separated, and the transmission device 103,
A digital transmission path 105 is connected via 104.

【0004】上位局の伝送装置は上位局の基準発振器1
06に同期して動作している。下位局の伝送装置104
では、上位局の伝送装置103から送信された信号のク
ロック成分(周波数成分)107を抽出する。抽出され
た周波数成分に位相同期発振器111を同期させれば、
上位局の基準発振器の周波数と下位局の位相同期発振器
の周波数が同期することになり、網同期が実現できる。
The transmitter of the upper station is the reference oscillator 1 of the upper station.
It is operating in synchronization with 06. Lower station transmission device 104
Then, the clock component (frequency component) 107 of the signal transmitted from the transmission device 103 of the higher station is extracted. If the phase-locked oscillator 111 is synchronized with the extracted frequency component,
Since the frequency of the reference oscillator of the upper station and the frequency of the phase locked oscillator of the lower station are synchronized, network synchronization can be realized.

【0005】[0005]

【発明が解決しようとする課題】CCITT勧告(G.
824)では、ディジタル網内のノードから出力される
信号の位相ゆらぎを規定している。この規定を満足する
ためには、ディジタル網内の基準クロックの位相変動量
を10μs以下に抑える必要がある。ところが、従来の
網同期方式では、図3に示したように、下位局で抽出し
た周波数成分を唯一の基準として同期を行うため、伝送
路や伝送装置で発生する異常な位相ゆらぎに追随して下
位局の位相同期発振器の位相がゆらいでしまうという好
ましくない問題があった。
[Problems to be Solved by the Invention] CCITT Recommendation (G.
824) specifies the phase fluctuation of the signal output from the node in the digital network. In order to satisfy this requirement, it is necessary to suppress the phase fluctuation amount of the reference clock in the digital network to 10 μs or less. However, in the conventional network synchronization method, as shown in FIG. 3, since the frequency component extracted by the lower station is used as the only reference for synchronization, it follows an abnormal phase fluctuation generated in the transmission line or the transmission device. There is an unfavorable problem that the phase of the phase locked oscillator of the lower station fluctuates.

【0006】すなわち、位相同期発振器では図3に示す
ように、位相比較部108において、伝送装置で抽出し
た周波数成分107と電圧制御発振器が発生するクロッ
ク112との位相差を検出し、位相差が零または一定値
になるよう電圧制御発振器の周波数を制御している。現
在のディジタル網では、電圧制御発振器には高安定な水
晶発振器やルビジウム原子発振器が用いられている。
That is, in the phase-locked oscillator, as shown in FIG. 3, the phase comparison unit 108 detects the phase difference between the frequency component 107 extracted by the transmission device and the clock 112 generated by the voltage-controlled oscillator, and the phase difference is detected. The frequency of the voltage controlled oscillator is controlled so that it becomes zero or a constant value. In current digital networks, highly stable crystal oscillators and rubidium atomic oscillators are used as voltage controlled oscillators.

【0007】これらの電圧制御発振器の周波数安定度は
非常に良いため、現在のディジタル網同期に用いられて
いる位相同期発振器では、1000秒程度の長い時定数
の制御ループが使われている。そのため、伝送路の障害
や伝送装置の故障などで位相の急激な変化が生じた場合
には、電圧制御発振器は位相変化にすぐには追随せず、
位相同期発振器の位相比較部では位相変化が検出され
る。
Since the frequency stability of these voltage-controlled oscillators is very good, the phase-locked oscillator currently used for digital network synchronization uses a control loop having a long time constant of about 1000 seconds. Therefore, when a sudden phase change occurs due to a failure in the transmission path or a failure in the transmission device, the voltage-controlled oscillator does not immediately follow the phase change,
A phase change is detected in the phase comparison section of the phase locked oscillator.

【0008】しかし、位相比較部での位相変化は、電圧
制御発振器の異常や位相同期発振器内の回路故障などで
も生じる。そのため、従来の方式では、位相比較部での
位相変化が、伝送路で発生した位相変化なのか、位相同
期ループ内の位相変化なのか判断することができなかっ
た。このため、従来の方式では、伝送された信号から抽
出した周波数成分に位相同期発振器を追随させるという
方法を採るしかなく、伝送路で急激な位相変化が最終的
に出力クロックの位相変動となり、網同期の精度が劣化
するという問題があった。
However, the phase change in the phase comparison section is caused by an abnormality in the voltage controlled oscillator or a circuit failure in the phase locked oscillator. Therefore, in the conventional method, it is impossible to determine whether the phase change in the phase comparison unit is the phase change generated in the transmission line or the phase change in the phase locked loop. Therefore, in the conventional method, there is no choice but to follow the method in which the phase-locked oscillator follows the frequency component extracted from the transmitted signal. There was a problem that the accuracy of synchronization deteriorates.

【0009】本発明は、このような従来の問題点を解決
するために成されたもので、異常な位相変化が発生した
際に異常箇所を特定することが可能で、これに基づいて
適切な対応措置を構ずることにより、高精度の位相同期
を維持することのできる同期方式を提供することを目的
としている。
The present invention has been made in order to solve such a conventional problem, and it is possible to identify an abnormal portion when an abnormal phase change occurs, and based on this, it is possible to identify an appropriate portion. It is an object of the present invention to provide a synchronization method capable of maintaining highly accurate phase synchronization by taking countermeasures.

【0010】[0010]

【課題を解決するための手段】本発明によれば上述の課
題は前記特許請求の範囲に記載した手段により解決され
る。
According to the present invention, the above-mentioned problems are solved by the means described in the claims.

【0011】すなわち、本発明は、上位局に設置された
基準発振器が発生する基準クロックを、1つ以上の下位
局に送信して、下位局を基準クロックに同期させるディ
ジタル網同期方式であって、上位局に、基準クロックを
発生する基準発振器と、基準クロックに同期して動作し
下位局に信号を送信し、かつ下位局からの信号を受信す
る伝送装置と、下位局から送信された信号のクロック成
分と上位局の基準クロックとの位相差を検出する位相比
較部と、位相比較部で検出した位相差情報を下位局に転
送する情報転送手段とを備える。
That is, the present invention is a digital network synchronization system for transmitting a reference clock generated by a reference oscillator installed in an upper station to one or more lower stations to synchronize the lower stations with the reference clock. , A reference oscillator that generates a reference clock to the upper station, a transmission device that operates in synchronization with the reference clock, transmits a signal to the lower station, and receives a signal from the lower station, and a signal transmitted from the lower station And a information transfer means for transferring the phase difference information detected by the phase comparison unit to the lower station.

【0012】又、下位局に上位局から送信された信号の
クロック成分に位相同期して発振する位相同期発振器
と、位相同期発振器に同期して動作し上位局に信号を送
信し、かつ上位局からの信号を受信する伝送装置と、上
位局から送信された信号のクロック成分と位相同期発振
器の出力の位相差を検出する位相比較部と、上位局の位
相比較部から上記情報転送手段で転送された位相差情報
と下位局の位相比較部からの位相差情報とを受ける制御
部とを備え、上記制御部は、伝送路などに異常が発生し
た場合、上位局の位相比較部からの位相差情報と下位局
の位相比較部からの位相差情報をもとに、異常の発生箇
所を特定する機能を備えて成るディジタル網同期方式で
ある。
Further, a phase-locked oscillator that oscillates in phase synchronization with the clock component of the signal transmitted from the upper station to the lower station, and operates in synchronization with the phase-locked oscillator to transmit a signal to the upper station and , A phase comparator for detecting the phase difference between the clock component of the signal transmitted from the upper station and the output of the phase-locked oscillator, and the information transfer means for transferring from the phase comparator of the higher station. The phase difference information from the phase comparison unit of the lower station, the control unit receives the phase difference information from the phase comparison unit of the higher station when an abnormality occurs in the transmission line. This is a digital network synchronization system that has a function of identifying the location of an abnormality based on the phase difference information and the phase difference information from the phase comparison unit of the lower station.

【0013】[0013]

【作用】本発明においては、上述のような構成を採って
いるので、下位局の制御部では、上位局の位相比較部と
下位局の位相比較部からの位相差情報とに基づいて下記
のように判断する。 位相差に急激な位相変動が生じた際、その位相変動
が、下位局の位相比較部で検出され、上位局の位相比較
部で検出されない場合には、上位局から下位局への伝送
路に異常が発生したと判断する。 上位局の位相比較部で検出され、下位局の位相比較部
で検出されない場合には、下位局から上位局への伝送路
に異常が発生したと判断する。 上位局の位相比較部と下位局の位相比較部で、符号が
同じで絶対値の等しい位相変動が検出されたときには、
下位局の位相同期発振器に異常が生じたと判断する。
In the present invention, since the above-mentioned configuration is adopted, the control unit of the lower station is based on the phase difference information from the phase comparison unit of the upper station and the phase comparison unit of the lower station, and To judge. When a sudden phase fluctuation occurs in the phase difference, if the phase fluctuation is detected by the phase comparison unit of the lower station and not detected by the phase comparison unit of the higher station, the transmission path from the higher station to the lower station is Judge that an abnormality has occurred. If it is detected by the phase comparison unit of the upper station and not detected by the phase comparison unit of the lower station, it is determined that an abnormality has occurred in the transmission path from the lower station to the higher station. When the phase comparison unit of the upper station and the phase comparison unit of the lower station detect phase fluctuations with the same sign and equal absolute values,
It is determined that an abnormality has occurred in the phase locked oscillator of the lower station.

【0014】このような判断に基づいて、下位局の制御
部は、異常の発生箇所を特定することができるから、異
常の発生箇所に応じた措置を講ずることにより位相同期
の精度劣化を防ぐことができる。
Based on such a judgment, the control unit of the subordinate station can identify the location where the abnormality has occurred. Therefore, by taking measures according to the location where the abnormality has occurred, it is possible to prevent the accuracy deterioration of the phase synchronization. You can

【0015】[0015]

【実施例】図1は本発明の一実施例の構成を示すブロッ
ク図である。ここでは、上位局と下位局がそれぞれ1つ
存在する場合について説明するが、1つの上位局に複数
の下位局が直接接続されている場合、あるいは、1つの
上位局から縦続接続でいくつかの下位局が接続されてい
る場合でも、直接接続されている2つの局を上位局と下
位局と見なして同様の構成で本発明を実施できる。
1 is a block diagram showing the configuration of an embodiment of the present invention. Here, the case where there is one upper station and one lower station will be described. However, when a plurality of lower stations are directly connected to one upper station, or when several upper stations are connected in cascade, Even when the lower station is connected, the two stations directly connected can be regarded as the upper station and the lower station, and the present invention can be implemented with the same configuration.

【0016】図1に示すように、上位局1には、伝送装
置4、基準発振器3、位相比較部5が設置される。下位
局2には、伝送装置8、位相同期発振器7、位相比較部
9、制御部10が設置される。上位局1と下位局2の伝
送装置4,8にはそれぞれ、発振器からのクロックを受
信するクロック受信部4b,8b、受信した伝送路信号
のクロックを抽出して外部に送出するクロック送出部4
a,8aとを備える。既存のFTM形多重中継装置やM
−20形同期端局装置はクロック受信部とクロック送出
部をすでに備えており、本発明の伝送装置としてそのま
ま利用することができる。
As shown in FIG. 1, the higher station 1 is provided with a transmission device 4, a reference oscillator 3, and a phase comparison unit 5. A transmission device 8, a phase-locked oscillator 7, a phase comparison unit 9, and a control unit 10 are installed in the lower station 2. The transmission devices 4 and 8 of the upper station 1 and the lower station 2 respectively include clock receivers 4b and 8b that receive a clock from an oscillator, and a clock transmitter 4 that extracts the clock of the received transmission path signal and sends it to the outside.
a, 8a. Existing FTM type multiple repeater and M
The -20 type synchronous terminal device is already provided with a clock receiving unit and a clock transmitting unit, and can be used as it is as a transmission device of the present invention.

【0017】伝送装置から出力される伝送路信号はクロ
ック受信部で受信したクロックに同期している。上位局
の伝送装置と下位局間の伝送装置との間は、対向する伝
送路で結ばれる。上位局から下位局へ送信される伝送路
を往路伝送路14、下位局から上位局へ送信される伝送
路を復路伝送路15とする。また、上位局から下位局へ
は位相差情報を転送する情報転送伝送路16が設置され
ている。上位局の位相比較部5で検出された位相差情報
13は上位局の情報転送装置6、情報転送伝送路16、
下位局の情報転送装置17を介して下位局の制御部10
に転送される。
The transmission path signal output from the transmission device is synchronized with the clock received by the clock receiving unit. The transmission device of the upper station and the transmission device of the lower station are connected by an opposite transmission path. A transmission path transmitted from the upper station to the lower station is called a forward transmission path 14, and a transmission path transmitted from the lower station to the upper station is called a return transmission path 15. An information transfer transmission line 16 for transferring the phase difference information is installed from the upper station to the lower station. The phase difference information 13 detected by the phase comparison unit 5 of the upper station is the information transfer device 6 of the upper station, the information transfer transmission line 16,
Control unit 10 of the lower station via information transfer device 17 of the lower station
Transferred to.

【0018】なお、本実施例では、上位局で検出された
位相差情報が独自の情報転送装置6と17を介して転送
される例を示したが、位相差情報を主信号に多重し、伝
送装置4,8と往路伝送路14を介して送信しても本発
明を実現できる。
In the present embodiment, the example in which the phase difference information detected by the upper station is transferred through the unique information transfer devices 6 and 17 has been shown. However, the phase difference information is multiplexed with the main signal, The present invention can be realized by transmitting data via the transmission devices 4 and 8 and the outward transmission line 14.

【0019】上位局の伝送装置4は、基準発振器3から
出力された基準クロック11に同期して動作する。よっ
て、伝送装置から出力され、往路伝送路を介して下位局
に伝送される伝送路信号は基準発振器3に同期してい
る。下位局の伝送装置では、往路伝送路の伝送路信号の
クロック成分18を抽出する。下位局の位相同期発振器
7は、抽出したクロック成分18に位相同期して発振し
ている。下位局の位相比較部9では、抽出したクロック
成分18の位相を基準にして位相同期発振器の出力クロ
ック20の位相変動を検出する。位相比較部9で検出さ
れた位相差情報19は制御部10に送られる。
The transmission device 4 of the higher station operates in synchronization with the reference clock 11 output from the reference oscillator 3. Therefore, the transmission path signal output from the transmission device and transmitted to the lower station via the outward transmission path is synchronized with the reference oscillator 3. The transmission device of the lower station extracts the clock component 18 of the transmission path signal of the forward transmission path. The phase-locked oscillator 7 of the lower station oscillates in synchronization with the extracted clock component 18. The phase comparison unit 9 of the lower station detects the phase fluctuation of the output clock 20 of the phase-locked oscillator based on the phase of the extracted clock component 18. The phase difference information 19 detected by the phase comparison unit 9 is sent to the control unit 10.

【0020】下位局の伝送装置8は、位相同期発振器の
出力クロック20に同期して動作する。下位局の伝送装
置からは伝送路信号が出力され、復路伝送路を介して上
位局に送信される。上位局の伝送装置では、復路伝送路
の伝送路信号のクロック成分12を抽出する。上位局の
位相比較部5では、基準クロック11の位相を基準にし
て抽出したクロック成分12の位相変動を測定する。位
相比較された結果の位相差情報13は、上位局の情報転
送装置6、情報転送伝送路16、下位局の情報転送装置
17を介して下位局の制御部10に転送される。
The transmission device 8 of the lower station operates in synchronization with the output clock 20 of the phase locked oscillator. A transmission path signal is output from the transmission device of the lower station and transmitted to the upper station via the return transmission path. The transmission device of the upper station extracts the clock component 12 of the transmission path signal of the return transmission path. The phase comparison unit 5 of the upper station measures the phase fluctuation of the clock component 12 extracted with the phase of the reference clock 11 as a reference. The phase difference information 13 as a result of the phase comparison is transferred to the control unit 10 of the lower station via the information transfer device 6 of the upper station, the information transfer transmission line 16, and the information transfer device 17 of the lower station.

【0021】以下各状態別の実施例の動作および各信号
の位相関係などについて説明する。 平常時の動作 まず、すべての装置が正常に動作しており、伝送路にも
障害がない状態を考える。この状態では、伝送路に加わ
る位相ゆらぎは、温度などの環境変化による伝送路遅延
時間の変動のみである。このとき、下位局で抽出したク
ロック成分18は、上位局の基準クロックの位相に往路
伝送路の遅延変動を加えた位相に同期している。往路伝
送路の遅延変動は、位相同期発振器の制御ループの時定
数よりも、さらに長い周期成分を持つ位相変動であるた
め、位相制御発振器の出力20は往路伝送路の遅延変動
を正確に追随することになる。従って、下位局の位相比
較部9で検出される、抽出したクロック成分18と位相
同期発振器の出力20の位相差には変動が現れない。
The operation of the embodiment for each state and the phase relationship of each signal will be described below. Normal operation First, let us consider a situation in which all devices are operating normally and there is no failure in the transmission path. In this state, the phase fluctuation applied to the transmission line is only the fluctuation of the transmission line delay time due to environmental changes such as temperature. At this time, the clock component 18 extracted by the lower station is synchronized with the phase of the reference clock of the upper station plus the delay variation of the forward transmission path. Since the delay fluctuation of the forward transmission path is a phase fluctuation having a longer period component than the time constant of the control loop of the phase locked oscillator, the output 20 of the phase control oscillator accurately follows the delay fluctuation of the forward transmission path. It will be. Therefore, no fluctuation appears in the phase difference between the extracted clock component 18 and the output 20 of the phase-locked oscillator, which is detected by the phase comparator 9 of the lower station.

【0022】一方、下位局の伝送装置は、位相制御発振
器に同期して動作するため、上位局で復路伝送路の伝送
路信号から抽出したクロック成分12は、基準発振器と
比較して、往路伝送路の遅延変動と復路伝送路の遅延変
動の和の分だけ位相変動する。よって、上位局の位相比
較部5では、往路伝送路の遅延変動と復路伝送路の遅延
変動の和の位相変動が検出される。
On the other hand, since the transmission device of the lower station operates in synchronization with the phase control oscillator, the clock component 12 extracted from the transmission line signal of the return transmission line in the upper station is transmitted in the forward transmission as compared with the reference oscillator. The phase varies by the sum of the delay variation of the path and the delay variation of the return transmission path. Therefore, the phase comparison unit 5 of the upper station detects the phase fluctuation of the sum of the delay fluctuation of the forward transmission path and the delay fluctuation of the return transmission path.

【0023】環境変化による伝送路の遅延変動は、伝送
路周囲の温度変動が主な原因であり、遅延変動の大きさ
は伝送路長と温度変動量に比例することがわかってい
る。伝送路長は既知の量であり、温度変動は季節から知
ることができ、最大でも数10℃である。ゆえに、上位
局の位相比較部5で検出される位相変動量が、伝送路長
と温度変動量から計算して妥当な値であり、かつ、下位
局の位相比較部9で位相変動が検出されないならば、ク
ロック分配動作は正常であり、下位局の位相同期発振器
は上位局の基準発振器に正確に同期していると判断でき
る。
It is known that the delay variation of the transmission line due to the environmental change is mainly due to the temperature variation around the transmission line, and the magnitude of the delay variation is proportional to the transmission line length and the temperature variation amount. The transmission path length is a known quantity, and the temperature fluctuation can be known from the season, which is several tens of degrees Celsius at the maximum. Therefore, the phase fluctuation amount detected by the phase comparison unit 5 of the upper station is a proper value calculated from the transmission path length and the temperature fluctuation amount, and the phase fluctuation is not detected by the phase comparison unit 9 of the lower station. If so, it can be determined that the clock distribution operation is normal and the phase-locked oscillator of the lower station is accurately synchronized with the reference oscillator of the upper station.

【0024】往路クロックパスに異常が生じた場合の
動作 つぎに、伝送路または伝送装置に異常が生じ、下位局の
位相同期発振器が追随できないような急激な位相変動が
生じた場合を考える。ここでは、正常動作のときに説明
した伝送路の温度変化による遅延変動よりは、ずっと大
きな位相変動を対象とする。
Operation when Abnormality Occurs in Outgoing Clock Path Next, let us consider a case where an abnormality occurs in the transmission path or the transmission device, causing a sudden phase fluctuation that cannot be followed by the phase-locked oscillator of the lower station. Here, the phase variation that is much larger than the delay variation due to the temperature change of the transmission line described in the normal operation is targeted.

【0025】ここで、上位局の伝送装置のクロック受信
部4b、往路伝送路14、下位局の伝送装置のクロック
送出部8aを一括して往路クロックパスと呼ぶ。同様
に、下位局の伝送装置のクロック受信部8b、復路伝送
路15、上位局の伝送装置のクロック送出部4aを一括
して復路クロックパスと呼ぶ。
Here, the clock receiving unit 4b of the transmission device of the upper station, the outward transmission line 14, and the clock transmission unit 8a of the transmission device of the lower station are collectively referred to as an outward clock path. Similarly, the clock receiving unit 8b of the transmission device of the lower station, the return transmission line 15, and the clock transmission unit 4a of the transmission device of the higher station are collectively referred to as a return clock path.

【0026】いま、往路クロックパスにのみ急激でかつ
大きな位相変動が生じた瞬間に検出される位相変動を考
える。下位局の位相同期発振器7は急激な位相変動には
すぐには追随しないため、下位局の位相比較部9では、
往路クロックパスの位相変動がそのまま検出される。一
方、上位局の位相比較部5では、位相変動は検出されな
い。この状態を放置しておくと、位相同期発振器7が往
路クロックパスの異常な位相変動に追随してしまい、ク
ロックの同期精度が劣化してしまう。そこで、往路クロ
ックパスの異常な位相変動が検出されると制御部10で
判断し、位相同期発振器の制御ループを切り、自走状態
にさせる。この操作により、往路クロックパスに異常な
位相変動が生じた際にも、同期精度の劣化を最小限にす
ることができる。
Now, let us consider the phase fluctuation detected at the moment when a sharp and large phase fluctuation occurs only in the forward clock path. Since the phase-locked oscillator 7 of the lower station does not immediately follow a sudden phase change, the phase comparator 9 of the lower station
The phase fluctuation of the forward clock path is detected as it is. On the other hand, the phase variation of the upper station is not detected by the phase comparison unit 5. If this state is left as it is, the phase-locked oscillator 7 follows an abnormal phase fluctuation in the forward clock path, and the clock synchronization accuracy deteriorates. Therefore, the control unit 10 determines that an abnormal phase fluctuation in the forward clock path is detected, and the control loop of the phase-locked oscillator is cut off to bring the phase-locked oscillator into a free-running state. By this operation, even if an abnormal phase variation occurs in the forward clock path, the deterioration of the synchronization accuracy can be minimized.

【0027】復路クロックパスに異常が生じた場合の
動作 また、復路クロックパスにのみ急峻でかつ大きな位相変
動が生じた場合を考える。このとき、上位局の位相比較
部5では復路クロックパスの位相変動が検出され、下位
局の位相比較部9では位相変動は検出されないので、往
路クロックパスの位相変動と明らかに区別できる。この
場合は、往路クロックパスは正常であり、下位局の位相
同期発振器7も正常に上位局の基準発振器3に同期して
いるので、下位局の制御部は特に動作をする必要がな
い。
Operation when Abnormality Occurs in Return Path Clock Path Also, consider a case where a steep and large phase variation occurs only in the return path clock path. At this time, since the phase comparison unit 5 of the higher station detects the phase fluctuation of the return clock path and the phase comparison unit 9 of the lower station does not detect the phase fluctuation, it can be clearly distinguished from the phase fluctuation of the forward clock path. In this case, the forward clock path is normal, and the phase-locked oscillator 7 of the lower station is also normally synchronized with the reference oscillator 3 of the upper station, so that the control unit of the lower station does not need to operate in particular.

【0028】下位局の位相同期発振器に異常が生じた
場合の動作 さらに、下位局の位相同期発振器7の内部に異常が生じ
た場合を考える。この異常により、位相同期発振器の出
力位相に急激な位相変動が生じたとする。このとき、往
路クロックパスは正常であるから、下位局の位相比較部
9では、位相同期発振器で生じた異常な位相変動が検出
できる。また、位相同期発振器の位相変動は復路クロッ
クパスを介して上位局に伝えられる。
Operation When Abnormality Occurs in the Phase-Locked Oscillator of the Lower Station Further, consider the case where an abnormality occurs in the phase-locked oscillator 7 of the lower station. It is assumed that this abnormality causes a sudden phase change in the output phase of the phase locked oscillator. At this time, since the forward clock path is normal, the phase comparator 9 of the lower station can detect an abnormal phase fluctuation caused in the phase locked oscillator. Further, the phase fluctuation of the phase locked oscillator is transmitted to the upper station via the return clock path.

【0029】よって、上位局の位相比較部5でも、位相
同期発振器の位相変動が検出できる。この状態は、前述
した往路クロックパスに位相変動が生じた場合や往路ク
ロックパスに位相変動が生じた場合と明確に区別でき
る。下位局の制御部で位相同期発振器の異常を検出した
場合には、予備の位相同期発振器に切り変えるなどの措
置をとる。
Therefore, the phase comparison section 5 of the upper station can detect the phase fluctuation of the phase locked oscillator. This state can be clearly distinguished from the case where the phase change occurs in the forward path clock path and the case where the phase change occurs in the forward path clock path. When the control unit of the subordinate station detects an abnormality in the phase-locked oscillator, it takes measures such as switching to a spare phase-locked oscillator.

【0030】各信号の位相関係の説明 図2は、上位局の基準クロック11、下位局の位相同期
発振器の出力クロック20、上位局、下位局で抽出され
る伝送路クロック12,18の位相を、横軸を時間とし
て表したものである。同図において、t1 ,t2
3 ,t4 をそれぞれ、上位局の基準クロック11の位
相、下位局で抽出される伝送路クロック18の位相、下
位局の位相同期発振器出力20の位相、上位局で抽出さ
れる伝送路クロック12の位相とする。
Description of the phase relationship of each signal FIG. 2 shows the phases of the reference clock 11 of the upper station, the output clock 20 of the phase locked oscillator of the lower station, and the transmission path clocks 12 and 18 extracted by the upper station and the lower station. , The horizontal axis is time. In the figure, t 1 , t 2 ,
t 3 and t 4 are respectively the phase of the reference clock 11 of the upper station, the phase of the transmission path clock 18 extracted by the lower station, the phase of the phase-locked oscillator output 20 of the lower station, and the transmission path clock extracted by the upper station. 12 phases.

【0031】このとき、往路クロックパスの遅延時間t
out は、 tout =t2 −t1 であり、復路クロックパスの遅延時間tinは、 tin=t4 −t3 である。また、上位局の位相比較部で検出される位相差
φM は、 φM =t4 −t1 であり、下位局の位相比較部で検出される位相差φ
S は、 φS =t3 −t2 である。
At this time, the delay time t of the forward clock path
out is a t out = t 2 -t 1, delay time t in the backward clock path is a t in = t 4 -t 3. Further, the phase difference φ M detected by the phase comparison unit of the higher station is φ M = t 4 −t 1 , and the phase difference φ detected by the phase comparison unit of the lower station is φ M.
S is φ S = t 3 −t 2 .

【0032】すなわち、上位局の位相比較部では、上位
局の基準クロックの位相を基準にして上位局で抽出され
る伝送路クロックの位相を測定している。また、下位局
の位相比較部では、下位局で抽出した伝送路クロックの
位相を基準にして、下位局の位相同期発振器の位相を測
定している。
That is, the phase comparison unit of the upper station measures the phase of the transmission path clock extracted by the upper station with reference to the phase of the reference clock of the upper station. Further, the phase comparison unit of the lower station measures the phase of the phase locked oscillator of the lower station with reference to the phase of the transmission path clock extracted by the lower station.

【0033】ここで、往路クロックパスに急峻な位相変
動が生じて遅延時間がΔtout だけ大きくなったとき、
3 はすぐには追随しないので、φS はΔtout だけ小
さくなり、φM は変化しない。
Here, when a steep phase variation occurs in the forward clock path and the delay time increases by Δt out ,
Since t 3 does not follow immediately, φ S becomes smaller by Δt out , and φ M does not change.

【0034】また、復路クロックパスに急峻な位相変動
が生じて遅延時間がΔtinだけ大きくなったとき、変化
するのはt4 だけなので、φS は変化せず、φM はΔt
inだけ大きくなる。
When a steep phase change occurs in the return clock path and the delay time increases by Δt in, only t 4 changes, so φ S does not change and φ M does not change Δt in.
in only increases.

【0035】さらに、下位局の位相同期発振器に異常が
生じて、位相同期発振器の出力位相がΔtp だけ遅れた
とき、tout とtinに変化がないとすれば、φS ,φM
共にΔtp だけ大きくなる。すなわち、下位局の位相同
期発振器に異常が生じたときは、φS ,φM 共に同じ符
号の等しい量の位相変化をする。
[0035] In addition, the abnormality occurs in the phase-locked oscillator of lower station, when the output phase of the phase-locked oscillator is delayed by Δt p, if there is no change in the t out and t in, φ S, φ M
Both increase by Δt p . That is, when an abnormality occurs in the phase locked oscillator of the lower station, both φ S and φ M undergo the same amount of phase change of the same sign.

【0036】そして、往路クロックパスと復路クロック
パスの遅延時間が同時にΔtc だけ共に急激に大きくな
ったときを考える。このようなことは、伝送路障害など
のときに、往路伝送路と復路伝送路が共に別の伝送路に
切替った時に起こる。このとき、t2 とt4 が共にΔt
c だけ遅れ、t3 はすぐには追随しないので、φs はΔ
c だけ小さくなり、φM はΔtc だけ大きくなる。す
なわち、この場合は、φS とφM とで逆符号の絶対値の
等しい量の位相変化をするので、下位局の位相同期発振
器に異常が生じた場合とは明確に区別がつく。
Now, let us consider a case where the delay time of the forward clock path and the delay time of the backward clock path both suddenly increase by Δt c . Such a thing occurs when both the forward transmission path and the return transmission path are switched to different transmission paths due to a failure of the transmission path. At this time, t 2 and t 4 are both Δt
Since c is delayed and t 3 does not follow immediately, φ s is Δ
It decreases by t c and φ M increases by Δt c . That is, in this case, since φ S and φ M change the phase by the same amount of absolute values of opposite signs, it can be clearly distinguished from the case where an abnormality occurs in the phase locked oscillator of the lower station.

【0037】往路クロックパスの遅延時間と復路クロッ
クパスの遅延時間に、符号が反対で絶対値の等しい量の
位相変化が生じた時は、下位局の位相同期発振器の異常
と区別がつかない。しかし、クロックパスにこのような
変化(対向する伝送路間で符号が反対で絶対値の等しい
量の位相変化)が生じる確率は非常に低いと考えられる
ので、φs とφM とで、同じ符号の等しい量の位相変化
を検出した場合は、下位局の位相同期発振器の異常とみ
なして差し支えない。
When the delay time of the forward clock path and the delay time of the backward clock path have phase changes of opposite signs and the same absolute value, it is indistinguishable from the abnormality of the phase locked oscillator of the lower station. However, the probability that such a change (phase change of opposite sign and equal absolute value between the opposite transmission lines) will occur in the clock path is very low, so φ s and φ M are the same. When the phase change of the same sign is detected, it may be considered as an abnormality of the phase locked oscillator of the lower station.

【0038】制御部の判断、動作 表1は、上位局、下位局の位相比較部5と9で、位相変
化が生じた場合、制御部でどのような判断をするかをま
とめたものである。下位局の制御部10は表1のような
判断機能を持っており、2つの位相比較部5と9からの
位相差情報を照らし合わせ、クロック分配系のどこに異
常が生じたかを判断することができる。また、制御部1
0は、判断したクロック分配系の異常発生箇所に対し
て、位相同期発振器の自走、切替など、最適な保護動作
をとることができる。
Judgment and Operation of Control Unit Table 1 summarizes what judgment is made by the control unit when phase changes occur in the phase comparison units 5 and 9 of the upper station and the lower station. . The control unit 10 of the subordinate station has a determination function as shown in Table 1, and can compare the phase difference information from the two phase comparison units 5 and 9 to determine where an abnormality has occurred in the clock distribution system. it can. In addition, the control unit 1
With 0, it is possible to take an optimum protection operation such as free-running or switching of the phase-locked oscillator with respect to the determined abnormality occurrence part of the clock distribution system.

【0039】[0039]

【表1】 [Table 1]

【0040】[0040]

【発明の効果】以上説明したように、本発明のディジタ
ル網同期方式によれば、上位局と下位局に設置された位
相比較部で位相差を検出することにより、異常な位相変
動が生じた際に、その原因箇所を特定することができる
から、これに対する相応の措置を行うことができる。そ
の結果、伝送路や位相同期発振器に障害が生じた際でも
位相同期精度の劣化を小さく抑えることができる利点が
ある。
As described above, according to the digital network synchronization system of the present invention, an abnormal phase variation occurs due to the phase difference being detected by the phase comparators installed in the upper station and the lower station. At this time, the cause can be identified, and appropriate measures can be taken. As a result, there is an advantage that deterioration of the phase synchronization accuracy can be suppressed to a small level even when a failure occurs in the transmission line or the phase locked oscillator.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の構成を示すブロック図であ
る。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

【図2】本発明における各信号の位相関係を説明する図
である。である。
FIG. 2 is a diagram illustrating a phase relationship of each signal in the present invention. Is.

【図3】従来のマスタースレーブ同期方式の系構成の例
を示す図である。
FIG. 3 is a diagram showing an example of a system configuration of a conventional master-slave synchronization system.

【符号の説明】[Explanation of symbols]

1,101 上位局 2,102 下位局 4,8,103,104 伝送装置 105 ディジタル伝送路 3,106 基準発振器 12,18,107 伝送路信号のクロック成分 108 位相同期発振器内の位相比較部 109 フィルタ 110 電圧制御発振器 7,111 位相同期発振器 20,112 位相同期発振器の出力クロック 5,9 位相比較部 10 制御部 4b,8b クロック受信部 4a,8a クロック送出部 14 往路伝送路 15 復路伝送路 16 情報転送伝送路 11 基準クロック 13,19 位相差情報 6,17 情報転送装置 1, 101 Upper station 2, 102 Lower station 4, 8, 103, 104 Transmission device 105 Digital transmission line 3, 106 Reference oscillator 12, 18, 107 Clock component of transmission line signal 108 Phase comparison unit in phase-locked oscillator 109 Filter 110 voltage controlled oscillator 7,111 phase-locked oscillator 20,112 output clock of phase-locked oscillator 5,9 phase comparator 10 controller 4b, 8b clock receiver 4a, 8a clock transmitter 14 forward transmission path 15 return transmission path 16 information Transfer transmission line 11 Reference clock 13,19 Phase difference information 6,17 Information transfer device

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 上位局に設置された基準発振器が発生す
る基準クロックを、少なくとも1つの下位局に送信し
て、下位局を基準クロックに同期させるディジタル網同
期方式において、 上位局(1)は、基準クロックを発生する基準発振器
(3)と、基準クロックに同期して動作し下位局に信号
を送信し、かつ下位局から送信された信号を受信する伝
送装置(4)と、下位局から送信された信号のクロック
成分と上位局の基準クロックとの位相差を検出する位相
比較部(5)と、位相比較部で検出した位相差情報を下
位局に転送する情報転送手段とを備え、 下位局(2)は、上位局から送信された信号のクロック
成分に位相同期して発振する位相同期発振器(7)と、
位相同期発振器に同期して動作し上位局に信号を送信
し、かつ上位局からの信号を受信する伝送装置(8)
と、上位局から送信された信号のクロック成分と位相同
期発振器の出力の位相差を検出する位相比較部(9)
と、上位局の位相比較部(5)から上記情報転送手段で
転送された位相差情報と下位局の位相比較部(9)から
の位相差情報とを受ける制御部(10)とを備え、 制御部(10)は、伝送路などに異常が発生した場合、
上位局の位相比較部(5)からの位相差情報と下位局の
位相比較部(9)からの位相差情報をもとに、異常の発
生箇所を特定する機能を有することを特徴とするディジ
タル網同期方式。
1. A digital network synchronization system for transmitting a reference clock generated by a reference oscillator installed in an upper station to at least one lower station to synchronize the lower station with the reference clock, wherein the upper station (1) is A reference oscillator (3) that generates a reference clock, a transmission device (4) that operates in synchronization with the reference clock, transmits a signal to a lower station, and receives a signal transmitted from the lower station; A phase comparison section (5) for detecting a phase difference between the clock component of the transmitted signal and the reference clock of the higher station, and an information transfer means for transferring the phase difference information detected by the phase comparison section to the lower station, The lower station (2) includes a phase-locked oscillator (7) that oscillates in phase with the clock component of the signal transmitted from the upper station,
Transmission device (8) which operates in synchronization with a phase-locked oscillator and transmits a signal to a higher station and receives a signal from the higher station
And a phase comparison unit (9) for detecting the phase difference between the clock component of the signal transmitted from the host station and the output of the phase-locked oscillator.
And a control unit (10) for receiving the phase difference information transferred from the phase comparison unit (5) of the higher station by the information transfer means and the phase difference information from the phase comparison unit (9) of the lower station, The control unit (10), when an abnormality occurs in the transmission line,
A digital feature having a function of identifying an abnormal place based on the phase difference information from the phase comparing unit (5) of the upper station and the phase difference information from the phase comparing unit (9) of the lower station. Network synchronization method.
JP5115479A 1993-05-18 1993-05-18 Digital network synchronization system Pending JPH06327072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5115479A JPH06327072A (en) 1993-05-18 1993-05-18 Digital network synchronization system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5115479A JPH06327072A (en) 1993-05-18 1993-05-18 Digital network synchronization system

Publications (1)

Publication Number Publication Date
JPH06327072A true JPH06327072A (en) 1994-11-25

Family

ID=14663547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5115479A Pending JPH06327072A (en) 1993-05-18 1993-05-18 Digital network synchronization system

Country Status (1)

Country Link
JP (1) JPH06327072A (en)

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US7227918B2 (en) 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
JP2014127888A (en) * 2012-12-27 2014-07-07 Hitachi Ltd Synchronous ethernet device

Cited By (7)

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WO1998045973A1 (en) * 1997-04-08 1998-10-15 Power X Limited Closed-loop synchronisation arrangement for data transmission system
US6608829B1 (en) 1997-04-08 2003-08-19 Xyratex Technology Limited Closed-loop synchronization arrangement for data transmission system
US7227918B2 (en) 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7333570B2 (en) 2000-03-14 2008-02-19 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7684532B2 (en) 2000-03-14 2010-03-23 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
JP2010172014A (en) * 2000-03-14 2010-08-05 Altera Corp Clock data recovery circuitry associated with programmable logic device circuitry
JP2014127888A (en) * 2012-12-27 2014-07-07 Hitachi Ltd Synchronous ethernet device

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