JPH0629364A - Semiconductor device and testing method therefor - Google Patents

Abstract

PURPOSE:To provide a semiconductor device wherein defective insulation between wiring layers is detectable by a simple test and also provide a method for such a test. CONSTITUTION:This semiconductor device is provided with a group of at least n (n is multiple of 2, including 0) bit lines BL0-BL7) and a test circuit 32 for judging whether the group of the bit lines is normal or not. The test circuit 32 is provided with an impression circuit 34 for impressing 9V voltage to the nth bit lines (BL0, BL2, BL4, BL6) and an impression circuit 36 for impressing 0V to the (n+1)th bit lines. 9V and 0V are simultaneously impressed to the nth bit lines and the (n+1)th bit lines, respectively, and maintained for a specified time. In the device and test method above, potential difference is provided between the bit lines each, and further maintained for a specified time. This accelerated electrical stress, and makes it possible to detect dust stuck between the bit lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a test method thereof, and more particularly to a semiconductor device capable of detecting a column defect and the like by a simple test and a simple test method thereof.

[0002]

2. Description of the Related Art With the miniaturization of devices, the space between metal wiring layers is becoming narrower. Then, the insulating property between the metal wiring layers, which has not been a problem in the past, becomes a problem. For example, if dust such as silicon debris adheres between the metal wiring layers during or after the manufacturing process, there is a possibility that the above-mentioned insulating property may be deteriorated. A particular problem is that this deterioration in insulation occurs over time, that is, during actual use. Especially EPROM, EE
In non-volatile memories such as PROMs and batch erasable EEPROMs, when programming cells between metal wiring layers, 6-10V
A relatively high voltage is applied. In a normal test, a cell program test is performed before shipment, but it is often performed at most several times. Therefore, during the actual use in which the test passes in that range but the writing may be repeated more than 100 times, for example, TDDB (Time Dependent: Time Depende
There is a risk that the insulation will deteriorate due to the mechanism such as nt Dielectric Breakdown).

In the case of the EEPROM, the program test may be performed a large number of times, but the stress may not be effectively applied between all the wiring layers depending on the type of the pattern to be programmed. Further, even if the EEPROM is performed many times, the method of performing the program test of the guaranteed number of times over all the chips is time-consuming and is not normally performed.

If dust or the like adheres to a wiring layer lower than a metal wiring layer such as a bit line, for example, a word line or the like, the cell may not function and a defective portion may be easily detected. It is possible to identify and screen defective chips. However, even if dust or the like adheres to the wiring layer that is the uppermost layer of the chip, it may pass in a normal test.

[0005]

The above-described deterioration of the insulation property due to the adhesion of dust or the like between the metal wiring layers can be improved to some extent by repeating the cell program test before shipment. Is possible. But,
Repeating the write test is unrealistic because the test time becomes huge and is not always the worst condition.

The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device capable of detecting insulation failure between wiring layers by a simple test, and a simple test method therefor. It is in.

[0007]

A semiconductor device according to the present invention comprises a wiring layer group parallel to each other and a test means for testing whether or not the wiring layer group is normal. Then, the test means is an n-th (n
Is a multiple of 2 including 0) and a first potential applying means for applying a first potential to a wiring layer, and a second potential different from at least the first potential in the (n + 1) th wiring layer of the wiring layer group. A second potential applying means for applying a potential, wherein the first potential is applied to the n-th wiring layer and the second potential is simultaneously applied to the (n + 1) -th wiring layer, and this state is kept for a predetermined time. It is characterized in that it is configured to hold.

Further, in the test method, the first potential is applied to the n-th wiring layer of the wiring layer group, and the first potential is applied to the (n + 1) th wiring layer of the wiring layer group. A second electric potential different from the electric potential is applied simultaneously, and this state is maintained for a predetermined time.

[0009]

In the semiconductor device as described above, the first potential is applied to the nth wiring layer of the wiring layer group, and at least the first potential is applied to the (n + 1) th wiring layer of the wiring layer group. Second potential applying means for applying a second potential different from the first potential, and the first potential is applied to the n-th wiring layer.
The test circuit is configured to simultaneously apply the second potential to the first potential and the (n + 1) th wiring layer and maintain this state for a predetermined time. Therefore, at the time of the test, a potential difference, that is, an electrical stress can be applied to all of the n wiring layers. Moreover,
Since this state is maintained for a predetermined time, electrical stress is accelerated and applied between wiring layers. The place where electrical damage is caused by such a test is a place where dust such as silicon dust is attached across wiring layers. Therefore, the semiconductor device according to the present invention can detect a defective mode caused by dust such as silicon debris attached across wiring layers. If such a defective mode can be detected, it becomes possible to screen a semiconductor device that causes latent defects such as the above dust adhesion and the like, and a semiconductor device having high reliability can be provided. become.

Further, in the test method, the first potential is applied to the nth wiring layer of the wiring layer group, and the first potential is applied to the (n + 1) th wiring layer of the wiring layer group. It is simple since it is sufficient to simultaneously apply the second electric potentials different from the electric potentials and hold this state for a predetermined time.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings.

Large-capacity EPR according to one embodiment of the present invention
The OM will be described. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view taken along line 2-2 in FIG.

As shown in FIGS. 1 and 2, N-type source regions 12 _{1 to} 12 ₂ and N-type drain region 14 are formed in a P-type silicon substrate 10, respectively. A floating gate made of polysilicon or the like is provided on the substrate 10 between the N-type source regions 12 _{1 to} 12 ₂ and the N-type drain region 14 via a gate insulating film 16 made of a silicon oxide film or the like. -To 1
8 ₀ to 18 ₃ are formed. Floating gate 18 ₀ ~ 1
8 on ₃ via the insulating film 20 made of a silicon oxide film, polysilicon or polysilicon and silicide and the control gate made of a laminated film layer, etc., - bets (word - also called word lines) WL ₀ ~ WL ₃ is formed. An interlayer insulating film 22 made of a silicon oxide film or the like is formed on the substrate 10 so as to cover the control gates WL ₀ to WL ₃ and the like. Contact holes 24 _{0 to} 24 ₇ reaching the drain region 14 are formed in the interlayer insulating film 22. Interlayer insulating film 22
The upper, through one of the contact holes 24 _{0 -} 24 _7, the bit lines BL ₀ to BL ₇ which is electrically connected to the drain region 14 are formed. Bit line BL ₀ ~
BL ₇ is usually made of an aluminum alloy and is also called a metal wiring layer. The bit lines BL _{0 to} BL ₇ are formed in a direction orthogonal to the word lines WL _{0 to} WL ₃ in a plane.

When data is programmed in the EPROM having the above structure, for example, a high voltage of 12.5 V is applied to the control gate and a high voltage of 9 V is applied to the drain region. As a result, channel hot electrons are generated. The data is programmed by injecting the channel hot electrons into the floating gate.

In programming such data, for example, the bit line adjacent to the selected bit to which 9V is applied is 0V. Therefore, a voltage of 9V is generated between the selected bit line and the adjacent bit line. Here, as shown in FIG. 5, a conductive material such as silicon scrap is provided between the selected bit line BL ₀ to which 9V is applied and the unselected bit line BL ₁ to which 0V is applied. It is assumed that dust 26 is attached. Then, due to electrical stress, a leak current 30 is generated through the insulating film 28.
Occurs. This may occur in one data program, or may occur over time by a mechanism such as TDDB. In particular, the latter is the majority. Figure 4
Shows the case where the dust 26 is simply attached to the insulating film 28. However, when the dust 26 is embedded in the insulating film 28, or before the deposition of the insulating film 28, the bit line B
If dust 26 adheres between L ₀ and the bit line BL ₁ ,
It facilitates the generation of the leak current 30 and further facilitates electrical breakdown. In the present invention, a test circuit 32 as shown in FIG. 1 is built in in order to screen a chip which may cause the above defective mode.

The test circuit 32 includes an nth bit line potential applying circuit 3 for supplying a predetermined potential to the nth bit line.
4 and an n first bit line potential applying circuit 36 for supplying a predetermined potential to the (n + 1) th bit line. The above n represents an integer represented by a multiple of 2, including 0. Further, the above n indicates a subscript added for convenience of explanation of the present invention, and has no particular relation to a signal in the memory circuit such as an address signal.

The nth bit line potential application circuit 34 is electrically connected to the bit lines BL ₀ , BL ₂ , BL ₄ and BL ₆ , and these bit lines BL ₀ , BL ₂ , BL ₄ and B are provided.
A predetermined potential, for example, 0 V to 9 V is switched to and applied to L ₆ . Further, n + 1-th bit line potential applying circuit 36 is electrically connected to the bit line BL _1, BL _3, BL ₅ and BL _7, the bit lines BL _1, BL _3, BL ₅ and a predetermined potential to BL _7, For example, the voltage is switched from 0V to 9V and applied. In this embodiment, the case where there are eight bit lines is shown, but if the bit lines are connected to the circuits 34 and 36 which can switch and apply different potentials every other bit line, the bit lines are actually connected. It doesn't matter how many Next, the operation of the test circuit will be described.

First, the n-th bit line potential applying circuit 34 is turned on to set the bit lines BL ₀ , BL ₂ , BL ₄ and BL.
A potential of 9V is applied to ₆ . At this time, the (n + 1) th bit line potential application circuit 36 is turned off or applied with a potential of 0V to generate a potential difference of 9V between the bit lines and apply an electrical stress of 9V between the bit lines. . This state is shown in FIG. FIG. 4 described above is a sectional view showing the vicinity of the dust 26 shown in FIG. 3 in an enlarged manner. The state where an electrical stress of 9V is applied to each bit line shown in FIG. 3 is maintained for a predetermined time. Then, it is possible to detect, in a short time, a defective mode due to the adhesion of dust 26 or the like, which has been found only by destruction due to the accumulation of electrical stress. The time for holding the state shown in FIG. 3 is, for example, the time during which the bit line is electrically stressed during data programming and destruction over time via the dust 26 or the like, for example, TDDB or the like. Calculate based on the mechanism and set to the time obtained by this calculation or a time close to it. Further, these operations are executed by a command from a control unit (not shown), for example.

As shown in FIGS. 3 and 4, when dust 26 such as silicon dust is attached on the memory cell array, an insulating film 28, for example, is formed by electrical stress after a lapse of a predetermined time. The insulation of the trash is destroyed and the garbage 2
The bit line BL ₀ and the bit line BL ₁ are short-circuited via 6,
A leak current 30 flows. A defective column can be detected by detecting this leak current 30.

With such a method, the dust 26 and the like can be attached in a shorter time than the method of repeating the write test in which a potential is applied to each bit line many times to accumulate electrical stress. It is possible to find a defective mode caused by the failure.

Further, in a non-volatile memory represented by an EPROM as a cell, there is a defective mode in which electrons escape from the floating gate to the drain, and a circuit for testing this, a so-called drain stress test circuit, is built in. There are many cases. In this drain stress test circuit, after programming the data in most of the cells, a voltage of, for example, 9 V is applied to all the bit lines all at once, and in this state it is checked whether electrons escape from the floating gate. Is. Therefore, a modification such as changing the connection of the transistor is added to the drain stress test circuit, and the bit line 1 as shown in FIG.
Circuits 34 and 36 are formed so that different potentials can be switched and applied for each book. In this way, first, for example, the nth bit line circuit potential applying circuit 34 is turned on, and n + 1
The third bit line circuit potential application circuit 36 is turned off, each bit line is electrically stressed for a predetermined time, and the above-described test is performed (hereinafter referred to as a bit line stress test).
After that, the n-th bit line circuit potential application circuit 34 and the (n + 1) th bit line circuit potential application circuit 36 are both turned on, and a potential of 9 V, for example, is applied to all the bit lines to perform a drain stress test.

Thus, if the test circuit 32 according to the present invention is provided with the drain stress test function, it is possible to obtain the advantage that not only the bit line stress test but also the drain stress test can be tested at the same time.

Further, in a large capacity memory, if a bit line has a defect, a redundant circuit (column redundancy circuit) that can replace the column is mounted. Therefore, if the defective portion is revealed in advance, there is a possibility that the defective portion can be relieved during the test. Therefore, it is desirable to perform a bit line stress test once before starting a normal test, for example, a drain stress test.

In this way, the place (column) where the short circuit between the bit lines has occurred can be repaired in the redundancy process. As a matter of course, even a portion which has become defective in the drain stress test is relieved in this redundancy process. After the redundancy process, a drain stress test and a bit line stress test are performed again to check whether the redundancy column is normal.

Further, according to the test method of the present invention, if there is a defective portion at one place and electrical breakdown occurs, the bit lines are short-circuited and the stress voltage is lowered. For example, if it is assumed that there is a defective part at some place, it is possible that after the weakest part is destroyed, other defective parts cannot be identified. Therefore, the memory cell array may be divided into predetermined blocks, and the bit line stress test may be performed for each block. Blocks can be divided into a predetermined number of columns, or one column can be divided into a plurality of columns, that is,
A method of combining a predetermined number of word lines or a predetermined number of columns and a predetermined number of word lines may be used.

Further, in the above-described embodiment, two kinds of potentials are applied to every other bit line to obtain a state in which each bit line is electrically stressed. However, if this state is maintained. For example, there are 3 types of potentials, 4 types ...
It may be divided into a large number.

It is also preferable to check whether a defect has occurred in the final stage after enclosing the package. According to the check at the final stage,
Defective chips due to dust attached in the assembly process and the package encapsulation process can be eliminated.

The present invention is not limited to the above-described embodiment, but various modifications can be made without departing from the scope of the invention. For example, although the present invention has been described by taking the EPROM as an example in the above-mentioned one embodiment, other nonvolatile memories such as the EEPROM and the batch erasing type EEPROM as well as the dynamic type memory having the high density wiring such as the bit line and the static type. It goes without saying that it can be applied to other memories such as a memory. Further, in the above-mentioned one embodiment, the short circuit failure mode in the bit line made of aluminum alloy has been described. Occur. Therefore, the present invention can be applied to a semiconductor device in which a wiring layer made of a conductive material such as silicide exists at a high density. Further, the wiring layer may have a multi-layer structure.

[0029]

As described above, according to the present invention, it is possible to provide a semiconductor memory device capable of detecting insulation failure between wiring layers by a simple test, and a simple test method therefor.

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along line 2-2 in FIG.

FIG. 3 is a diagram showing a stress application state of a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view showing an enlarged main part in FIG.

[Explanation of symbols]

10 ... P-type silicon substrate, 12 _1, 12 ₂ ... N-type source - source region, 14 ... N-type drain region, 16 ... gate - gate insulating film,
18 _{0-18 3} ... floating gate - DOO, 20 ... insulating film, 22 ... interlayer insulation film, 24 _{0 -} 24 ₇ ... contact hole 26 ... dust, 28 ... insulating film, 30 ... Li - leakage current, BL ₀ ~ BL ₇
... bit lines, WL ₀ ~WL ₇ ... word - word line.

Claims (6)

[Claims] 1. A wiring layer group parallel to each other, and a test means for testing whether or not the wiring layer group is normal, wherein the test means is the n-th wiring layer group (n is 0).
A multiple of 2) including a first potential applied to a first wiring layer
Potential applying means and second potential applying means for applying at least a second potential different from the first potential to the (n + 1) th wiring layer of the wiring layer group, the nth wiring layer The semiconductor device is configured to simultaneously apply the first potential and the second potential to the (n + 1) th wiring layer and maintain this state for a predetermined time. 2. The second potential applying means, in addition to applying the second potential, further has a function of applying the first potential to an (n + 1) th wiring layer of the wiring layer group. The test means applies the first potential to the n-th wiring layer and the second potential to the (n + 1) -th wiring layer at the same time, and holds this state for a predetermined time. And a second mode for simultaneously applying the potential of the first potential to the wiring layer group and maintaining this state for a predetermined time. The semiconductor device according to claim 1. 3. The bit line group according to claim 1, wherein the at least n wiring layer group is a bit line group.
The semiconductor device according to any one of claims. 4. A method of testing a semiconductor device having wiring layer groups parallel to each other, wherein a first potential and the wiring are applied to an n-th wiring layer (n is a multiple of 2 including 0) of the wiring layer groups. A method for testing a semiconductor device, comprising: simultaneously applying a second potential different from the first potential to the (n + 1) th wiring layer of the layer group and maintaining this state for a predetermined time. 5. A method of testing a semiconductor device comprising wiring layer groups parallel to each other, wherein a first potential and the wiring are applied to an n-th (n is a multiple of 2 including 0) wiring layer of the wiring layer group. A first mode for simultaneously applying a second potential different from the first potential to the (n + 1) th wiring layer of the layer group and maintaining this state for a predetermined time, and the wiring layer group simultaneously. And a second mode for applying the first potential and maintaining this state for a predetermined time. 6. The test method for a semiconductor device according to claim 4, wherein the test method is performed after enclosing the package.