JPH0629314A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH0629314A JPH0629314A JP18067192A JP18067192A JPH0629314A JP H0629314 A JPH0629314 A JP H0629314A JP 18067192 A JP18067192 A JP 18067192A JP 18067192 A JP18067192 A JP 18067192A JP H0629314 A JPH0629314 A JP H0629314A
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- Prior art keywords
- semiconductor device
- insulating film
- electrode
- manufacturing
- nitrogen
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- Electrodes Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置及びその製
造方法に係り、特に半導体基板とゲート酸化膜との間の
界面特性の向上した半導体装置及びその製造方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having improved interface characteristics between a semiconductor substrate and a gate oxide film and a method of manufacturing the same.
【0002】[0002]
【従来の技術】半導体装置を構成する主要な素子の一つ
にMOSトランジスタがある。このトランジスタの半導
体基板とゲート絶縁膜との間の界面には界面準位が存在
し、これがしきい値電圧を変動させたり、表面反転層内
のキャリアの移動度を低下させたり、また接合のリーク
電流を増加させる要因となっていた。この界面準位を低
減させる方法としては、界面準位の物理的実体であるダ
ングリングボンドをフッ素原子により終端する方法等が
知られている。この方法は、例えば、アイ イーイー
イー トランスアクション オン エレクトロン デバ
イス、第36巻、第879〜887頁(1989)(IE
EE. Transactions on Electron Device,vol 36,No
5,pp879-887(1989))に記載されている。2. Description of the Related Art A MOS transistor is one of the main elements constituting a semiconductor device. There is an interface state at the interface between the semiconductor substrate of this transistor and the gate insulating film, which changes the threshold voltage, reduces the mobility of carriers in the surface inversion layer, and It was a factor that increased the leak current. As a method of reducing the interface state, a method of terminating a dangling bond, which is a physical substance of the interface state, with a fluorine atom is known. This method is, for example,
E-Transaction on Electron Device, Vol. 36, pp. 879-887 (1989) (IE
EE. Transactions on Electron Device, vol 36, No
5, pp879-887 (1989)).
【0003】他方、基板と酸化膜の界面に窒素を導入す
る技術としては、N2Oガスを用いた窒化技術がある。
この技術は、例えば、固体素子と材料コンファレンスの
予稿集、第159〜162頁(1990)(Extended
Abstracts of the 22ndConference on Solid Sta
te Devices and Materials,pp159−162(1990))
に記載されている。しかし、窒素導入により界面準位を
低減したという報告は無い。On the other hand, as a technique for introducing nitrogen into the interface between the substrate and the oxide film, there is a nitriding technique using N 2 O gas.
This technique is described, for example, in Proceedings of Solid State Devices and Materials Conference, pp. 159-162 (1990) (Extended
Abstracts of the 22ndConference on Solid Sta
te Devices and Materials, pp159-162 (1990))
It is described in. However, there is no report that the interface state is reduced by introducing nitrogen.
【0004】[0004]
【発明が解決しようとする課題】LSIの高集積化を図
るためには、トランジスタのゲート絶縁膜を薄くするこ
とにより単位面積当りの容量を増加させる必要がある。
ところが、上記従来技術のように、フッ素による界面準
位低減法を用いると、ゲート絶縁膜の容量低下が起こ
り、MOSトランジスタの設計が難しくなるという問題
があった。また、フッ素の導入量が多い場合には逆に界
面準位が増加するために、最適範囲が狭いという問題が
あった。In order to achieve high integration of the LSI, it is necessary to increase the capacitance per unit area by thinning the gate insulating film of the transistor.
However, when the interface state reduction method using fluorine is used as in the above-mentioned conventional technique, there is a problem that the capacitance of the gate insulating film is reduced and the design of the MOS transistor becomes difficult. Further, when the amount of fluorine introduced is large, the interface state increases conversely, so that there is a problem that the optimum range is narrow.
【0005】本発明の目的は、絶縁膜の容量を低下させ
ることなく、かつ制御性よく界面準位を低減した半導体
装置及びその製造方法を提供することにある。An object of the present invention is to provide a semiconductor device in which the interface state is reduced with good controllability and without reducing the capacitance of the insulating film, and a method for manufacturing the same.
【0006】[0006]
【課題を解決するための手段】本発明の半導体装置は、
半導体基板と、その上に形成された絶縁膜と、その上に
形成された電極とからなり、半導体基板及び上記電極の
少なくとも一方並びに絶縁膜に窒素原子が導入された領
域を有するものである。また、絶縁膜、半導体基板と絶
縁膜の界面、絶縁膜と電極の界面には窒素原子と共にフ
ッ素原子が存在していてもよい。The semiconductor device of the present invention comprises:
A semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the semiconductor substrate, and at least one of the semiconductor substrate and the electrode and a region in which nitrogen atoms are introduced into the insulating film. Further, fluorine atoms may be present together with nitrogen atoms at the insulating film, the interface between the semiconductor substrate and the insulating film, and the interface between the insulating film and the electrode.
【0007】これらの原子は、半導体基板の深さ方向に
濃度分布のピークを持つように導入されることが多い。
窒素原子の濃度分布のピークが半導体基板にあるとき
は、そのピーク濃度が1×1018cm~3以上、1×10
21cm~3以下であることが好ましい。また、絶縁膜中に
フッ素原子がなく、窒素原子のみがあり、その濃度分布
のピークが絶縁膜にあるときは、そのピーク濃度は、1
×1018cm~3以上1×1022cm~3以下であることが
好ましい。絶縁膜は2nmから20nmの薄い膜が用い
られることが多いので、ピーク濃度と窒素原子の濃度は
ほぼ同じである。絶縁膜中に窒素原子と共にフッ素原子
が存在し、その濃度分布のピークが絶縁膜にあるとき
は、窒素原子及びフッ素原子の濃度は、いずれも1×1
018cm~3以上1×1021cm~3以下であることが好ま
しい。[0007] These atoms are often introduced so as to have a concentration distribution peak in the depth direction of the semiconductor substrate.
When the peak of the concentration distribution of nitrogen atoms is present in the semiconductor substrate, the peak concentration is 1 × 10 18 cm 3 or more, 1 × 10
It is preferably 21 cm to 3 or less. When there are no fluorine atoms in the insulating film but only nitrogen atoms and the peak of the concentration distribution is in the insulating film, the peak concentration is 1
It is preferably × 10 18 cm 3 or more and 1 × 10 22 cm 3 or less. Since a thin film having a thickness of 2 nm to 20 nm is often used as the insulating film, the peak concentration and the concentration of nitrogen atoms are almost the same. When fluorine atoms are present together with nitrogen atoms in the insulating film and the concentration distribution peaks in the insulating film, the concentrations of nitrogen atoms and fluorine atoms are both 1 × 1.
It is preferably 0 18 cm 3 or more and 1 × 10 21 cm 3 or less.
【0008】このような半導体装置は、半導体基板上に
絶縁膜を形成し、絶縁膜上に電極を形成し、電極に窒素
原子を導入するか、電極を通して絶縁膜又は半導体基板
に窒素原子を導入して製造することができる。窒素原子
と共にフッ素原子が存在するときは、フッ素原子も同様
に電極を通して絶縁膜に導入することができる。In such a semiconductor device, an insulating film is formed on a semiconductor substrate, an electrode is formed on the insulating film, and nitrogen atoms are introduced into the electrode, or nitrogen atoms are introduced into the insulating film or the semiconductor substrate through the electrode. Can be manufactured. When a fluorine atom is present together with a nitrogen atom, the fluorine atom can be similarly introduced into the insulating film through the electrode.
【0009】これらの導入は、イオン打ち込みにより行
なうことが好ましい。またこの際、例えば、窒素イオン
の平均投影飛程を絶縁膜中に設定すれば、窒素イオンの
多くは絶縁膜中に存在する。このイオン打ち込みの後
に、絶縁膜を熱処理することによりこれらの原子を絶縁
膜以外の部分に移動させることもできる。このような方
法により、窒素原子やフッ素原子を半導体装置の所望の
部分に存在せしめることができる。It is preferable to introduce these by ion implantation. At this time, for example, if the average projected range of nitrogen ions is set in the insulating film, most of the nitrogen ions are present in the insulating film. It is also possible to move these atoms to a portion other than the insulating film by heat treating the insulating film after the ion implantation. By such a method, nitrogen atoms and fluorine atoms can be made to exist in desired portions of the semiconductor device.
【0010】[0010]
【作用】本発明の半導体装置において界面準位が減少す
ることは、原子状の窒素が半導体基板とゲート絶縁膜界
面のダングリングボンドを終端した結果と考えられるが
その機構については解明できていない。The reduction of the interface state in the semiconductor device of the present invention is considered to be a result of atomic nitrogen terminating the dangling bond at the interface between the semiconductor substrate and the gate insulating film, but its mechanism has not been clarified. .
【0011】[0011]
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。 実施例1 図1〜図5を用いて、第1の実施例を説明する。図1は
本発明の実施例を示すMOSキャパシタの断面模式図で
ある。同図に示すように、通常の製造プロセスを用い
て、面方位(100)である比抵抗10Ω・cmのn型
シリコン基板101上に素子分離酸化膜102を選択的
に形成した後、温度850℃、水蒸気雰囲気中で膜厚8
nmのゲート酸化膜103となるシリコン酸化膜を形成
する(図1(a))。その後、同ゲート酸化膜103上
に、形成後の膜厚が100nmになるようにリン(P)
をドーピングしながらシリコン膜104を形成する。こ
の時、形成温度は525℃、P濃度は1×1020cm~3
である。その後、打ち込みエネルギー45keVで窒素
イオン打ち込みを行なう。打ち込まれた窒素の多くはゲ
ート酸化膜中に存在する。打ち込み量は、1×1013〜
1×1016cm~2の範囲で変化させた。その後、100
%窒素雰囲気中で900℃、30分間の熱処理を行なう
ことにより、イオン打ち込み損傷の回復と、シリコン膜
104内のPの活性化を図る(図1(b))。なお、こ
のアニール後の窒素原子は、電極中、酸化膜中及び基板
中に存在し、このときの窒素原子濃度ピークは酸化膜中
にあり、ピーク濃度は1×1018〜1×1022cm~3で
ある。Embodiments of the present invention will now be described in detail with reference to the drawings. Example 1 A first example will be described with reference to FIGS. FIG. 1 is a schematic sectional view of a MOS capacitor showing an embodiment of the present invention. As shown in the figure, after the element isolation oxide film 102 is selectively formed on the n-type silicon substrate 101 having a plane resistance (100) and a specific resistance of 10 Ω · cm using a normal manufacturing process, the temperature is set to 850. 8 ° C in steam atmosphere
A silicon oxide film to be the gate oxide film 103 having a thickness of 10 nm is formed (FIG. 1A). Then, phosphorus (P) is formed on the gate oxide film 103 so that the film thickness after formation is 100 nm.
A silicon film 104 is formed while doping. At this time, the formation temperature is 525 ° C., and the P concentration is 1 × 10 20 cm to 3
Is. After that, nitrogen ion implantation is performed with an implantation energy of 45 keV. Most of the implanted nitrogen is present in the gate oxide film. The driving amount is 1 × 10 13 ~
It was changed within the range of 1 × 10 16 cm 2 Then 100
By performing heat treatment at 900 ° C. for 30 minutes in a% nitrogen atmosphere, ion implantation damage is recovered and P in the silicon film 104 is activated (FIG. 1B). The nitrogen atoms after this annealing are present in the electrode, the oxide film and the substrate, and the nitrogen atom concentration peak at this time is in the oxide film, and the peak concentration is 1 × 10 18 to 1 × 10 22 cm 2. ~ 3 .
【0012】このシリコン膜104上にレジスト106
を塗布してパターンニングした後、このレジスト106
をマスクにしてシリコン膜104をパターンニングする
(図1(c))。その後、レジスト106を除去して、
上記シリコン膜をゲート電極107とする(図1
(d))。最後に、100%水素雰囲気中で、450℃
30分の熱処理を行なう。以下、通常通り保護膜、配線
等を形成し、半導体装置を完成する。A resist 106 is formed on the silicon film 104.
After applying and patterning, the resist 106
Is used as a mask to pattern the silicon film 104 (FIG. 1C). After that, the resist 106 is removed,
The silicon film is used as the gate electrode 107 (FIG. 1
(D)). Finally, in a 100% hydrogen atmosphere, 450 ℃
Heat treatment for 30 minutes. Thereafter, a protective film, wiring, etc. are formed as usual to complete a semiconductor device.
【0013】このようにして作成したMOSキャパシタ
の容量−電圧測定を行ない、その結果から界面準位密度
を計算した。窒素打ち込み量とミッドギャップでの界面
準位密度の関係を図2に示す。窒素打ち込み量の増加と
ともに、界面準位密度が減少していることが分かる。こ
れは、打ち込まれた窒素原子が、ゲート酸化膜とシリコ
ン基板界面のダングリングボンドを終端しているためで
あると考える。また、本実施例においては、フッ素の場
合に見られる導入量の増加に伴う界面準位の増加は見ら
れず、プロセス制御性に優れていることが分かる。The capacitance-voltage of the MOS capacitor thus produced was measured, and the interface state density was calculated from the result. FIG. 2 shows the relationship between the nitrogen implantation amount and the interface state density in the midgap. It can be seen that the interface state density decreases as the nitrogen implantation amount increases. It is considered that this is because the implanted nitrogen atoms terminate the dangling bonds at the interface between the gate oxide film and the silicon substrate. In addition, in this example, no increase in the interface level with the increase in the amount of introduction, which is seen in the case of fluorine, is seen, and it is understood that the process controllability is excellent.
【0014】さらに、打ち込み量と酸化膜容量の変化と
の関係を図3に示す。ここでは、比較のために、上記試
料作成方法に記載した窒素イオン打ち込みに代えて、従
来のフッ素イオン打ち込みを行なった試料の結果(図中
従来法と記す)も合わせて示す。同図より、窒素打ち込
みの場合には、打ち込み量が増加しても酸化膜容量は殆
ど低下しないことが分かる。この時の酸化膜厚の変化を
図4に示す。同図より本発明においては、酸化膜厚は殆
ど増加しないことが分かる。また、同ゲート酸化膜10
3に流れる電流密度が1μA/cm2のときの電界強度
(臨界電界強度)を用いて、窒素イオン打ち込み後のゲ
ート酸化膜絶縁性について検討した結果を図5に示す。
これによると、1×1016cm~2の窒素イオン打ち込み
量においては、ゲート酸化膜の絶縁性が向上することが
分かる。Further, FIG. 3 shows the relationship between the implantation amount and the change in oxide film capacitance. Here, for comparison, the results of a sample in which a conventional fluorine ion implantation is performed instead of the nitrogen ion implantation described in the above-mentioned sample preparation method (also referred to as a conventional method in the figure) are also shown. From the figure, it is understood that in the case of nitrogen implantation, the oxide film capacitance hardly decreases even if the implantation amount increases. The change in oxide film thickness at this time is shown in FIG. From the figure, it can be seen that the oxide film thickness hardly increases in the present invention. In addition, the gate oxide film 10
FIG. 5 shows the result of examining the gate oxide film insulating property after implantation of nitrogen ions by using the electric field strength (critical electric field strength) when the current density flowing in 3 is 1 μA / cm 2 .
According to this, in the 1 × 10 16 cm ~ nitrogen ion implantation amount of 2, it can be seen that insulating gate oxide film is improved.
【0015】なお、本実施例においては、イオン打ち込
み後の熱処理を900℃で行なったが、600℃以上1
200℃以下で行なった場合にも、同様の効果が得られ
た。600℃未満の場合には、シリコン膜104が結晶
化しないために導電性が得られず、MOSキャパシタと
して機能しなかった。また、1200℃を越えると、ゲ
ート絶縁膜に劣化が生じるため好ましくない。また、同
様の実験をp型シリコン基板を用いて行なった場合も、
本実施例と全く同様の効果が得られた。さらに、同様の
実験を基板面方位が(110)、(111)である基板
を用いて行なった場合にも、本実施例と全く同様の効果
が得られた。また、面方位が(100)、(110)又
は(111)からの傾斜角度が10°以内であるシリコ
ン基板をそれぞれ用いた場合にも、本実施例と全く同様
の効果が得られた。In this embodiment, the heat treatment after ion implantation was performed at 900 ° C., but 600 ° C. or higher 1
The same effect was obtained when performed at 200 ° C. or lower. When the temperature was lower than 600 ° C., the silicon film 104 was not crystallized, so that conductivity was not obtained and the silicon capacitor did not function as a MOS capacitor. Further, if the temperature exceeds 1200 ° C., the gate insulating film is deteriorated, which is not preferable. Also, when a similar experiment is performed using a p-type silicon substrate,
The same effect as that of this example was obtained. Furthermore, when the same experiment was performed using substrates having substrate plane orientations of (110) and (111), the same effect as that of this example was obtained. In addition, even when the silicon substrates having the plane orientations of (100), (110) or (111) and the inclination angles of 10 ° or less were used, the same effect as that of this example was obtained.
【0016】実施例2 図1、図6を用いて、第2の実施例を説明する。実施例
1と同様のプロセスにより、(100)面方位であるP
型シリコン基板101上に素子分離酸化膜102を選択
的に形成した後、温度850℃、100%O2雰囲気中
で膜厚8nmのゲート酸化膜103となるシリコン酸化
膜を形成する(図1(a))。次に同ゲート酸化膜上に
形成後の膜厚が100nmになるようにリン(P)をド
ーピングしながら電極となるシリコン膜104を形成し
た。この時、P濃度は1×1020cm~3である。その
後、打ち込みエネルギー25keVで窒素イオン105
のイオン打ち込みを行なった。このとき、打ち込まれた
イオンの多くは電極中に存在する。打込み量は、各々1
×1014〜1×1016cm~2である。その後、100%
窒素雰囲気中で900℃、30分間の熱処理を行なうこ
とにより、イオン打ち込み損傷の回復と、シリコン膜1
04のPの活性化を図った(図1(b))。なお、この
アニール後の窒素原子は、電極中及び酸化膜中に主に存
在し、このときの窒素原子濃度ピークは電極中及び酸化
膜中にあり、ピーク濃度は1×1018〜1×1022cm
~3である。このシリコン膜104上にレジスト106を
塗布してパターンニングした後、このレジスト106を
マスクにしてシリコン膜104をパターンニングする
(図1(c))。その後、レジスト106を除去して、
上記シリコン膜をゲート電極107とする。(図1
(d))。最後に、100%水素雰囲気中で、450℃
30分の熱処理を行ない、以下、実施例1と同様にして
半導体装置を完成する。Second Embodiment A second embodiment will be described with reference to FIGS. 1 and 6. By the same process as in Example 1, the (100) plane orientation P
After selectively forming an element isolation oxide film 102 on a silicon substrate 101, a silicon oxide film to be a gate oxide film 103 having a film thickness of 8 nm is formed in a 100% O 2 atmosphere at a temperature of 850 ° C. (FIG. a)). Next, a silicon film 104 to be an electrode was formed on the gate oxide film while doping phosphorus (P) so that the film thickness after formation was 100 nm. At this time, the P concentration is 1 × 10 20 cm ~ 3 . After that, with the implantation energy of 25 keV, nitrogen ions 105
Ion implantation was performed. At this time, most of the implanted ions are present in the electrode. The driving amount is 1 each
It is × 10 14 to 1 × 10 16 cm to 2 . Then 100%
By performing heat treatment at 900 ° C. for 30 minutes in a nitrogen atmosphere, ion implantation damage recovery and silicon film 1
The activation of P of 04 was attempted (FIG. 1 (b)). The nitrogen atoms after this annealing are mainly present in the electrode and the oxide film, and the nitrogen atom concentration peaks at this time are in the electrode and the oxide film, and the peak concentration is 1 × 10 18 to 1 × 10 5. 22 cm
~ 3 . A resist 106 is applied on the silicon film 104 and patterned, and then the silicon film 104 is patterned using the resist 106 as a mask (FIG. 1C). After that, the resist 106 is removed,
The silicon film is used as the gate electrode 107. (Fig. 1
(D)). Finally, in a 100% hydrogen atmosphere, 450 ℃
After heat treatment for 30 minutes, the semiconductor device is completed in the same manner as in Example 1.
【0017】この試料の、容量−電圧測定結果より求め
た界面準位密度を図6に示す。窒素打ち込み無しの試料
と比較して、界面準位が低減できていることが分かる。
しかも、容量低下及び酸化膜厚増加は見られなかった。
さらに、絶縁性は劣化しなかった。また、同様の実験を
n型シリコン基板を用いて行なった場合も、本実施例と
全く同様の効果が得られた。さらに、同様の実験を基板
面方位が(110)、(111)である基板を用いて行
なった場合にも、本実施例と全く同様の効果が得られ
た。また、面方位が(100)、(110)又は(11
1)からの傾斜角度が10°以内であるシリコン基板を
それぞれ用いた場合にも、本実施例と全く同様の効果が
得られた。The interface state density of this sample obtained from the capacitance-voltage measurement results is shown in FIG. It can be seen that the interface state can be reduced as compared with the sample without nitrogen implantation.
Moreover, the capacity was not reduced and the oxide film thickness was not increased.
Furthermore, the insulation did not deteriorate. Also, when the same experiment was performed using an n-type silicon substrate, the same effect as this example was obtained. Furthermore, when the same experiment was performed using substrates having substrate plane orientations of (110) and (111), the same effect as that of this example was obtained. In addition, the plane orientation is (100), (110) or (11
Even when each of the silicon substrates whose inclination angle from 1) was within 10 ° was used, the same effect as this example was obtained.
【0018】実施例3 図1、図7を用いて、第3の実施例を説明する。実施例
1と同様のプロセスにより、(100)面方位であるP
型シリコン基板101上に素子分離酸化膜102を選択
的に形成した。その後、温度850℃、100%O2雰
囲気中で膜厚8nmのゲート酸化膜103となるシリコ
ン酸化膜を形成する(図1(a))。次に同ゲート酸化
膜上に形成後の膜厚が100nmになるようにリン
(P)をドーピングしながら電極となるシリコン膜10
4を形成した。この時、P濃度は1×1020cm~3であ
る。その後、打ち込みエネルギー160keVで窒素イ
オン105のイオン打ち込みを行なった。このとき、打
ち込まれたイオンの多くは、基板中に存在する。打込み
量は、1×1014cm~2である。Third Embodiment A third embodiment will be described with reference to FIGS. 1 and 7. By the same process as in Example 1, the (100) plane orientation P
An element isolation oxide film 102 was selectively formed on the silicon substrate 101. Then, a silicon oxide film to be the gate oxide film 103 having a film thickness of 8 nm is formed in a 100% O 2 atmosphere at a temperature of 850 ° C. (FIG. 1A). Next, a silicon film 10 to be an electrode is formed on the gate oxide film while doping phosphorus (P) so that the film thickness after formation is 100 nm.
4 was formed. At this time, the P concentration is 1 × 10 20 cm ~ 3 . After that, the nitrogen ions 105 were ion-implanted at an implantation energy of 160 keV. At this time, most of the implanted ions are present in the substrate. The implantation amount is 1 × 10 14 cm- 2 .
【0019】その後、100%窒素雰囲気中で900
℃、30分間の熱処理を行なうことにより、イオン打ち
込み損傷の回復と、シリコン膜104のPの活性化を図
った(図1(b))。なお、このアニール後の窒素原子
は、酸化膜中及び基板中に存在し、このときの窒素原子
濃度ピークは酸化膜と基板界面付近にあり、ピーク濃度
は1×1018〜1×1021cm~3である。このシリコン
膜104上にレジスト106を塗布してパターンニング
した後、このレジスト106をマスクにしてシリコン膜
104をパターンニングする(図1(c))。その後、
レジスト106を除去して、上記シリコン膜をゲート電
極107とする。(図1(d))。最後に、100%水
素雰囲気中で、450℃、30分の熱処理を行ない、以
下、実施例1と同様にして半導体装置を完成する。Then, in a 100% nitrogen atmosphere, 900
By performing a heat treatment at 30 ° C. for 30 minutes, recovery of ion implantation damage and activation of P in the silicon film 104 were achieved (FIG. 1B). The nitrogen atoms after this annealing are present in the oxide film and the substrate, and the nitrogen atom concentration peak at this time is near the interface between the oxide film and the substrate, and the peak concentration is 1 × 10 18 to 1 × 10 21 cm 2. ~ 3 . A resist 106 is applied on the silicon film 104 and patterned, and then the silicon film 104 is patterned using the resist 106 as a mask (FIG. 1C). afterwards,
The resist 106 is removed and the silicon film is used as the gate electrode 107. (FIG. 1 (d)). Finally, heat treatment is performed at 450 ° C. for 30 minutes in a 100% hydrogen atmosphere, and the semiconductor device is completed in the same manner as in Example 1.
【0020】この試料の、容量−電圧測定結果より求め
た界面準位密度を図7に示す。窒素打ち込み無しの試料
と比較して、界面準位が低減できていることが分かる。
しかも、酸化膜容量低下及び膜厚増加は見られなかっ
た。また、絶縁性は劣化しなかった。さらに、ゲート酸
化を温度900℃、窒素中1%酸素雰囲気で行なった場
合にも本実施例と同様の効果が得られた。シリコン基板
の面方位が(100)の場合と(111)の場合の界面
準位密度を図7に合わせて示す。また、同様の実験をn
型シリコン基板を用いて行なった場合も、基板面方位が
(110)である基板を用いて行なった場合にも、本実
施例と全く同様の効果が得られた。また、面方位が(1
00)、(110)又は(111)からの傾斜角度が1
0°以内であるシリコン基板をそれぞれ用いた場合に
も、本実施例と全く同様の効果が得られた。The interface state density of this sample obtained from the capacitance-voltage measurement results is shown in FIG. It can be seen that the interface state can be reduced as compared with the sample without nitrogen implantation.
Moreover, no decrease in oxide film capacity and no increase in film thickness were observed. Also, the insulation did not deteriorate. Further, when the gate oxidation was performed at a temperature of 900 ° C. in a 1% oxygen atmosphere in nitrogen, the same effect as this example was obtained. The interface state densities when the plane orientation of the silicon substrate is (100) and (111) are also shown in FIG. In addition, a similar experiment
The same effect as that of the present example was obtained both when using the type silicon substrate and when using the substrate having the substrate surface orientation of (110). Also, the plane orientation is (1
The tilt angle from 00), (110) or (111) is 1
Even when the silicon substrates each having an angle of 0 ° or less were used, the same effect as that of this example was obtained.
【0021】実施例4 図1、図8を用いて、第4の実施例を説明する。実施例
1と同様のプロセスにより、(100)面方位であるP
型シリコン基板101上に素子分離酸化膜102を選択
的に形成した。その後、温度850℃、100%O2雰
囲気中で膜厚8nmのゲート酸化膜103となるシリコ
ン酸化膜を形成する(図1(a))。次に同ゲート酸化
膜上に、形成後の膜厚が100nmになるようにリン
(P)をドーピングしながら電極となるシリコン膜10
4を形成した。この時、P濃度は1×1020cm~3であ
る。その後、打ち込みエネルギー45keVで窒素イオ
ンとフッ素イオン105のイオン打ち込みをそれぞれ行
なった。このとき、打ち込まれたイオンの多数はゲート
酸化膜中に存在する。打込み量は、各々1×1014、1
×1015cm~2である(図1(b))。その後、100
%窒素雰囲気中で900℃、30分間の熱処理を行なう
ことにより、イオン打ち込み損傷の回復と、シリコン膜
104のPの活性化を図った。このシリコン膜104上
にレジスト106を塗布してパターンニングした後、こ
のレジスト106をマスクにしてシリコン膜104をパ
ターンニングする(図1(c))。その後、レジスト1
06を除去して、上記シリコン膜104をゲート電極1
07とする。(図1(d))。最後に、100%水素雰
囲気中で、450℃、30分の熱処理を行ない、以下、
実施例1と同様にして半導体装置を完成する。この時
の、容量−電圧測定結果より求めた界面準位密度を図8
に示す。窒素打ち込み無しの試料と比較して、界面準位
が低減できていることが分かる。しかも、容量低下及び
酸化膜厚増加は見られなかった。また、絶縁性は劣化し
なかった。Fourth Embodiment A fourth embodiment will be described with reference to FIGS. By the same process as in Example 1, the (100) plane orientation P
An element isolation oxide film 102 was selectively formed on the silicon substrate 101. Then, a silicon oxide film to be the gate oxide film 103 having a film thickness of 8 nm is formed in a 100% O 2 atmosphere at a temperature of 850 ° C. (FIG. 1A). Next, on the gate oxide film, a silicon film 10 to be an electrode is formed while doping phosphorus (P) so that the film thickness after formation is 100 nm.
4 was formed. At this time, the P concentration is 1 × 10 20 cm ~ 3 . Then, nitrogen ions and fluorine ions 105 were ion-implanted at an implantation energy of 45 keV. At this time, most of the implanted ions are present in the gate oxide film. The driving amount is 1 × 10 14 , 1 respectively.
It is × 10 15 cm to 2 (Fig. 1 (b)). Then 100
By performing heat treatment at 900 ° C. for 30 minutes in a nitrogen atmosphere, recovery of ion implantation damage and activation of P in the silicon film 104 were achieved. A resist 106 is applied on the silicon film 104 and patterned, and then the silicon film 104 is patterned using the resist 106 as a mask (FIG. 1C). Then resist 1
06 to remove the silicon film 104 from the gate electrode 1
07. (FIG. 1 (d)). Finally, heat treatment was performed at 450 ° C. for 30 minutes in a 100% hydrogen atmosphere.
A semiconductor device is completed in the same manner as in Example 1. The interface state density obtained from the capacitance-voltage measurement result at this time is shown in FIG.
Shown in. It can be seen that the interface state can be reduced as compared with the sample without nitrogen implantation. Moreover, the capacity was not reduced and the oxide film thickness was not increased. Also, the insulation did not deteriorate.
【0022】なお、上記アニール後の窒素原子は、電極
中、酸化膜中及び基板中に存在し、また、フッ素原子は
酸化膜中に存在し、窒素原子及びフッ素原子の濃度分布
はいずれも酸化膜中にピークを持ち、ピーク濃度をSI
MS計測により求めると、各々1×1018cm~3以上1
×1021cm~3以下であった。次に、フッ素イオンの打
ち込みエネルギーは上記のままで、窒素イオンの打ち込
みエネルギーを25keVに設定して同様の実験を行な
った。打ち込まれた窒素イオンの多くは電極中に存在
し、また、アニール後は電極中及び酸化膜中に存在し、
その濃度分布は電極中にピークを持ち、ピーク濃度は1
×1018cm~3以上1×1021cm~3以下であった。フ
ッ素原子については上記と同じであった。この時も、上
記実施例と全く同様の効果が得られた。The nitrogen atoms after the annealing are present in the electrode, the oxide film and the substrate, and the fluorine atoms are present in the oxide film, and the concentration distributions of the nitrogen atoms and the fluorine atoms are both oxidized. There is a peak in the film, and the peak concentration is SI
Each measured by MS measurement is 1 × 10 18 cm ~ 3 or more 1
It was × 10 21 cm 3 or less. Next, the same experiment was conducted by setting the implantation energy of nitrogen ions to 25 keV while keeping the implantation energy of fluorine ions as above. Most of the implanted nitrogen ions exist in the electrode, and also exist in the electrode and the oxide film after annealing.
The concentration distribution has a peak in the electrode, and the peak concentration is 1
It was not less than × 10 18 cm -3 and not more than 1 × 10 21 cm -3 . The fluorine atom was the same as above. Also at this time, the same effect as that of the above-mentioned embodiment was obtained.
【0023】また、フッ素イオンの打ち込みエネルギー
は上記のままで、窒素イオンの打ち込みエネルギーを1
60keVに設定して同様の実験を行なった。打ち込ま
れた窒素イオンの多くは基板中に存在し、また、アニー
ル後は酸化膜中及び基板中に存在し、その濃度分布は酸
化膜と基板界面付近にピークを持ち、ピーク濃度は1×
1018cm~3以上1×1021cm~3以下であった。フッ
素原子については上記と同じであった。この場合も本実
施例と全く同様の効果が得られた。The implantation energy of fluorine ions is the same as above, and the implantation energy of nitrogen ions is 1
A similar experiment was conducted with the setting of 60 keV. Most of the implanted nitrogen ions exist in the substrate, and also exist in the oxide film and the substrate after annealing, and the concentration distribution has a peak near the interface between the oxide film and the substrate, and the peak concentration is 1 ×.
It was 10 18 cm 3 or more and 1 × 10 21 cm 3 or less. The fluorine atom was the same as above. Also in this case, the same effect as that of this embodiment was obtained.
【0024】さらにまた、フッ素イオンの打ち込みエネ
ルギーを25keVに、窒素イオンの打ち込みエネルギ
ーを25、45、160keVの3種類に設定し、同様
の実験を行なうと、打ち込まれたフッ素イオンの多数は
ゲート酸化膜中に存在し、またアニール後もゲート酸化
膜中に存在する。アニール後のフッ素原子の濃度分布
は、電極と酸化膜の界面又は酸化膜と基板の界面の少な
くとも一方にピークを持つ。窒素原子については、上記
各実施例の打ち込みエネルギーが25、45、160k
eVの場合と同様であり、各々の場合のアニール後の窒
素原子の濃度分布は上述のように、各々電極中、酸化膜
中、酸化膜と基板の界面付近にピークを持つ。これらの
フッ素原子及び窒素原子のピーク濃度は、各々1×10
18cm~3以上1×1021cm~3以下であった。この場合
も、本実施例と全く同様の効果が得られた。Furthermore, when the implantation energy of fluorine ions is set to 25 keV and the implantation energy of nitrogen ions is set to three types of 25, 45, and 160 keV, and a similar experiment is performed, many of the implanted fluorine ions are gate-oxidized It exists in the film and also exists in the gate oxide film after annealing. The concentration distribution of fluorine atoms after annealing has a peak at at least one of the interface between the electrode and the oxide film or the interface between the oxide film and the substrate. Regarding the nitrogen atom, the implantation energies of the above-mentioned respective examples are 25, 45 and 160 k.
As in the case of eV, the concentration distribution of nitrogen atoms after annealing in each case has peaks in the electrodes, in the oxide film, and near the interface between the oxide film and the substrate, as described above. The peak concentration of these fluorine atoms and nitrogen atoms is 1 × 10
It was 18 cm 3 or more and 1 × 10 21 cm 3 or less. Also in this case, the same effect as that of the present embodiment was obtained.
【0025】また、同様の実験をn型シリコン基板を用
いて行なった場合も、本実施例と全く同様の効果が得ら
れた。さらに、同様の実験を基板面方位が(110)、
(111)である基板を用いて行なった場合にも、本実
施例と全く同様の効果が得られた。また、面方位が(1
00)、(110)又は(111)からの傾斜角度が1
0°以内であるシリコン基板をそれぞれ用いた場合に
も、本実施例と全く同様の効果が得られた。Also, when the same experiment was performed using an n-type silicon substrate, the same effect as that of this embodiment was obtained. Furthermore, a similar experiment was conducted with a substrate plane orientation of (110),
The same effect as that of this example was obtained when the process was performed using the substrate of (111). Also, the plane orientation is (1
The tilt angle from 00), (110) or (111) is 1
Even when the silicon substrates each having an angle of 0 ° or less were used, the same effect as that of this example was obtained.
【0026】[0026]
【発明の効果】半導体基板、電極の少なくとも一方及び
絶縁膜中に窒素原子を導入すると、導入された窒素原子
が絶縁膜と半導体基板の界面でのダングリングボンドを
終端するために、界面準位が減少し、半導体装置の界面
特性が向上する。このとき、絶縁膜の容量低下、絶縁膜
厚増加は伴わない。さらに、絶縁性は劣化しないか又は
向上する。窒素原子とともにフッ素原子を導入しても同
様である。When nitrogen atoms are introduced into the semiconductor substrate, at least one of the electrodes, and the insulating film, the introduced nitrogen atoms terminate the dangling bond at the interface between the insulating film and the semiconductor substrate, so that the interface level is increased. Is reduced and the interface characteristics of the semiconductor device are improved. At this time, the capacity of the insulating film is not decreased and the insulating film thickness is not increased. In addition, the insulation does not deteriorate or improves. The same applies when a fluorine atom is introduced together with a nitrogen atom.
【図1】本発明の半導体装置の製造工程図である。FIG. 1 is a manufacturing process diagram of a semiconductor device of the present invention.
【図2】窒素打込み量と界面準位密度との関係を表す図
である。FIG. 2 is a diagram showing a relationship between a nitrogen implantation amount and an interface state density.
【図3】窒素打込み量と酸化膜容量変化(打ち込み無し
の試料を基準にした)との関係を表す図である。FIG. 3 is a diagram showing a relationship between a nitrogen implantation amount and a change in oxide film capacity (based on a sample without implantation).
【図4】窒素打ち込み量と酸化膜厚変化(打ち込み無し
の試料を基準にした)との関係を表す図である。FIG. 4 is a diagram showing a relationship between a nitrogen implantation amount and a change in oxide film thickness (based on a sample without implantation).
【図5】窒素打ち込み量と臨界電界強度との関係を表す
図である。FIG. 5 is a diagram showing a relationship between a nitrogen implantation amount and a critical electric field strength.
【図6】打込み量と界面準位密度との関係を表す図であ
る。FIG. 6 is a diagram showing a relationship between an implantation amount and an interface state density.
【図7】本発明の半導体装置の界面準位低減効果を表す
図である。FIG. 7 is a diagram showing the effect of reducing the interface state of the semiconductor device of the present invention.
【図8】本発明の半導体装置の界面準位低減効果を表す
図である。FIG. 8 is a diagram showing the effect of reducing the interface state of the semiconductor device of the present invention.
101 シリコン基板 102 素子分離酸化膜 103 ゲート酸化膜 104 シリコン膜 105 イオン 106 ゲート電極 101 Silicon substrate 102 Element isolation oxide film 103 Gate oxide film 104 Silicon film 105 Ion 106 Gate electrode
Claims (23)
た絶縁膜と、該絶縁膜上に形成された電極とを有する半
導体装置において、上記半導体基板及び上記電極の少な
くとも一方並びに上記絶縁膜は、窒素原子が導入された
領域を有することを特徴とする半導体装置。1. A semiconductor device having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the insulating film. At least one of the semiconductor substrate and the electrode, and the insulating film. Is a semiconductor device having a region into which nitrogen atoms are introduced.
半導体基板は、窒素原子が導入された領域を有し、か
つ、半導体基板の深さ方向に窒素原子の濃度分布のピー
クを持ち、該ピーク濃度は1×1018cm~3以上1×1
021cm~3以下であることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the semiconductor substrate has a region into which nitrogen atoms are introduced, and has a peak of concentration distribution of nitrogen atoms in a depth direction of the semiconductor substrate. Peak concentration is 1 × 10 18 cm ~ 3 or more 1 × 1
A semiconductor device having a size of 0 21 cm to 3 or less.
て、上記絶縁膜の窒素原子が導入された領域の窒素原子
の濃度は、1×1018cm~3以上1×1022cm~3以下
であることを特徴とする半導体装置。3. The semiconductor device according to claim 1, wherein the concentration of nitrogen atoms in the region of the insulating film into which nitrogen atoms are introduced is 1 × 10 18 cm 3 or more and 1 × 10 22 cm 3 or less. A semiconductor device characterized by:
体装置において、上記半導体基板の面方位の傾斜角度が
(100)面方位から±10°以内か、(111)面方
位から±10°以内か又は(110)面方位から±10
°以内であることを特徴とする半導体装置。4. The semiconductor device according to claim 1, wherein a tilt angle of a plane orientation of the semiconductor substrate is within ± 10 ° from a (100) plane orientation or ± from a (111) plane orientation. Within 10 ° or ± 10 from (110) plane orientation
A semiconductor device characterized by being within °.
た絶縁膜と、該絶縁膜上に形成された電極とを有する半
導体装置において、上記絶縁膜は、窒素原子及びフッ素
原子が導入された領域を有し、上記半導体基板及び上記
電極の少なくとも一方に窒素原子が導入された領域を有
することを特徴とする半導体装置。5. A semiconductor device having a semiconductor substrate, an insulating film formed on the semiconductor substrate, and an electrode formed on the insulating film, wherein nitrogen atoms and fluorine atoms are introduced into the insulating film. A semiconductor device having a region in which nitrogen atoms are introduced into at least one of the semiconductor substrate and the electrode.
絶縁膜の窒素原子及びフッ素原子が導入された領域の窒
素原子及びフッ素原子の濃度は、いずれも1×1018c
m~3以上1×1021cm~3以下であることを特徴とする
半導体装置。6. The semiconductor device according to claim 5, wherein the concentration of nitrogen atoms and fluorine atoms in the region of the insulating film introduced with nitrogen atoms and fluorine atoms is 1 × 10 18 c.
A semiconductor device having a size of m 3 or more and 1 × 10 21 cm 3 or less.
て、上記半導体基板の面方位の傾斜角度が(100)面
方位から±10°以内か、(111)面方位から±10
°以内か又は(110)面方位から±10°以内である
ことを特徴とする半導体装置。7. The semiconductor device according to claim 5, wherein the inclination angle of the plane orientation of the semiconductor substrate is within ± 10 ° from the (100) plane orientation or ± 10 from the (111) plane orientation.
A semiconductor device, which is within ° or within ± 10 degrees from the (110) plane orientation.
上に電極を形成し、少なくとも該電極に窒素原子を導入
し、請求項1から4のいずれか一に記載の半導体装置を
形成することを特徴とする半導体装置の製造方法。8. A semiconductor device according to claim 1, wherein an insulating film is formed on a semiconductor substrate, an electrode is formed on the insulating film, and nitrogen atoms are introduced into at least the electrode. A method of manufacturing a semiconductor device, which comprises forming the semiconductor device.
上に電極を形成し、該電極を通して少なくとも該絶縁膜
に窒素原子を導入し、請求項1から4のいずれか一に記
載の半導体装置を形成することを特徴とする半導体装置
の製造方法。9. The method according to claim 1, wherein an insulating film is formed on a semiconductor substrate, an electrode is formed on the insulating film, and nitrogen atoms are introduced into at least the insulating film through the electrode. 1. A method for manufacturing a semiconductor device, comprising forming the semiconductor device according to claim 1.
膜上に電極を形成し、該電極を通して少なくとも該半導
体基板に窒素原子を導入し、請求項1から4のいずれか
一に記載の半導体装置を形成することを特徴とする半導
体装置の製造方法。10. The method according to claim 1, wherein an insulating film is formed on a semiconductor substrate, an electrode is formed on the insulating film, and nitrogen atoms are introduced into at least the semiconductor substrate through the electrode. 1. A method for manufacturing a semiconductor device, comprising forming the semiconductor device according to claim 1.
おいて、上記窒素原子の導入は、窒素イオンの平均投影
飛程を上記電極中に設定したイオン打ち込みにより行な
うことを特徴とする半導体装置の製造方法。11. The method of manufacturing a semiconductor device according to claim 8, wherein the introduction of the nitrogen atom is performed by ion implantation in which an average projection range of nitrogen ions is set in the electrode. Production method.
おいて、上記窒素原子の導入は、窒素イオンの平均投影
飛程を上記絶縁膜中に設定したイオン打ち込みにより行
なうことを特徴とする半導体装置の製造方法。12. The method of manufacturing a semiconductor device according to claim 9, wherein the introduction of the nitrogen atoms is performed by ion implantation in which the average projected range of nitrogen ions is set in the insulating film. Manufacturing method.
において、上記窒素原子の導入は、窒素イオンの平均投
影飛程を上記半導体基板中に設定したイオン打ち込みに
より行なうことを特徴とする半導体装置の製造方法。13. The method of manufacturing a semiconductor device according to claim 10, wherein the introduction of the nitrogen atoms is performed by ion implantation in which the average projected range of nitrogen ions is set in the semiconductor substrate. Manufacturing method.
の半導体装置の製造方法において、上記イオン打ち込み
の後に上記絶縁膜を熱処理することを特徴とする半導体
装置の製造方法。14. The method of manufacturing a semiconductor device according to claim 11, wherein the insulating film is heat-treated after the ion implantation.
において、上記熱処理は、600℃から1200℃の範
囲で行なうことを特徴とする半導体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 14, wherein the heat treatment is performed in a range of 600 ° C. to 1200 ° C.
工程、該絶縁膜上に電極を形成する第2の工程及び少な
くとも該電極への窒素原子の導入と、該電極へ又は該電
極を通して該絶縁膜へのフッ素原子の導入とを所望の順
に行なう第3の工程により、請求項5から7のいずれか
一に記載の半導体装置を形成することを特徴とする半導
体装置の製造方法。16. A first step of forming an insulating film on a semiconductor substrate, a second step of forming an electrode on the insulating film, and introduction of nitrogen atoms into at least the electrode, and to the electrode or the electrode. 8. A method of manufacturing a semiconductor device, comprising forming the semiconductor device according to claim 5 through a third step of performing introduction of fluorine atoms into the insulating film in a desired order through.
工程、該絶縁膜上に電極を形成する第2の工程及び該電
極を通して少なくとも該絶縁膜への窒素原子の導入と、
該電極へ又は該電極を通して該絶縁膜へのフッ素原子の
導入とを所望の順に行なう第3の工程により、請求項5
から7のいずれか一に記載の半導体装置を形成すること
を特徴とする半導体装置の製造方法。17. A first step of forming an insulating film on a semiconductor substrate, a second step of forming an electrode on the insulating film, and introducing at least nitrogen atoms into the insulating film through the electrode,
6. The third step of introducing fluorine atoms into the insulating film to the electrode or through the electrode in a desired order,
7. A method of manufacturing a semiconductor device, comprising forming the semiconductor device according to any one of items 1 to 7.
工程、該絶縁膜上に電極を形成する第2の工程及び該電
極を通して少なくとも該半導体基板への窒素原子の導入
と、該電極へ又は該電極を通して該絶縁膜へのフッ素原
子の導入とを所望の順に行なう第3の工程により、請求
項5から7のいずれか一に記載の半導体装置を形成する
ことを特徴とする半導体装置の製造方法。18. A first step of forming an insulating film on a semiconductor substrate, a second step of forming an electrode on the insulating film, and introduction of nitrogen atoms into at least the semiconductor substrate through the electrode, and the electrode. 9. A semiconductor device according to claim 5, wherein the semiconductor device is formed by a third step of performing introduction of fluorine atoms into the insulating film in the desired order through or through the electrode. Manufacturing method.
において、上記窒素原子の導入は、窒素イオンの平均投
影飛程を上記電極中に設定したイオン打ち込みにより行
ない、上記フッ素原子の導入は、フッ素イオンの平均投
影飛程を上記電極中又は上記絶縁膜中に設定したイオン
打ち込みにより行なうことを特徴とする半導体装置の製
造方法。19. The method of manufacturing a semiconductor device according to claim 16, wherein the introduction of the nitrogen atom is performed by ion implantation in which an average projected range of nitrogen ions is set in the electrode, and the introduction of the fluorine atom is performed. A method for manufacturing a semiconductor device, characterized in that the average projected range of fluorine ions is performed by ion implantation set in the electrode or in the insulating film.
において、上記窒素原子の導入は、窒素イオンの平均投
影飛程を上記絶縁膜中に設定したイオン打ち込みにより
行ない、上記フッ素原子の導入は、フッ素イオンの平均
投影飛程を上記電極中又は上記絶縁膜中に設定したイオ
ン打ち込みにより行なうことを特徴とする半導体装置の
製造方法。20. The method of manufacturing a semiconductor device according to claim 17, wherein the nitrogen atoms are introduced by ion implantation in which an average projected range of nitrogen ions is set in the insulating film, and the fluorine atoms are introduced. A method for manufacturing a semiconductor device, wherein the average projected range of fluorine ions is performed by ion implantation set in the electrode or the insulating film.
において、上記窒素原子の導入は、窒素イオンの平均投
影飛程を上記半導体基板中に設定したイオン打ち込みに
より行ない、上記フッ素原子の導入は、フッ素イオンの
平均投影飛程を上記電極中又は上記絶縁膜中に設定した
イオン打ち込みにより行なうことを特徴とする半導体装
置の製造方法。21. The method of manufacturing a semiconductor device according to claim 18, wherein the introduction of the nitrogen atom is performed by ion implantation in which an average projected range of nitrogen ions is set in the semiconductor substrate, and the introduction of the fluorine atom is performed. A method for manufacturing a semiconductor device, wherein the average projected range of fluorine ions is performed by ion implantation set in the electrode or the insulating film.
の半導体装置の製造方法において、上記第3の工程の後
に上記絶縁膜を熱処理する第4の工程を有することを特
徴とする半導体装置の製造方法。22. The method of manufacturing a semiconductor device according to claim 19, further comprising a fourth step of heat-treating the insulating film after the third step. Manufacturing method.
において、上記熱処理は、600℃から1200℃の範
囲で行なうことを特徴とする半導体装置の製造方法。23. The method of manufacturing a semiconductor device according to claim 22, wherein the heat treatment is performed in a range of 600 ° C. to 1200 ° C.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18067192A JPH0629314A (en) | 1992-07-08 | 1992-07-08 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18067192A JPH0629314A (en) | 1992-07-08 | 1992-07-08 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0629314A true JPH0629314A (en) | 1994-02-04 |
Family
ID=16087278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18067192A Pending JPH0629314A (en) | 1992-07-08 | 1992-07-08 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0629314A (en) |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2709599A1 (en) * | 1993-09-02 | 1995-03-10 | Mitsubishi Electric Corp | Semiconductor device in particular of the nitrogen doped MOS type and its manufacturing process. |
FR2735908A1 (en) * | 1994-06-22 | 1996-12-27 | Mitsubishi Electric Corp | Semiconductor field effect transistor for SRAM or DRAM |
JPH1140803A (en) * | 1997-07-15 | 1999-02-12 | Toshiba Corp | Semiconductor device and its manufacture |
JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
US6069041A (en) * | 1996-11-27 | 2000-05-30 | Sharp Kabushiki Kaisha | Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms |
US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
JP2005116582A (en) * | 2003-10-03 | 2005-04-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
WO2006034181A1 (en) * | 2004-09-17 | 2006-03-30 | Honeywell International Inc. | Semiconductor-insulator-semiconductor structure for high speed applications |
CN100359694C (en) * | 2003-04-10 | 2008-01-02 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit device |
US7445994B2 (en) | 2002-07-05 | 2008-11-04 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices using selective nitridation techniques |
US7566929B2 (en) | 2002-07-05 | 2009-07-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof |
-
1992
- 1992-07-08 JP JP18067192A patent/JPH0629314A/en active Pending
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6300664B1 (en) | 1993-09-02 | 2001-10-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
US6521527B1 (en) | 1993-09-02 | 2003-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of fabricating the same |
FR2709599A1 (en) * | 1993-09-02 | 1995-03-10 | Mitsubishi Electric Corp | Semiconductor device in particular of the nitrogen doped MOS type and its manufacturing process. |
FR2735908A1 (en) * | 1994-06-22 | 1996-12-27 | Mitsubishi Electric Corp | Semiconductor field effect transistor for SRAM or DRAM |
US6380036B1 (en) | 1994-06-22 | 2002-04-30 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
US6153910A (en) * | 1994-06-22 | 2000-11-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with nitrogen implanted channel region |
US6069041A (en) * | 1996-11-27 | 2000-05-30 | Sharp Kabushiki Kaisha | Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms |
JPH1140803A (en) * | 1997-07-15 | 1999-02-12 | Toshiba Corp | Semiconductor device and its manufacture |
JPH11204793A (en) * | 1997-10-24 | 1999-07-30 | Lsi Logic Corp | Electronic device gate oxide hardening method and semiconductor device |
US7445994B2 (en) | 2002-07-05 | 2008-11-04 | Samsung Electronics Co., Ltd. | Methods of forming non-volatile memory devices using selective nitridation techniques |
US7566929B2 (en) | 2002-07-05 | 2009-07-28 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof |
US8008153B2 (en) | 2002-07-05 | 2011-08-30 | Samsung Electronics Co., Ltd. | Methods of fabricating nonvolatile memory devices having gate structures doped by nitrogen |
US8552488B2 (en) | 2002-07-05 | 2013-10-08 | Samsung Electronics Co., Ltd. | Nonvolatile memory devices having gate structures doped by nitrogen |
CN100359694C (en) * | 2003-04-10 | 2008-01-02 | 恩益禧电子股份有限公司 | Semiconductor integrated circuit device |
JP2005116582A (en) * | 2003-10-03 | 2005-04-28 | Renesas Technology Corp | Semiconductor device and its manufacturing method |
WO2006034181A1 (en) * | 2004-09-17 | 2006-03-30 | Honeywell International Inc. | Semiconductor-insulator-semiconductor structure for high speed applications |
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