JPH06295953A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE: To realize a high-integration degree and low-leak current insulation substrate by forming mesas including semiconductor material-made device mesas and dummy mesas are formed with spacings on flat surface of the insulation substrate, replacing the dummy mesas with an insulation material, and electrically interconnecting the device mesas. CONSTITUTION: On a patterned Si layer on an insulation layer 24 device mesas 26A and adjacent dummy mesas are formed with grooves extending to the insulation layer 24 surface therebetween. A silicon dioxide layer, silicon nitride layer and polysilicon layer on the surfaces of the device mesas 26A and dummy mesas are nonselectively polished down to a polish stop layer, the dummy mesas and remaining polysilicon layer are exposed to an oxidative atmosphere to convert the dummy mesas, remaining polysilicon layer and edges of the device regions 26A into a silicon dioxide layer 38. The converted dummy mesas 38A and polysilicon layer 38B insulate the device mesas 26A from other device mesas.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to the formation of multilayer structures. More specifically, the present invention relates to forming insulated semiconductor mesas on an insulating substrate.

Relevant to the present invention is S. Ogura,
N. Rovedo and G.L. W. Invented by Doerre and filed in the US on April 30, 1992, application number 07 / 876,598 and is titled "Metho
d of Forming Thin Silicon
Mesa Having Uniform Thick
Applicant's patent application for "ness." This patent application forms a silicon mesa on an insulator using abrasion resistant silicon nitride with large wiring channel spaces between silicon mesas. Regarding what to do.

[0003]

In the manufacture of complementary field effect transistors, commonly known as CMOS devices, it is desirable to form the highly isolated device regions in which each device is formed. In the past, such device regions were formed in a common silicon substrate, and electrical isolation was provided in the substrate by selectively oxidizing or selectively doping regions of the substrate. .

More recently, it has been known to form small silicon device regions on an insulating substrate such as silicon dioxide. To complete the electrical isolation between the silicon device regions, an insulating material is formed between the silicon device regions and a CMOS device is formed in the insulated silicon device regions.

Silicon-on-insulator (SO
This structure, known as I), results in a highly isolated device area and thus a highly isolated high performance CMOS device. CMOS devices formed using the SOI structure have very low parasitic capacitance and good resistance to latch-up. Minimizing the parasitic capacitance and increasing the resistance to latch-up significantly improve the operating characteristics of CMOS devices and the circuits formed thereby.

In forming these SOI devices, they are made to a uniform thickness, typically in the range of 20-100 nm, and the thickness variation is not greater than 5-10%. It is necessary to. Large variations in thickness not only change the characteristics of the device, but also make subsequent processing more difficult, such as forming studs.

In addition to the uniform thickness of the SOI device area, S
The insulating material placed between the OI device areas must have good integrity. That is, it must conform to the sides of the underlying substrate and device areas to minimize electrical and electrical leakage.

One previously recognized problem is that during polishing, the silicon device area falls below some required thin, uniform height. Applicant's US Pat. No. 4,735,679 shows a method of forming an SOI structure in which a thin tungsten polish stop layer is placed in the trench between the silicon mesas. The silicon mesa is then polished, where a chemical-mechanical polishing process is used to selectively remove silicon over tungsten and stop on the tungsten layer. Then
The tungsten is removed and processing of the device in the silicon mesa is performed.

[0009]

Although various processes for forming SOI structures are known, forming such structures with uniform and thin silicon device regions is extremely difficult. Furthermore, it is difficult to form an SOI structure in which the electrical insulation formed by the insulating material between the silicon device regions is such that leakage current is minimized.

[0010]

SUMMARY OF THE INVENTION It is a primary object of the present invention to provide a method of forming a semiconductor-on-insulator structure having a thin and uniform thickness of semiconductor mesas. .

Another object of the present invention is to provide a method of forming a semiconductor-on-insulator structure having a high degree of electrical isolation between semiconductor mesas.

Another object of the present invention is to provide a method of forming a semiconductor-on-insulator structure in which electrical leakage between semiconductor mesas is very low.

Another object of the present invention is to provide a method of forming a semiconductor-on-insulator structure with very low parasitic source-to-drain leakage.

Another object of the invention is to have the above characteristics,
And to provide a semiconductor-on-insulator structure that can be efficiently manufactured at low cost using commonly available semiconductor processing techniques, processes and equipment.

In accordance with the present invention, an insulating substrate comprising an insulating material having a flat surface is provided, wherein a plurality of device mesas of semiconductor material and a plurality of mesas including dummy mesas are spaced from each other. Forming a polishing stop structure of at least one selected material in a groove formed thereon and defined by the spacing between the mesas on the surface of the substrate; Polishing the plurality of mesas to the polishing stop layer to the same thickness as the stop structure and replacing the dummy mesas with an insulating material to electrically insulate the device mesas from each other. There is provided a method of manufacturing a semiconductor device including:

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to the drawings, FIG.
2 shows a silicon-on-insulator (SOI) structure 20 including. A layer of insulating material 24 (silicon dioxide in this example) is disposed on the upper surface of substrate 22. A patterned layer 26 of semiconductor material (monocrystalline silicon in this example) is formed over the insulating layer 24. In accordance with the present invention, the silicon layer 26 is a device area or device mesa 26.
A, and patterned to form a plurality of adjacent dummy mesas 26B. Insulating layer 24 through the mesa
A groove 27 that extends to the surface above the device spaces the device mesas 26A and the dummy mesas 26B.

In practice, the basic SOI structure is commercially available. This basic structure comprises a silicon substrate 22, a layer of insulator 24 adhered to the substrate 22 such as silicon dioxide and a monocrystalline silicon layer such as layer 26. The insulating layer 24 has a thickness of 100-1000 nm (+ /
-5%) with a very uniform thickness and a very flat upper surface. Due to the nature of the process of forming the silicon layer 26, the thickness uniformity is small. For example, the silicon layer 26 has a nominal thickness of 2.0 microns and the variation is +/- 0.5 microns. To form the structure 20 shown in FIG.
Is patterned using standard photoresist masking and anisotropic etching. A conventional photoresist mask is first formed so that the trenches 27 expose the areas to be etched. An etchant that works selectively with respect to the silicon layer on top of the insulating layer 24 is used so that the etch process is not very time sensitive.
For selectively etching the silicon layer 26 and stopping on silicon dioxide, for example Cl ₂ or HC
A reactive ion etching process using a dry etchant such as 1 or HBr can be used. In FIG. 1, the resulting thickness non-uniformity of mesas 26A and 26B is shown.

In practice, there are numerous device mesas 26A above the SOI structure 20. In a CMOS integrated circuit chip, a CMOS device is typically 80% of the chip.
Exists to reach. Thus, as mentioned above, it is necessary to planarize all device areas 26A to a uniform thickness. The desired device mesa 26A thickness to provide high performance CMOS devices is chosen to be 80 nm. Obviously, for different purposes, different thicknesses will be chosen.

Thus, it is necessary to reduce the thickness of device mesa 26A from its initial thickness of about 2000 nm to a uniform thickness of 80 nm. In accordance with the present invention, dummy mesas 26B are utilized as a key part of the inventive process.

To illustrate the present invention, FIGS. 2-7 show a partial enlarged area of device mesa 26A. It is clear that the described process operates on the entire upper surface of the SOI structure.

Referring to FIG. 2, polycrystalline silicon (polysilicon
A layer 28 of silicon) of 40 nm along the surface of the structure
Attached to thickness. The polysilicon layer 28 is made of silane (S
iH _Four) Using standard chemical vapor deposition (CVD)
Formed.

Silicon nitride layer 30 and polysilicon layer 3
2 are sequentially deposited on the polysilicon layer 28.
The silicon nitride layer 30 is formed to a thickness of 40 nm using a standard CVD process such as SiCl ₂ H ₂ + NH ₃ . Polysilicon layer 32 is formed to a thickness of approximately 100 nm using the polysilicon CVD process described above.

Still referring to FIG. 2, a silicon nitride layer (not shown) is deposited to a thickness of 60 nm on the polysilicon layer 32 by using the silicon nitride CVD process described above. This last silicon nitride layer is anisotropically etched (selective to polysilicon) using, for example, a dry RIE process using a CHF ₃ / O ₂ etchant.

Referring now to FIG. 3, the structure is placed in an oxidizing atmosphere, which results in polysilicon layer 32.
The exposed region is converted into silicon dioxide 32A. This oxidizing atmosphere can include, for example, an atmosphere of oxygen and water vapor. Layer 32 was initially formed to the thickness described above, and the oxidized region 32A has a very uniform thickness (ie 220 nm), which is about 2.2 times the thickness of the original polysilicon.

Referring now to FIG. 4, selective to silicon nitride over silicon dioxide and polysilicon,
A wet etch is used to form the silicon nitride sidewall 3
Remove 4. This etch can use, for example, H ₃ PO ₄ . Next, a dry etch selective to polysilicon over silicon dioxide and silicon nitride is used to remove the unprotected areas of the polysilicon layer. These unprotected areas are exposed by the removal of silicon nitride. This etch is S
It can be done by dry etch using F ₆ plasma. The exposed sidewalls of the silicon nitride layer 30 of the device mesa 26A are removed by a wet etch, such as H ₃ PO ₄ , which is selective to silicon nitride over silicon dioxide. The resulting structure is shown in FIG.

Referring now to FIG. 5, device mesa 26A.
And non-selective polishing is used to remove the silicon dioxide layer 32A, the silicon nitride layer 30 and the polysilicon layer 28 on the top surface of the dummy mesas 26B.
This polishing can be performed using a KOH-stabilized colloidal silica solution chemo-mechanical polishing process. This polishing step also removes some of the upper portion of mesas 26A and 26B, but does
It is stopped before reaching the silicon oxide layer 32A. The resulting structure is shown in FIG.

Thus, in the above-described non-selective polishing step, the dummy mesas 26B have the polishing stop layer 3 in the groove 27.
It serves to protect what is 0 and 32A.

Referring to FIG. 6, an initial selection is made to remove the upper portions of the dummy mesas 26B and the silicon mesas 26A until they stop at the upper surface of the silicon dioxide polish stop layer 32A in the trench 27. Polishing is performed. The selective polishing is, NH ₄ OH @ - stabilized chemically using a colloidal silica Suraryi - mechanical process is desirable. The mesas 26A and 26B have grooves 27
The total thickness of the layers 28, 30 and 32A within, ie 300n
Note that it has a thickness or height equal to m.
By including a dummy mesa 26B on top of this structure, the thickness of the dummy and device mesas is made very uniform. In fact, experiments have shown that the thickness uniformity of mesas 26A and 26B in the above process is:
It was possible to control within about +/- 15 nm.

At this point, if it is desired to keep certain selected device mesas 26A or dummy mesas 26B at the above thickness, the portion of the structure containing these selected devices is protected. Masked. This masking is done using standard photolithographic processing techniques to form the resist mask. Otherwise, the above structure is processed according to the steps described below.

Referring to FIG. 7, the first polish stop layer 32.
A is selectively removed to expose the underlying silicon nitride polish stop layer 30 and silicon regions 26A and 26B. This removal is performed using, for example, an HF solution. A second selective polish is then performed using a polishing process that is selective to silicon over silicon nitride. Thus, the mesas 26A and 26B are polished down through the thickness of the polish stop layer 32A down to the second polish stop layer, the silicon nitride layer 30, in the groove 27. The second abrasive is a chemical used NH ₄ OH @ - stabilized colloidal Suraryi - it is preferably performed by using a mechanical polishing process. At this point, mesas 26A and 2
Note that the thickness of 6 is the total thickness of polysilicon layer 28 and silicon nitride layer 30 in trench 27 or 80 nm. Experiments have shown that using a process that includes a dummy mesa 26B and a second selective polishing step, the thickness uniformity of all mesas is about +/- 3.0 nm.
It turned out that it is possible to control.

If any region of the structure contains a photoresist mask, so that the thickness of the mesas in this region is greater than the thickness described with respect to FIG. It is removed by the method of. The mesas thus masked have the uniform dimensions of the large thicknesses mentioned above, so that in this case thick mesas and thin mesas are present on this structure.

From the above description, it is clear that the resulting thickness of mesas 26A and 26B can be controlled to about the same error as the thickness of the polish stop layer deposited in groove 27.
Thus, it turns out that this is a highly controllable process.

Referring to FIG. 8, the SOI structure 2 of FIG. 1 which has undergone the processing and polishing steps described with respect to FIGS.
0 is shown. Dummy and device mesas 26B and 26
A is flattened to the above-mentioned uniform thickness.
In the groove 27 between the mesas 26A and 26B, there is a polysilicon layer 28 and a silicon nitride layer 30 above it.

Referring to FIG. 9, an etch selective to silicon nitride over silicon and polysilicon, such as a wet etch such as H ₃ PO ₄ , removes the remaining portion of silicon nitride 30 in trench 27. It is used to
Thus, the polysilicon layer 28 is exposed to the ambient atmosphere. Next, a silicon nitride protective mask 36 is formed over the device mesas 26A, covering the portions of the mesas that will be the active device regions. The mask 36 is made of the above-mentioned silicon nitride C.
It is formed by using a VD process and conventional photoresist masking techniques that expose only device mesas 26A. It is clear from FIG. 9 that the mask 36 is formed on the upper surface of the device mesa 26A so as to cover the region having a slightly smaller area than this.

Referring to FIG. 10, in accordance with the key concepts of the present invention, the structure of FIG. 9 including dummy mesa 26B and remaining polysilicon layer portion 28 is exposed to an oxidizing atmosphere. This atmosphere may be an atmosphere of oxygen and water vapor, for example.

Thus, the unmasked edges of dummy mesa 26B, remaining polysilicon layer portion 28 and device region 26A are converted to an insulating layer of silicon dioxide 38. The converted dummy mesas are shown at 38A, while the converted polysilicon layers are shown at 38B. Thus, each device mesa 26A is electrically isolated from the same other device mesas as this.

Further, following the process described above, the active device mesa 26 shown in the completed structure of FIG.
A is slightly smaller than the device mesa shown before FIG. This is based on the dimensions of the mask 36, as described above, and the inventors of the present invention have found that a CMOS device with significantly reduced source to drain leakage current can be realized.

The inventive method of converting the dummy mesas 26B and the portion 28 of the polysilicon layer into an integral silicon dioxide layer results in an isolated device mesa 26A having very low leakage current between mesas.

The structure shown in FIG. 10 is then used to support active semiconductor devices, such as CMOS devices, within device mesas 26A. Various processes and structures for forming such active semiconductor devices will be apparent to those skilled in the art.

Thus, a method is provided for forming an SOI structure in which the silicon device regions / mesas exhibit a highly uniform thickness and a high degree of electrical isolation. This process uses dummy mesas with a highly controllable polish stop layer to precisely control the selective polish process to produce a uniform thickness. Converting the remaining portions of the dummy mesas and the polish stop layer into an insulating layer results in a highly integrated and low leakage current insulating structure.

The present invention can be used in the formation of integrated circuits, especially in the formation of substrates for large scale CMOS integrated circuits.

Although the present invention has been described with respect to particular embodiments, it is not limited thereto. It will be apparent to those skilled in the art that various modifications, changes and improvements within the scope of the present invention are possible.

[0043]

As described above, the present invention makes it possible to realize an insulating substrate having a high degree of integration and a low leakage current.

[Brief description of drawings]

FIG. 1 is a silicon device mesa and silicon according to the present invention.
It is sectional drawing of the SOI substrate containing a dummy mesa.

FIG. 2 shows a polishing process according to the present invention shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 3 shows a polishing process according to the present invention shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 4 shows the polishing process according to the invention shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 5 shows a polishing process according to the invention as shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 6 shows a polishing process according to the present invention shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 7 shows a polishing process according to the present invention as shown in FIG.
It is sectional drawing demonstrated using the one side of one mesa.

FIG. 8 is a cross-sectional view of the SOI structure of FIG. 1 with mesas planarized according to the process shown in FIGS. 2-7.

FIG. 9 S of FIG. 8 showing the treatment of the polishing stop layer and the device mesas.
It is sectional drawing of OI structure.

FIG. 10: SOI completed according to the process of the present invention
It is sectional drawing of a structure.

[Explanation of symbols]

 20 ... SOI structure 22 ... Substrate 24 ... Insulating layer 26 ... Single crystal silicon layer 26A ... Device mesa 26B ... Dummy mesa 27 ... Groove 28. ... Polysilicon layer 30 ... Silicon nitride layer 32 ... Polysilicon layer 32A ... Oxide layer 34 ... Silicon nitride sidewalls

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Mark Anthony Jaso York Town Heights Wipoor Road 163, New York, USA 163 (72) Inventor Sabramanian Slicante Swala Eyer York City Heights Saeda Road, New York, USA 3172 (72) Inventor Scott Richard Stiffler, 6th Avenue Apartment, Brooklyn, New York, USA 4 313 (72) Inventor James Douglas Warnock Mohigan Lake Ivory Road, New York, USA 1530

Claims (8)

[Claims] 1. An insulating substrate including an insulating material having a flat surface is provided, and a plurality of device mesas of semiconductor material and a plurality of mesas including dummy mesas are formed on the surface of the substrate at intervals. Forming a polish stop structure of at least one selected material in a groove defined on the surface of the substrate by the spacing between the mesas, the plurality of mesas having a thickness of the polish stop structure. Polishing the plurality of mesas to the polishing stop layer to the same thickness, electrically isolating the device mesas from one another,
A method of manufacturing a semiconductor device, comprising replacing the dummy mesa with an insulating material. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of replacing the dummy mesa with an insulating material includes the step of replacing the dummy mesa with the insulating material. 3. The step of converting the dummy mesas to the insulating material simultaneously converts at least a portion of the polish stop structure to the insulating material, and at least the modified dummy mesas and the modified polish stop structure. The method of manufacturing a semiconductor device according to claim 2, wherein a part of the insulating material forms an integral layer. 4. The dummy mesa and a portion of the polish stop structure are placed in an oxidizing atmosphere and the dummy mesa and a portion of the polish stop structure are converted to an oxide layer.
Of manufacturing a semiconductor device of. 5. The step of forming the polish stop structure comprises: a layer of at least one selected material having a thickness less than a thickness of the plurality of mesas on the substrate and the plurality of mesas. And removing the at least one layer of selected material from the top and side surfaces of the plurality of mesas.
4. The method of manufacturing a semiconductor device of claim 3, including leaving two layers of selected material on the surface of the trench in the substrate. 6. The step of converting a portion of the dummy mesa and the polishing stop structure into an insulating material comprises forming a protective layer of an oxidation resistant material on the device mesa and converting the device mesa into an oxide. The method for manufacturing a semiconductor device according to claim 4, further comprising a step of preventing 7. The method of manufacturing a semiconductor device according to claim 6, wherein the protective layer is applied to a portion other than an edge of the upper surface of the device mesa, and the edge portion of the device mesa is changed to the oxide. 8. The step of polishing the plurality of mesas comprises chemically and mechanically polishing the plurality of mesas using a polishing material selective to the plurality of mesas over the polishing stop structure. The method of manufacturing a semiconductor device according to claim 1.