JPH06283999A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To simply minimize the influence of a noise from a digital circuit on an analog circuit by shifting the phase of a clock signal for controlling the respective circuits in the semiconductor integrated circuit device on which the digital circuit and analog circuits are both mounted in mixture. CONSTITUTION:Four delay elements D1-D4 which differ in delay time are previously formed and a delay element having an optimum delay time is found from among those delay elements D1-D4; and the inputs of code signals X1 and X2 of a decoder 18 are properly fixed to activate only the found delay element.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more specifically, to an analog-digital mixed type semiconductor in which an analog circuit and a digital circuit are formed on the same semiconductor substrate. The present invention relates to an integrated circuit device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, there has been provided a semiconductor integrated circuit device such as an LSI in which an analog circuit and a digital circuit are formed on the same silicon wafer. In such an analog-digital mixed type LSI, there is a problem that noise is mixed from the digital circuit to the analog circuit. As a countermeasure, for example, a wiring pattern,
In addition to the method of devising the pin arrangement and the like, there is a method of relatively shifting the phase of the clock signal for operating the analog circuit and the digital circuit.

For example, IEICE research report ICD
89-119 "Video signal processing L with built-in AD / DA converter"
SI ", page 62, discloses a method of reducing interference due to noise by disposing an output buffer that switches asynchronously with an AD converter at a position far from the AD converter.

On the other hand, FIG. 23 is a block diagram showing a configuration of a one-chip microcomputer which is an analog-digital mixed type semiconductor integrated circuit device disclosed in Japanese Patent Laid-Open No. 3-75976.

As shown in FIG. 23, this one-chip microcomputer comprises a digital circuit 1 including a CPU 1a, a timer 1b and the like, and an analog circuit 2 including an A / D converter and the like.

The digital circuit 1 operates based on the first clock signal CLK1 from the system clock signal generator 3. The analog circuit 2 has a first delay circuit 4 and a first delay circuit 4.
Of the second clock signal CLK2 whose phase is delayed.

As shown in the timing chart of FIG. 24, in the digital circuit 1, the first clock signal CLK
Noise is generated with the rise and fall of 1. For example, when the digital circuit 1 and the analog circuit 2 are connected to the same power supply line, the noise generated in the digital circuit 1 is mixed into the analog circuit 2 via the power supply line. The influence of this noise causes the analog circuit 2 to malfunction and deteriorates its performance. The influence of noise from the digital circuit 1 to the analog circuit 2 occurs not only through the power supply line but also through various paths such as the inside of the silicon wafer and the electromagnetic space including the wiring.

Therefore, in this microcomputer,
Second clock signal CLK for operating the analog circuit 2
The phase of 2 is set by the delay circuit 4 to the first clock signal C
It is delayed from the phase of LK1. Therefore, the analog circuit 2 does not malfunction.

On the other hand, FIG. 25 is a block diagram showing a configuration of a full-duplex modem (MODEM) which is a semiconductor integrated circuit device of an analog-digital mixed type disclosed in Japanese Patent Laid-Open No. 2-28707.

As shown in FIG. 25, this modem is
An oscillator 5 that oscillates a main clock, a 1/2 frequency divider 6 including a flip-flop, and a transmission circuit 7.
And a receiving circuit 8.

The transmitter circuit 7 and the receiver circuit 8 respectively include a digital PLL circuit 7a or 8a, a D / A converter 7b or an A / D converter 8b, and an SCF (Swit).
chedCapacitor Filter) and other filter groups 7c or 8c.

In this modem, a digital circuit and an analog circuit are formed on the same substrate, and clocks mutually shifted are supplied to these modems, so that the influence of noise mixed from the digital circuit to the analog circuit through a power supply line or the like is exerted. Is configured to prevent

[0013]

However, in the actual analog-digital mixed type semiconductor integrated circuit, the phase of the clock signal immediately before being applied to the analog circuit or the digital circuit is from the outside due to the wiring resistance and the stray capacitance. It is already behind the phase of the applied clock signal. Further, it is rare that all digital circuits operate based on clock signals having the same phase, and in most cases, they operate based on clock signals having various different phases. Further, there are many cases where a plurality of types of clock signals having different frequencies are generated inside the digital circuit. In addition, analog circuits and digital circuits may operate asynchronously.

Therefore, it is difficult to predict the optimum phase difference between the clock signals applied to the analog circuit and the digital circuit before designing. Therefore, it is extremely difficult to optimally set the performance of the analog-digital mixed type semiconductor integrated circuit device.

That is, conventionally, since the phase difference between the clock signals applied to the analog circuit and the digital circuit was set based on the prediction, it was difficult to optimize the performance of the analog circuit. Further, in order to optimize the performance of the analog circuit, it was necessary to repeatedly revise the mask and form a delay circuit having an optimum delay time by trial and error.

An object of the present invention is to provide an analog-digital mixed type semiconductor integrated circuit in which the influence of noise from a digital circuit to an analog circuit is reduced as much as possible.

Another object of the present invention is to reduce the influence of noise from the digital circuit to the analog circuit as much as possible by relatively shifting the phases of the clock signal of the analog circuit and the clock signal of the digital circuit. Is.

Still another object of the present invention is to easily specify the optimum phase difference between the clock signals.

Yet another object of the present invention is to optimize the performance of analog circuits with as few masks as possible.

[0020]

SUMMARY OF THE INVENTION The present invention is summarized as a semiconductor integrated circuit device and includes a semiconductor substrate, a digital circuit, an analog circuit, and a phase control means. The digital circuit is formed on the semiconductor substrate and operates based on the first clock signal. The analog circuit is formed on the semiconductor substrate and operates based on the second clock signal having the same cycle as the first clock signal.
The phase control means includes a plurality of phase shift elements capable of relatively shifting the phases of the first and second clock signals,
Activation of one of the phase shift elements shifts the phases of the first and second clock signals by a relatively constant amount.

The semiconductor integrated circuit device further includes a decoding means for activating any of the phase shift elements based on the applied code signal.

According to another aspect of the present invention, in summary, the present invention is a method for manufacturing a semiconductor integrated circuit device including one semiconductor substrate, a digital circuit, and an analog circuit. A step of forming a plurality of phase shift elements capable of relatively shifting the phases of the first and second clock signals, and which of the phase shift elements is activated, the A step of finding out whether the influence of noise is minimized, and a step of finding out the phase shift element for relatively shifting the phases of the first and second clock signals,
Immobilizing so that it can be activated.

According to still another aspect of the present invention, the present invention is a method for manufacturing a semiconductor integrated circuit device including one semiconductor substrate, a digital circuit, and an analog circuit, which includes a trial production stage and a mass production stage. including. At the prototype stage,
A step of forming a plurality of phase shift elements capable of relatively shifting the phases of the first and second clock signals on a semiconductor substrate; and which of the phase shift elements is activated, a digital circuit and an analog circuit And a step of finding out whether the influence of noise between circuits is minimized.
In the mass production stage, the phase shift element found was
And a step of forming a plurality of phase shift elements in a fixed state so as to be activated so as to relatively shift the phase of the second clock signal.

[0024]

In the semiconductor integrated circuit device according to the present invention, by activating any one of the plurality of phase shift elements, the phases of the first and second clock signals are relatively shifted by a fixed amount. Therefore, it is possible to set the phase difference between the clock signals so that the influence of noise between the digital circuit and the analog circuit is minimized.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a phase shift element that minimizes the influence of noise between the digital circuit and the analog circuit is searched for, and the searched phase shift element is used as the first and second phase shift elements.
Since the phase of the clock signal is fixed so as to be relatively shifted, it is possible to easily manufacture the semiconductor integrated circuit device in which the performances of the digital circuit and the analog circuit are optimized.

In another method of manufacturing a semiconductor integrated circuit device according to the present invention, a phase shift element that minimizes the influence of noise between analog circuits and digital circuits is searched for in the prototype stage, and the phase shift element is searched for in the mass production stage. Since multiple phase shift elements are formed with the found phase shift element fixed, the performance of the digital circuit and analog circuit is optimized by at least one revision of the mask when shifting from the prototype stage to the mass production stage. An integrated semiconductor integrated circuit device can be manufactured.

[0027]

Embodiments of a semiconductor integrated circuit device and a method of manufacturing the same according to the present invention will now be described in detail with reference to the drawings. [Embodiment 1] FIG. 1 is a block diagram showing a structure of a first embodiment of an analog-digital mixed type semiconductor integrated circuit device according to the present invention at a trial production stage.

As shown in FIG. 1, the semiconductor integrated circuit device 10 includes a digital circuit 12 and an analog circuit 1.
4, a phase control circuit 16, and a decoder 18.

The digital circuit 12 operates based on the first clock signal CLK1 applied to the clock signal input terminal 20. The analog circuit 14 is the phase control circuit 1.
It operates based on the second clock signal CLK2 from 6. The phase control circuit 16 decodes the first clock signal CLK1 applied to the clock signal input terminal 20 by a decoder 18
Then, it is delayed by a fixed time specified by the control signal Y from and output as the second clock signal CLK2. The decoder 18 decodes the code signals X1 to Xk applied to the code signal input terminal 22 and outputs it as the control signal Y.

FIG. 2 is a block diagram showing an example of the configuration of the phase control circuit 16 and the decoder 18 shown in FIG.

As shown in FIG. 2, the phase control circuit 16
Are four delay elements D1 to D4 connected in parallel with each other.
And one buffer B1 connected in series with the delay elements D1 to D4. The delay elements D1 to D4 include two switching elements S1 to S4 that are opened and closed by the control signals Y1 to Y4, and one resistor R1 to R4 connected in series between them. The resistors R1 to R4 have different values.

The decoder 18 includes two inverters I1 and I2 and four AND gates A1 to A4,
The code signals X1 and X2 applied to the code signal input terminal 22 are logically operated, and the result is the control signals Y1 to Y4.
Output as.

Table 1 below is a truth table showing the relationship between the code signals X1 and X2 and the control signals Y1 to Y4.

[0034]

[Table 1]

As is clear from Table 1, when the code signals X1 and X2 are applied to the code signal input terminal 22,
The corresponding control signals Y1 to Y4 are output by the decoder 18. One of the switching elements S1 to S of the delay elements D1 to D4 is responsive to the control signals Y1 to Y4.
4 turns on. As a result, the delay elements D1 to D1
D4 is activated.

These delay elements D1 to D4 further include a stray capacitance (not shown) parasitic on its output node, and the stray capacitance and resistors R1 to R4 form a time constant circuit. The time constants of the delay elements D1 to D4 are determined by the resistance R
Since the values of 1 to R4 are different, they are all different.

Therefore, the first clock signal CLK1 input to the phase control circuit 16 is delayed by a certain time by any of the delay elements D1 to D4, and the buffer B1.
Is output as the second clock signal CLK2. That is, the delay elements D1 to D4 are phase shift elements capable of relatively shifting the phases of the first clock signal CLK1 and the second clock signal CLK2.

As described above, first, the digital circuit 12 and the analog circuit 14 are formed, and the phase control circuit 16 and the decoder 18 are formed on one semiconductor substrate. More specifically, four delay elements D1 to D4
Is formed. The resistors R1 to R1 of the delay elements D1 to D4
The value of R4 is set at a design stage with some prediction.

Then, which of the delay elements D1 to D4 is activated is searched for to minimize the influence of noise between the digital circuit 12 and the analog circuit 14.

FIG. 3 is a block diagram showing a configuration of a device for evaluating the semiconductor integrated circuit device 10 in which the analog circuit 14, for example, the A / D converter 14a is mounted together.

As shown in FIG. 3, the A / D converter 14a converts the analog signal applied to the analog signal input terminal 24 into a digital signal based on the second clock signal CLK2 from the phase control circuit 16. . These digital signals are given to the digital circuit 12 and output to the outside through the digital signal output terminal 26.

To evaluate this semiconductor integrated circuit device 10, a sine wave generator 28 is connected to the analog signal input terminal 24, and a spectrum analyzer 30 is connected to the digital signal output terminal 26 via the D / A converter 32. .

As a result, the sine wave applied by the sine wave generator 28 is A / D converted by the A / D converter 14a and further D / A converted by the D / A converter 32, and the result is obtained by the spectrum analyzer 30. Is displayed. When various code signals X1 to Xk are input to the code signal input terminal 22 in this state, one of the delay elements D1 to D4 of the phase control circuit 16 is activated based on the code signals X1 to Xk, and the first clock signal CLK1 and The phase of the second clock signal CLK2 is relatively variously shifted. Then, the spectrum analyzer 30 measures which of the delay elements D1 to D4 is activated to minimize the frequency other than the frequency of the sine wave applied by the sine wave generation circuit 28. That is, when the reproducibility of the sine wave is the highest, the influence of the noise that the digital circuit 12 gives to the A / D converter 14a is minimal, and the A / D
The performance of converter 14a is optimized.

Next, the delay elements D1 to D4 that optimize the performance of the analog circuit 14 are fixed as those that relatively shift the phases of the first and second clock signals CLK1 and CLK2.

For example, when the decode signal X2 is "1", X
When it is determined that the performance of the analog circuit 14 is optimum when 1 is “0”, as shown in FIG.
One input of 8 is connected to the power supply V _CC , and the other input is connected to the ground GND. As a result, only the delay element D3 of the phase control circuit 16 is activated, and the phase control circuit 1
When the first clock signal CLK1 is input to 6, it is delayed by the delay time of the delay element D3 and output as the second clock signal CLK2.

Here, a method for fixing the input of the decoder 18 will be specifically described. FIG. 5 is a plan view showing a specific configuration of the inverter I1 or I2 of the decoder 18, and FIG. 6 is a circuit diagram of the inverter shown in FIG.

As shown in FIGS. 5 and 6, the inverter I1 or I2 includes a P channel MOS transistor Q1 and an N channel MOS transistor Q2. The source of the P-channel MOS transistor Q1 is connected to the power supply node 34 connected to the power supply V _CC , and the source of the N-channel MOS transistor Q2 is the ground GN.
It is connected to the ground node 35 connected to D.
P-channel MOS transistor Q1 drain and N
The drain of the channel MOS transistor Q2 is connected to the output node 36 of the inverter I1 or I2, and the gates of the transistors Q1 and Q2 are connected to the input node 37 of the inverter 1 or I2. A pad 38 is formed at the end of the output node 37.

Therefore, by applying a power supply voltage or a ground voltage to the pad 38 using a probe or the like, any one of the delay elements D1 to D1 of the phase control circuit 16 is applied.
D4 is activated.

When the delay elements D1 to D4 that optimize the performance of the analog circuit 14 are specified and it is clear that the power supply voltage should be applied to the input node 37, as shown in FIG. In addition, the input node 37a is laid out so as to be connected to the power supply node 34 using a mask different from the mask used in the trial production stage.

As described above, according to the method of manufacturing the semiconductor integrated circuit device, the first and second clock signals CLK1 and CLK1 are set so that the influence of noise on the digital circuit 12 to the analog circuit 14 is minimized. The phase difference of CLK2 can be optimally set.

In addition, all the delay elements D1 to
Since the layout is such that D4 can be activated and only the delay elements D1 to D4 that optimize the performance of the analog circuit 14 at the mass production stage can be activated, mass production is started from the prototype stage. The mask only needs to be revised once at the stage.

Therefore, a high-performance and inexpensive analog-digital mixed type integrated circuit device can be manufactured in a short period of time, and the analog circuit 12 can be shipped with its performance optimized.

Further, in this embodiment, since the decoder 18 is provided, any of the four delay elements D1 to D4 can be activated based on the two code signals X1 and X2.

In this embodiment, four delay elements D
Any one of 1 to D4 is activated, but two or more may be activated. In this case, each delay element D1
The delay amount of D4 may be the same. This also applies to the following examples. [Embodiment 2] FIG. 8 is a block diagram showing structures of a decoder and a phase control circuit in an analog-digital mixed type semiconductor integrated circuit device according to a second embodiment of the present invention.

As shown in FIG. 8, the phase control circuit 40 includes four delay elements D5 to D5 connected in series with each other.
Including D8. Further, these delay elements D5 to D8 are respectively provided with two inverters I3 and I4, I5 and I2.
6, I7 and I8 or I9 and I10 and two switching elements S1 and * S1, S2 and * S
2, S3 and * S3, S4 and * S4.

The decoder 42 receives the applied code signal X
1 and X2 are logically operated, and the result is a control signal Y1,
Output as * Y1 to Y4 and * Y4.

Table 2 below is a truth table showing the relationship between the code signals X1 and X2 and the control signals Y1 to Y4.

[0058]

[Table 2]

As is clear from Table 2, the decoder 4
2 to the code signals X1 and X2, the corresponding control signals Y1, * Y1 to Y4 and * Y4 are transmitted to the decoder 4
It is output from 2. Switching elements S1, * S1 to S
4, * S4 are the control signals Y1, * Y1 to Y4, * Y.
Turn on or off in response to 4. Here, an asterisk (*) before a signal indicates that the signal has a negative logic (active state when it is at "L" level).

Therefore, the switching elements S1 to S4
And the switching elements * S1 to S4 are alternately turned on or off, the effective number of inverters forming the phase control circuit 40 changes, and the entire delay time changes.

As described above, the phase shift element may be composed of a delay element composed of a logic circuit such as an inverter.

In the second embodiment, inverters I4, I6, I8, I10 and switching elements *
Instead of 1, * S2, * S3, * S4, a tristate buffer may be used. In addition, the inverter I
A resistor may be used instead of 3 to I10. The same applies to the following examples. [Third Embodiment] FIG. 9 is a block diagram showing structures of a phase control circuit and a decoder of a semiconductor integrated circuit device according to a third embodiment of the present invention.

As shown in FIG. 9, the phase control circuit 44 includes four delay elements D9 to D9 connected in series.
Including D12. Furthermore, these delay displays D9 to D12
Is one inverter I4, I6, I8, I10 and 2
It includes two switching elements S1, * S1 to S4, * S4.

This phase control circuit 44 is equivalent to the phase control circuit 40 shown in FIG. 8 with inverters I3, I5, I7 and I9 removed. In the drawings, the parts denoted by the same reference numerals indicate the same or corresponding parts, and the same applies to the following drawings. [Fourth Embodiment] FIG. 10 is a block diagram showing structures of a phase control circuit and a decoder of a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

As shown in FIG. 10, the phase control circuit 46 includes four inverters I11 to I14, four switching elements S1 to S4, a capacitor C1 and an inverter I15.

In this embodiment, one inverter I11
To I14, the switching elements S1 to S4 connected in series thereto, and the capacitor C1 form one delay element. The size of the final-stage transistors inside the inverters I11 to I14 is different,
The driving capability of I14 is different. Therefore, each inverter I
The time constants of the RC circuits composed of the output impedances of 11 to I14 and the capacitance C1 are different, and the delay times of the respective delay elements are all different.

According to the phase control circuit 46, any of the switching elements S1 to S4 is turned on in response to the control signals Y1 to Y4 from the decoder 18 and various delay times are realized.

The inverter I15 at the final stage of the phase control circuit 46 performs waveform shaping and may be omitted. Since the decoder 18 is the same as that shown in FIG. 2, its truth table is also the same as that shown in Table 1. Further, the capacitor C1 may be composed of a stray capacitance.

According to this embodiment, the number of elements is smaller than that of the above-mentioned second and third embodiments. [Fifth Embodiment] FIG. 11 is a circuit diagram showing a structure of a phase control circuit in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

As shown in FIG. 11, this phase control circuit 48 includes three inverters I16 to I18, two switching elements S1 and S2, a capacitor C1 and an inverter I15.

In this embodiment, one inverter I16
No switching element is connected to this inverter, and this inverter I16 always delays the first clock signal CLK1. As in the fourth embodiment, the drive capability of each of the inverters I16 to I18 is different.

According to this embodiment, the number of elements is further reduced as compared with the above-mentioned fourth embodiment. Further, since there are two switching elements S1 and S2, the code signals (for example, binary signals) X1 and X2 can be used as they are, and a decoder is not necessary. [Sixth Embodiment] FIG. 12 is a circuit diagram showing a structure of a phase control circuit in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

As shown in FIG. 12, this phase control circuit 50 includes an inverter 52 capable of changing the output impedance, a capacitor C1 and an inverter I15.

Further, the inverter 52 has an N channel MOS transistor Q3 connected to its input / output terminal.
And P channel MOS transistor Q4, and further includes three N channel MOS transistors Q5 to Q7 and P channel MOS transistors Q8 to Q10 connected to respective sources of transistors Q3 and Q4.

The sizes of these three transistors Q5 to Q7 or Q8 to Q10 are different, and the drain resistances of the respective transistors are different.

Therefore, the output impedance of the inverter 52 can be changed by applying the code signals X1, X2 or * X1, * X2 to the gates of the transistors Q6, Q7 or Q9, Q10. Therefore, the time constant of the RC circuit composed of the output impedance of the inverter 52 and the capacitance C1 can be changed, and as a result, the phase control circuit 50 can be changed.
Can have a different delay time.

In this embodiment, a negative logic code signal * X
Although an inverter for generating 1 and * X2 is required, the number of elements is further reduced as compared with the fifth embodiment described above. [Embodiment 7] In the second to sixth embodiments, the gate delay is basically used. Therefore, if a large delay time is to be generated, the size of the transistor becomes large and the inverter becomes large. There is a problem that the number of

FIG. 13 is a block diagram showing a structure of the phase control circuit 54 and the decoder 18 in the semiconductor integrated circuit device according to the seventh embodiment of the present invention for solving this problem.

As shown in FIG. 13, the phase control circuit 54 includes an inverter I19 having a very small driving capability.
, A capacitor C2, four inverters I20 to I23 having different logic thresholds, and four switching elements S1 to S
4 and an inverter I15.

According to the phase control circuit 54, the first clock signal CLK1 becomes dull due to the inverter I19 and the capacitance C2, and the voltage V _A becomes as shown in FIG. Since the four inverters I20 to I23 have different logic threshold values, the respective inverters I20 to I2 are different.
As shown in FIG. 14, the output voltages V _B , V _C , V _D and V _E of No. 3 fall and rise at different timings.

In this embodiment, the inverter I2
The logical threshold value becomes lower in the order of 0, I21, I22, I23.

The dull amount of voltage V _A at the output node of inverter I19 depends on the output impedance of inverter I19. Therefore, as shown in FIG. 15, the N channel MOS forming the inverter I19 is formed.
The N-channel MOS transistor Q11 is connected to the sources of the transistor Q3 and the P-channel MOS transistor Q4.
And a P-channel MOS transistor Q12 are connected,
By controlling the voltages Z1 and Z2 applied to the gates of the transistors Q11 and Q12, an arbitrary amount of dullness can be realized. [Embodiment 8] In the seventh embodiment, the inverter I19 is used.
It is difficult to adjust the delay time because the bluntness of the voltage V _A at the output node of is non-linear.

FIG. 16 is a block diagram showing a structure of a phase control circuit and a decoder in a semiconductor integrated circuit device according to an eighth embodiment of the present invention, which is provided to solve this problem.

As shown in FIG. 16, the phase control circuit 56 includes an integrator 58 instead of the inverter I19 and the capacitor C2 of the phase control circuit 54. The integrator 58 is
For example, it is an integrating circuit composed of operational amplifiers or a CR circuit composed of capacitors and resistors.

According to the phase control circuit 56, the output voltage V _A of the integrator 58 is linearized as shown in FIG. 17, so that the delay time can be easily compared with the seventh embodiment. Can be adjusted. In addition, the output voltage V is changed by changing the value of the capacitance or the resistance that configures the integrator 58.
It is also possible to control the slope of the waveform of _A , whereby the delay time of each of the inverters I20 to I23 can be lengthened by a fixed time. [Ninth Embodiment] The seventh and eighth embodiments described above have a problem that the duty ratio changes.

FIG. 18 is a block diagram showing a structure of a phase control circuit and a decoder in a semiconductor integrated circuit device according to a ninth embodiment of the present invention, which is provided to solve such a problem. is there.

As shown in FIG. 18, this phase control circuit 60 further includes, in addition to the phase control circuit 56 described above,
Inverters I24 and I25 and OR gates O1 and O
2, O3, O4, O5 and O6 and AND gate A
5, A6, A7 and A8.

FIG. 19 shows the configuration of this phase control circuit 60.
Output of inverters I20, I21, I22 and I23
Force voltage V_B, V_C, V_DAnd V_EAnd OR gate O
Output voltage of 1, O2, O3, O4, O5 and O6
V_F, V_H, V_K, V_J, V_NAnd V_MAnd AND
Output voltage V of the gates A5, A6, A7 and A8_G，
V_I, V _LAnd V_OIs a time chart showing
It

As shown in the time chart of FIG. 19, according to the phase control circuit 60, the second duty ratio 50%, which is the same as that of the input first clock signal CLK1, is used.
The clock signal CLK2 is obtained. Further, the delay amount of the second clock signal CLK2 can be changed by the decoder 18.

Table 3 below shows each AND when the delay rate when the phase is shifted by 180 ° is 100%.
Output voltages V _G , V of the gates A5, A6, A7 and A8
_I, representing the delay rate and the duty ratio of the V _L and V _O.

[0091]

[Table 3]

Here, in the case of shifting the phase between 180 ° and 360 °, the same circuit as the phase control circuit 60 may be constructed by utilizing the inverted signal * CLK1 of the first clock signal CLK1. .

The range in which the delay time is changed is determined at the design stage. In the above embodiments, four types of delay elements having different delay times are used. However, the number of delay elements,
And the delay time is appropriately determined. [Embodiment 10] FIG. 20 is a block diagram showing a tenth embodiment of a semiconductor integrated circuit device according to the present invention.

As shown in FIG. 20, the semiconductor integrated circuit device 62 includes a digital circuit 12 and an analog circuit 1.
4, a phase control circuit 16, and a decoder 18. The tenth embodiment differs from the first embodiment in that the clock signal input to the analog circuit 14 is delayed in comparison with the clock signal input to the digital circuit 12 in the first embodiment. In the tenth embodiment, the phase of the first clock signal CLK1 input to the digital circuit 12 is delayed relative to the phase of the second clock signal CLK2 input to the analog circuit 14.

The phase control circuit 16 delays the second clock signal CLK2 applied to the clock signal input terminal 20 by a fixed time and delays it by the first clock signal CLK.
Output as 1.

As is apparent from this embodiment, the clock signal whose phase is delayed may be the clock signal input to either the analog circuit or the digital circuit. [Eleventh Embodiment] FIG. 21 is a block diagram showing a structure of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

As shown in FIG. 21, the semiconductor integrated circuit device 64 includes a digital circuit 12 and an analog circuit 1.
4, first and second phase control circuits 16a and 16
b, and decoder 18. The eleventh embodiment differs from the first and tenth embodiments in that both the first clock signal CLK1 input to the digital circuit 12 and the second clock signal CLK2 input to the analog circuit 14 are delayed. It's about to come. That is, the reference clock signal CLK0 applied to the clock signal input terminal 20 is delayed by the first phase control circuit 16a for a fixed time and is output as the first clock signal CLK1.
The second phase control circuit 16b delays the signal by a predetermined time and outputs it as the second clock signal CLK2. The delay time of the first and second phase control circuits 16a and 16b is controlled by the control signal X from the decoder 18.

As is apparent from this embodiment, the phases of the first and second clock signals CLK1 and CLK2 are delayed by different times so that the phases thereof are relatively shifted by a constant amount. Good. [Embodiment 12] FIG. 22 is a block diagram showing a structure of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

As shown in FIG. 22, the semiconductor integrated circuit device 66 includes a digital circuit 12 and an analog circuit 1.
4, a phase control circuit 16, and a decoder 18.

The twelfth embodiment differs from the first to third embodiments in that the analog circuit 14 is not controlled by a clock signal. The analog circuit 14 processes an analog input signal from the input terminal 68 and outputs the result as an analog output signal to the output terminal 7
Output from 0 to the outside.

In this case, since the analog circuit 14 is not controlled by the clock signal, the digital circuit 12
Although it may be considered that the interference due to noise from can not be reduced, when the analog output signal is input to the external analog circuit controlled by the clock signal,
Optimizing the performance of the external analog circuit by shifting the phase of the second clock signal CLK2 input to the external analog circuit and the phase of the first clock signal CLK1 input to the digital circuit 12. Can be converted.

As described above, even if the analog circuit formed on the same substrate as the digital circuit does not operate based on the clock signal, the external analog circuit connected to the analog circuit is controlled by the clock signal. In this case, by relatively shifting the phases of the clock signals, it is possible to minimize the influence of noise that the digital circuit has on the analog circuit.

[0103]

A semiconductor integrated circuit device according to the present invention includes a first clock signal for controlling a digital circuit,
A plurality of phase shift elements capable of relatively shifting the phase with respect to the second clock signal for controlling the analog circuit are prepared in advance, and one of the phase shift elements is activated to make the phase relative to each other. Since it is configured to shift by a fixed amount, it is possible to minimize the influence of noise between the digital circuit and the analog circuit in the analog-digital mixed type semiconductor integrated circuit device of any configuration. Therefore, the performance of those circuits can always be optimized.

On the other hand, in the method of manufacturing the semiconductor integrated circuit device according to the present invention, the phases of the first clock signal for controlling the digital circuit and the second clock signal for controlling the analog circuit are relatively shifted. Since a plurality of phase shift elements to be obtained are formed in advance, the phase shift element that minimizes the influence of noise between the digital circuit and the analog circuit is searched from the phase shift elements, and the phase shift element is fixed. A semiconductor integrated circuit device in which a circuit and an analog circuit always operate optimally can be manufactured very easily.

Further, in the method of manufacturing a semiconductor integrated circuit device according to the present invention, a phase shift element having an optimum phase shift amount is searched for in the trial production stage, and the searched phase shift element is fixed in the mass production stage. Since multiple phase shift elements are formed, it is only necessary to revise the mask at least once when shifting from the trial production stage to the mass production stage, and it is extremely easy to use the clock signal for controlling the digital circuit and the analog circuit. It is possible to manufacture an analog-digital mixed type semiconductor integrated circuit device in which the phase is optimally shifted.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.

2 is a circuit diagram showing a specific configuration of a phase control circuit and a decoder of the semiconductor integrated circuit device shown in FIG.

FIG. 3 is a block diagram illustrating a method of finding a delay element having an optimum delay time in the method of manufacturing a semiconductor integrated circuit device according to the first embodiment of the present invention.

4 is a circuit diagram showing a decoder and a phase control circuit in a state where a delay element having an optimum delay time is activated in the semiconductor integrated circuit device shown in FIGS. 1 and 2. FIG.

5 is a plan view showing a specific configuration of the inverter shown in FIGS. 2 and 4. FIG.

6 is a circuit diagram of the inverter shown in FIG.

FIG. 7 is a plan view showing a state in which the wiring pattern of the inverter shown in FIG. 5 is changed to a wiring pattern for mass production.

FIG. 8 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 10 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a phase control circuit in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a phase control circuit in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 13 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to a seventh embodiment of the present invention.

FIG. 14 is a time chart showing the operation of the phase control circuit shown in FIG.

15 is a circuit diagram showing a specific configuration of an input stage inverter that constitutes the phase control circuit shown in FIG.

FIG. 16 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to an eighth embodiment of the present invention.

17 is a time chart showing an operation of the phase control circuit shown in FIG.

FIG. 18 is a block diagram showing a phase control circuit and a decoder in a semiconductor integrated circuit device according to a ninth embodiment of the present invention.

19 is a time chart showing an operation of the phase control circuit shown in FIG.

FIG. 20 is a block diagram showing the structure of a semiconductor integrated circuit device according to a tenth embodiment of the present invention.

FIG. 21 is a block diagram showing the structure of a semiconductor integrated circuit device according to an eleventh embodiment of the present invention.

FIG. 22 is a block diagram showing the structure of a semiconductor integrated circuit device according to a twelfth embodiment of the present invention.

FIG. 23 is a block diagram showing an example of a conventional analog-digital mixed type semiconductor integrated circuit device.

FIG. 24 is a timing chart for explaining the operation of the semiconductor integrated circuit device shown in FIG. 23.

FIG. 25 is a block diagram showing another example of a conventional analog-digital mixed type semiconductor integrated circuit device.

[Explanation of symbols]

10, 62, 64, 66 semiconductor integrated circuit device 12 digital circuit 14 analog circuit 16, 16a, 16b, 40, 44, 46, 48, 5
0, 54, 56, 60 Phase control circuit 18, 42 Decoder CLK1 First clock signal CLK2 Second clock signal X1 to Xk Code signal D1 to D4 Delay element R1 to R4 Resistance

Claims (4)

[Claims] 1. A semiconductor integrated circuit device, comprising: a semiconductor substrate; a digital circuit formed on the semiconductor substrate and operating based on a first clock signal; and formed on the semiconductor substrate. An analog circuit that operates based on a second clock signal having the same cycle as the first clock signal; and a plurality of phase shift elements that can relatively shift the phases of the first and second clock signals, By activating one of those phase shift elements,
A semiconductor integrated circuit device, comprising: a phase control unit that relatively shifts the phases of the first and second clock signals by a fixed amount. 2. The semiconductor integrated circuit device according to claim 1, further comprising decoding means for activating any one of said phase shift elements based on a given code signal. 3. A semiconductor substrate, a digital circuit formed on the semiconductor substrate and operating on the basis of a first clock signal, and a digital circuit formed on the semiconductor substrate, the same as the first clock signal. A method of manufacturing a semiconductor integrated circuit device, comprising: an analog circuit that operates based on a second clock signal of a cycle, wherein the phases of the first and second clock signals are relatively arranged on the semiconductor substrate. Forming a plurality of shiftable phase shift elements, and finding out which one of the phase shift elements is activated to minimize the effect of noise between the digital circuit and the analog circuit, The phase shift element found is replaced with the first and second phase shift elements.
And a step of fixing the clock signal so that it can be activated so that the phase of the clock signal is relatively shifted. 4. A semiconductor substrate, a digital circuit formed on the semiconductor substrate and operating based on a first clock signal, and a digital circuit formed on the semiconductor substrate, the same as the first clock signal. A method of manufacturing a semiconductor integrated circuit device, comprising: an analog circuit that operates based on a second clock signal of a cycle, including a prototype stage and a mass production stage, wherein the prototype stage further comprises: Forming a plurality of phase shift elements capable of relatively shifting the phases of the first and second clock signals, and which of the phase shift elements is activated, the digital circuit and the analog circuit Between the first and the first and second phase shift elements, wherein the mass production step further comprises: Two
2. A method of manufacturing a semiconductor integrated circuit device, comprising the step of forming the plurality of phase shift elements in a fixed state so as to be activated so that the phase of the clock signal is relatively shifted.