JPH0628246A - Storage device - Google Patents
Storage deviceInfo
- Publication number
- JPH0628246A JPH0628246A JP3150760A JP15076091A JPH0628246A JP H0628246 A JPH0628246 A JP H0628246A JP 3150760 A JP3150760 A JP 3150760A JP 15076091 A JP15076091 A JP 15076091A JP H0628246 A JPH0628246 A JP H0628246A
- Authority
- JP
- Japan
- Prior art keywords
- storage unit
- speed
- data
- storage
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Memory System (AREA)
- Dram (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は記憶装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device.
【0002】[0002]
【従来の技術】従来、この種の記憶装置は、高速記憶部
をまったく持たないかまたは記憶部全てが高速なもので
構成されていた。2. Description of the Related Art Heretofore, a storage device of this type has no high-speed storage part at all or has a high-speed storage part.
【0003】[0003]
【発明が解決しようとする課題】上述した従来の記憶装
置は、高速記憶部を持たない場合は使用頻度の高いデー
タについても高速アクセスする手段がないため全体の処
理速度のネックとなり、また、全ての記憶部を高速なも
ので構成した場合、記憶容量が大きくとれずコストも高
くなるという欠点がある。The above-mentioned conventional storage device, if it does not have a high-speed storage unit, has no means for high-speed access even for frequently used data, which is a bottleneck in the overall processing speed. If the storage unit is configured with a high-speed storage unit, there is a drawback that the storage capacity cannot be large and the cost is high.
【0004】[0004]
【課題を解決するための手段】本発明の記憶装置は、通
常の記憶部に加えて高速記憶部と、記憶制御部を有し、
更に記憶制御部内に高速記憶部のアドレス割り付けのた
めの割り付け設定手段と、アドレス変換手段と、通常の
記憶部と高速記憶部間のデータ転送を行うデータ転送手
段と、各データに対するアクセス回数をカウントするカ
ウント手段と、アクセス回数設定手段と、カウント値と
設定アクセス回数の比較手段と、前記データ転送をリフ
レッシュ動作に代えてまたは平行して実行するリフレッ
シュ制御手段を有している。A storage device of the present invention has a high-speed storage portion and a storage control portion in addition to an ordinary storage portion,
Further, in the storage control unit, allocation setting means for address allocation of the high-speed storage portion, address conversion means, data transfer means for transferring data between the normal storage portion and the high-speed storage portion, and the number of accesses to each data are counted. It has a counting means, an access number setting means, a count value and a set access number comparing means, and a refresh control means for executing the data transfer instead of or in parallel with the refresh operation.
【0005】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の一実施例を示すブロック図である。
記憶制御部10において、プロセッサからのリクエスト
/コマンド,アドレス,データを入力端子1,3,4か
らそれぞれ取り込むとリクエスト受付回路11は、タイ
ミング制御回路12、アドレス制御回路16、データ制
御回路17へ制御信号を出力し、コマンドに応じた書込
み/読出し動作を高速記憶部30または記憶部40に対
して実行する。プロセッサからのアクセス頻度の高いデ
ータを高速記憶部30へ格納することにより処理速度が
向上するため、あらかじめ使用頻度の高いアドレス領域
が判明している場合には、入力端子2からアドレス割り
付け情報を割り付け設定回路13へ入力する。アドレス
変換回路16は割り付け設定回路13からの設定を保持
し、高速記憶部30のアドレス内に使用頻度の高いアド
レス領域を変換する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.
When the storage controller 10 fetches requests / commands, addresses, and data from the processor from the input terminals 1, 3, and 4, the request acceptance circuit 11 controls the timing control circuit 12, the address control circuit 16, and the data control circuit 17. A signal is output, and the write / read operation according to the command is executed on the high-speed storage unit 30 or the storage unit 40. Since the processing speed is improved by storing the data frequently accessed by the processor in the high-speed storage unit 30, when the frequently used address area is known in advance, the address allocation information is allocated from the input terminal 2. Input to the setting circuit 13. The address conversion circuit 16 holds the setting from the allocation setting circuit 13 and converts the frequently used address area into the address of the high speed storage unit 30.
【0006】プロセッサからの書込時にデータごとの使
用頻度が判明している場合には、プロセッサ側からデー
タと同期して送られる割り付け情報を入力端子2から割
り付け設定回路13へ取り込む。割り付け設定回路13
はアドレス変換回路15,リクエスト受付け回路11へ
それぞれ制御信号を出力する。アドレス変換回路16は
割り付け設定回路15からの出力によりアドレスを高速
記憶部30のアドレスに変換し、また、リクエスト受付
回路11はタイミング制御回路12,アドレス制御回路
16,データ制御回路17を制御して高速記憶部30へ
の書込みを実行する。When the frequency of use for each data is known at the time of writing from the processor, allocation information sent from the processor side in synchronization with the data is fetched from the input terminal 2 to the allocation setting circuit 13. Allocation setting circuit 13
Outputs control signals to the address conversion circuit 15 and the request acceptance circuit 11, respectively. The address conversion circuit 16 converts the address into the address of the high speed storage unit 30 by the output from the allocation setting circuit 15, and the request reception circuit 11 controls the timing control circuit 12, the address control circuit 16 and the data control circuit 17. Writing to the high speed storage unit 30 is executed.
【0007】この時アドレス変換回路16は変換したア
ドレス情報を割り付け設定回路13が解除するまで保持
する。また、読出し後、データの使用頻度が下がること
が判明している場合には、読出し時のリクエストと同期
してプロセッサ側から割り付け解除情報を入力端子2を
介して割り付け設定回路13へ入力する。割り付け設定
回路13は、アドレス変換回路15の該当するアドレス
を変換対象から解除し、またリクエスト受付け回路11
を介してタイミング制御回路12,アドレス制御16,
データ制御回路17を制御し高速記憶部30から入出力
端子5を介したプロセッサへの読出しデータの転送及び
高速記憶部30から読出したデータの記憶部40への移
動を行う。At this time, the address conversion circuit 16 holds the converted address information until the allocation setting circuit 13 releases it. Further, when it is known that the frequency of use of the data decreases after the reading, the allocation cancellation information is input from the processor side to the allocation setting circuit 13 via the input terminal 2 in synchronization with the request at the time of reading. The allocation setting circuit 13 releases the corresponding address of the address conversion circuit 15 from the conversion target, and the request reception circuit 11
Via the timing control circuit 12, the address control 16,
The data control circuit 17 is controlled to transfer read data from the high speed storage unit 30 to the processor via the input / output terminal 5 and move the data read from the high speed storage unit 30 to the storage unit 40.
【0008】プロセッサからのアクセスと非同期に各デ
ータの高速記憶部30への設定・解除を行う場合、デー
タごとの割り付け解除情報を入力端子2を介して割り付
け設定回路13へ取り込む。割り付け設定回路13はリ
クエスト受付け回路11へ高速記憶部30と記憶部40
とのデータ移動を起動する。When setting / releasing each data to / from the high-speed storage unit 30 asynchronously with the access from the processor, the allocation release information for each data is fetched into the allocation setting circuit 13 via the input terminal 2. The allocation setting circuit 13 sends the request receiving circuit 11 to the high-speed storage unit 30 and the storage unit 40.
Start data movement with.
【0009】リクエスト受付け回路11は、タイミング
制御回路12,アドレス制御回路16,データ制御回路
17を制御して、設定の場合には記憶部40からのデー
タの読出し及び高速記憶部30へのデータの書込みを行
い、設定解除の場合は高速記憶部30からデータの読出
し及び記憶部40へのデータの書込みを行う。また、割
り付け設定回路13は、アドレス変換回路15の該当ア
ドレスの変換情報のクリアを行う。The request accepting circuit 11 controls the timing control circuit 12, the address control circuit 16 and the data control circuit 17 to read out data from the storage unit 40 and transfer data to the high-speed storage unit 30 when set. Writing is performed, and when the setting is released, data is read from the high speed storage unit 30 and data is written to the storage unit 40. The allocation setting circuit 13 also clears the conversion information of the corresponding address in the address conversion circuit 15.
【0010】高速記憶部30を効率的に使うためには、
実際の使用頻度に応じたデータの格納が必要であり、か
つ、その設定の負担からプロセッサを解放するため本装
置内でダイナミックに高速記憶部30と記憶部40間の
データ移動をする必要がある。そのため、各データまた
はアドレス領域に対して一定期間内のアクセス頻度をカ
ウント回路18で監視する。入力端子5からアクセス回
数設定回路20へ設定した一定期間内の基準アクセス回
数とカウント回路18の各カウント値を比較回路19で
比較し一定期間内のカウント数が基準アクセス回数を越
えた場合比較回路19から割り付け設定回路13へ出力
信号を出力する。In order to use the high speed storage section 30 efficiently,
It is necessary to store data according to the actual frequency of use, and to dynamically move data between the high-speed storage unit 30 and the storage unit 40 in this device in order to release the processor from the burden of the setting. . Therefore, the count circuit 18 monitors the access frequency of each data or address area within a certain period. When the reference access count set in the access count setting circuit 20 from the input terminal 5 and each count value of the count circuit 18 are compared by the comparison circuit 19, and the count count in the fixed period exceeds the reference access count, the comparison circuit An output signal is output from 19 to the allocation setting circuit 13.
【0011】該当データまたはアドレス領域が記憶部4
0上に有る場合には、割り付け設定回路13は該当デー
タまたはアドレス領域の高速記憶部30へのデータ移動
のためリクエスト受付け回路11を起動し、また、アド
レス割り付けの設定をアドレス変換回路に対して行う。
また、高速記憶部30上に割り付けられた各データまた
はアドレス領域へのアクセスが基準アクセス回数以下の
場合、比較回路19は割り付け設定回路13へ出力し、
割り付け設定回路13はアドレス変換回路15への設定
解除及びリクエスト受付け回路11への高速記憶部30
から記憶部40へのデータ移動の起動を出力する。これ
により使用頻度の高いデータまたはアドレス領域が高速
記憶部へ割り付けられる状態が保たれる。The corresponding data or address area is the storage unit 4.
If it is above 0, the allocation setting circuit 13 activates the request acceptance circuit 11 to move the data or the address area to the high-speed storage unit 30, and sets the address allocation to the address conversion circuit. To do.
Further, when the access to each data or address area allocated on the high-speed storage unit 30 is less than or equal to the reference access frequency, the comparison circuit 19 outputs to the allocation setting circuit 13,
The allocation setting circuit 13 releases the setting to the address conversion circuit 15 and the high-speed storage unit 30 to the request receiving circuit 11.
To activate storage of data from the storage unit 40 to the storage unit 40. As a result, a state in which frequently used data or address areas are allocated to the high speed storage unit is maintained.
【0012】上記データ移動がプロセッサのアクセスと
競合するのを避けるための各記憶部の未使用期間に行わ
れることが必要である。記憶部に使用される記憶素子が
ダイナミックランダムアクセスメモリ(DRAM)の場
合には、一定期間ごとにリフレッシュ動作を行うことが
必要であり、上記データ移動が発生した場合、割り付け
制御回路13からリフレッシュ制御回路14へ制御信号
を出力してリフレッシュ実行時間にリフレッシュ動作の
代りまたはリフレッシュと平行して上記データ転送を行
うことによりプロセッサとのアクセス競合を回避するこ
とができる。It is necessary to perform the above-mentioned data movement during the unused period of each storage unit in order to avoid conflict with access by the processor. If the storage element used in the storage unit is a dynamic random access memory (DRAM), it is necessary to perform a refresh operation at regular intervals, and when the above data movement occurs, the allocation control circuit 13 performs refresh control. By outputting the control signal to the circuit 14 and performing the data transfer instead of the refresh operation or in parallel with the refresh operation at the refresh execution time, access conflict with the processor can be avoided.
【0013】[0013]
【発明の効果】以上説明したように本発明は、通常の大
容量の記憶部と比較的小容量の高速記憶部とを持ち、記
憶制御部が使用頻度の高いデータを高速記憶部内に置く
ことにより、高速記憶部の使用効率を高め装置の記憶容
量を小さくすることなく比較的低コストに高速アクセス
を行う記憶装置を実現できる効果がある。As described above, the present invention has a normal large-capacity storage unit and a relatively small-capacity high-speed storage unit, and the storage control unit places frequently used data in the high-speed storage unit. As a result, there is an effect that it is possible to realize a storage device that performs high-speed access at a relatively low cost without increasing the use efficiency of the high-speed storage unit and reducing the storage capacity of the device.
【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.
1〜6 入出力端子 10 記憶制御部 11 リクエスト受付回路 12 タイミング制御回路 13 優先度設定回路 14 リフレッシュ制御回路 15 割り付け設定回路 16 アドレス変換回路 17 アドレス制御回路 18 データ制御回路 19 カウント回路 20 アクセス回数設定回路 21 比較回路 30 高速記憶部 40 記憶部 1 to 6 input / output terminals 10 storage control unit 11 request reception circuit 12 timing control circuit 13 priority setting circuit 14 refresh control circuit 15 allocation setting circuit 16 address conversion circuit 17 address control circuit 18 data control circuit 19 count circuit 20 access count setting Circuit 21 Comparison circuit 30 High-speed storage unit 40 Storage unit
Claims (7)
スが可能な高速記憶部と、前記記憶部及び前記高速記憶
部の制御を行う記憶制御部を有することを特徴とする記
憶装置。1. A storage device comprising an ordinary storage unit, a small-capacity high-speed storage unit that can be accessed at high speed, and a storage control unit that controls the storage unit and the high-speed storage unit.
装置内の任意のアドレスに割り付けるアドレス変換手段
と、アドレス変換のための設定を行う割り付け設定手段
を有する請求項1記載の記憶装置。2. The storage device according to claim 1, wherein the storage control unit has address conversion means for allocating the high-speed storage part to an arbitrary address in the storage device, and allocation setting means for making settings for address conversion. .
ータの前記高速記憶部への割り付け・設定・解除を行
い、また、通常の記憶部と高速記憶部間のデータ転送を
行うデータ転送手段を有する請求項2記載の記憶装置。3. The data transfer means for allocating / setting / releasing individual stored data to / from the high-speed storage unit, and the data transfer unit for transferring data between the normal storage unit and the high-speed storage unit. The storage device according to claim 2, further comprising:
出し動作に同期して割り付けの設定・解除を行う請求項
3記載の記憶装置。4. The storage device according to claim 3, wherein the allocation setting means performs allocation setting / cancellation in synchronization with a write or read operation.
出し動作に非同期に割り付けの設定・解除を行う請求項
3記載の記憶装置。5. The storage device according to claim 3, wherein the allocation setting means performs allocation setting / cancellation asynchronously with writing and reading operations.
各データに対して一定期間内のアクセス回数をカウント
するカウンタと、前記カウンタのカウント値と設定され
たアクセス回数の比較を行う比較手段と、前記比較手段
で前記カウント値と比較するアクセス回数を設定するア
クセス回数設定手段を有し、前記比較手段における比較
結果から前記割り付け設定手段が割り付けの設定及び解
除を行う請求項4または5記載の記憶装置。6. The storage control unit compares a counter that counts the number of times of access to each data stored in each storage unit within a certain period, and a comparison that compares the count value of the counter with the set number of accesses. 6. An access number setting means for setting an access number for comparing with the count value by the comparing means, wherein the allocation setting means sets and cancels the allocation based on a comparison result of the comparing means. The storage device described.
解除時高速記憶部から通常の記憶部へのデータ転送をリ
フレッシュ動作時にリフレッシュ動作に代えてまたは平
行して実行するためのリフレッシュ制御手段を有し、前
記データ転送とプロセッサからのアクセスとの競合を避
ける請求項4,5または6記載の記憶装置。7. The storage control unit includes refresh control means for executing data transfer from the high-speed storage unit to the normal storage unit at the time of setting and releasing allocation, instead of or in parallel with the refresh operation during the refresh operation. 7. The storage device according to claim 4, wherein the storage device has contention to avoid contention between the data transfer and an access from a processor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3150760A JPH0628246A (en) | 1991-06-24 | 1991-06-24 | Storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3150760A JPH0628246A (en) | 1991-06-24 | 1991-06-24 | Storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0628246A true JPH0628246A (en) | 1994-02-04 |
Family
ID=15503818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3150760A Pending JPH0628246A (en) | 1991-06-24 | 1991-06-24 | Storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0628246A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6393520B2 (en) | 1997-04-17 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Data processor and data processing system with internal memories |
JP2006059403A (en) * | 2004-08-18 | 2006-03-02 | Nec Micro Systems Ltd | Semiconductor device and refresh processing method of the device |
JP2009048613A (en) * | 2007-08-14 | 2009-03-05 | Samsung Electronics Co Ltd | Solid state memory, computer system including the same, and its operation method |
JP2011164669A (en) * | 2010-02-04 | 2011-08-25 | Nec Corp | System and method for control of memory access |
US8010739B2 (en) | 2007-09-28 | 2011-08-30 | Denso Corporation | Electronic device and program for operating the same |
US8023012B2 (en) | 2004-08-23 | 2011-09-20 | Fujifilm Corporation | Image capture device correcting defective pixel information |
JP2014182674A (en) * | 2013-03-21 | 2014-09-29 | Nec Corp | Storage device and storage method |
-
1991
- 1991-06-24 JP JP3150760A patent/JPH0628246A/en active Pending
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6393520B2 (en) | 1997-04-17 | 2002-05-21 | Matsushita Electric Industrial Co., Ltd. | Data processor and data processing system with internal memories |
JP2006059403A (en) * | 2004-08-18 | 2006-03-02 | Nec Micro Systems Ltd | Semiconductor device and refresh processing method of the device |
US8023012B2 (en) | 2004-08-23 | 2011-09-20 | Fujifilm Corporation | Image capture device correcting defective pixel information |
JP2009048613A (en) * | 2007-08-14 | 2009-03-05 | Samsung Electronics Co Ltd | Solid state memory, computer system including the same, and its operation method |
US8626996B2 (en) | 2007-08-14 | 2014-01-07 | Samsung Electronics Co., Ltd. | Solid state memory (SSM), computer system including an SSM, and method of operating an SSM |
KR101498673B1 (en) * | 2007-08-14 | 2015-03-09 | 삼성전자주식회사 | Solid state drive, data storing method thereof, and computing system including the same |
US9208079B2 (en) | 2007-08-14 | 2015-12-08 | Samsung Electronics Co., Ltd. | Solid state memory (SSM), computer system including an SSM, and method of operating an SSM |
US8010739B2 (en) | 2007-09-28 | 2011-08-30 | Denso Corporation | Electronic device and program for operating the same |
JP2011164669A (en) * | 2010-02-04 | 2011-08-25 | Nec Corp | System and method for control of memory access |
JP2014182674A (en) * | 2013-03-21 | 2014-09-29 | Nec Corp | Storage device and storage method |
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