JPH06274571A - Automatic wiring processing system in printed board design supporting system - Google Patents

Abstract

PURPOSE:To provide an efficient wiring pattern by changing viaholes registered in a library when wiring among component pins is performed. CONSTITUTION:The inter-component-pin wiring means 10 of a processor 1 first takes out connection information among the component pins from a pattern file 3 and performs the wiring among the component pins from a net with a higher priority order. Then, a viahole pattern layer discrimination means 11 retrieves the library 2 for the viaholes inside the net, discriminates whether or not the registered viahole (registered as a through-viahole) is present and when it is present, discriminates connection conditions wired by the inter- component-pin wiring means 10 and discriminates a layer to be connected by the viahole. By the discrimination, whether the viahole is unnecessary or not or which internal layer is to be connected with a surface layer in the case of using it is discriminated. By the discriminated result, a viahole correction means 12 erases the information of the viahole registered as the through viahole in the library 12 or corrects the internal layer viahole.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic wiring processing method in a printed board design support system. The outline of printed circuit board design is the procedure of specification / function determination, circuit design, and mounting design. Among them, in the mounting setting, a placement process of components on a board and a wiring process between component pins having the same net (automatic wiring and manual wiring correction) are performed.

In recent years, printed boards have become larger and higher in density, and along with this, importance of correctness of automatic wiring processing has been emphasized.

[0003]

2. Description of the Related Art FIG. 5 is an explanatory diagram of functions of a conventional automatic wiring processing program. A of FIG. 4 shows a cross section of a four-layer printed board including L1 to L4 layers for surface mounting. In the figure, 50 is a printed board, 51 and 56 are surface mount components (displayed by SMD), and 52, 53, 57 and 58 are SMD.
The component pins 54, 55 for connecting the terminals of (1) on the surface are vias (VIA). The via is a terminal having a conductor hole between layers for connecting the connection between the pins which cannot be connected on the front surface of the printed board on the inner layer or the back surface, and the via 54 is L3.
The layer 55 and the L4 layer are connected, and the via 55 includes the L2 layer, the L3 layer and the L5 layer.
Connect between the four layers.

In the conventional automatic wiring processing program, A.
SMDs 51, 56 and their respective component pins 52, 53, 57, 58, etc., as shown in FIG. 5, patterns for forming the nets connecting the component arrangements and component pins, and for connecting the layers. It had a function to automatically determine the route of the wiring based on the information showing the placement of the via (structure of the via).

In the process, B. And C.I. The following judgments are made by recognizing such patterns. That is, B. Shows an example of a connection pattern (pattern seen from the upper surface) of a part of the L3 layer of the printed board 50. Since the vias 54 and 55 are connected in this L3 layer, these two vias are arranged. It is determined that another pattern (wiring) cannot be generated at the specified position. In addition, C.I.
In the case of, the example of the connection pattern of the L2 layer of the printed board 50 is shown. In the case of the L2 layer, the via 55 has a connection pattern arranged between it and another via (not shown) in this layer, so that another pattern cannot be connected to this position. However, since the via 54 shown by the dotted line is terminated in the upper L3 layer, it is determined that another pattern can be generated at a position corresponding to the via 54 of the L2 layer, and a necessary wiring pattern is generated. Improve the wiring rate. That is, since the structure of a via is conventionally determined when a pattern is generated, when the other nets are automatically routed, the wiring is performed while determining whether or not the pattern can be generated in each layer at the location where the via is generated.

As described above, in the conventional automatic wiring processing program, each via is arranged between layers (via 54 is between the L4 layer and L3 layer, via 55 is between the L4 layer and L3 layer) as input component arrangement and pattern data. Layer and L2 layer) or through (between the front and back surfaces of L4 layer and L1 layer) is automatically selected, thereby improving the wiring rate. There is. That is, the type of via to be used is determined at the time of automatic wiring, and a function to determine whether or not a pattern is generated in another layer (B. or C. in FIG. 5) at a position where the via is generated corresponding to the structure of the via. have.

[0007]

As described above, in the automatic wiring program, the structure of the via is defined in the component information and pattern data input as the processing target (interlayer connection structure or through connection, etc.). Therefore, it is possible to determine that another pattern can be arranged at the same position on the lower layer if the via is terminated in the upper layer even if the via for interlayer connection is arranged.

However, when an SMD (surface mount component) such as a QPF (Quad Flat Package) having a large number of pins and a narrow pitch between terminals is used, automatic wiring processing is performed with the terminals of the SMD as a direct wiring target. Then, the SM shown in FIG.
The problem shown in the explanatory diagram occurs when the terminal D is directly subjected to automatic wiring. That is, when an SMD terminal having a large number of pins and a narrow pitch between terminals is directly targeted for automatic wiring, as shown in FIG. 8, wiring of other terminals of the same SMD interferes with each other, and There is a problem that a considerable number of terminals cannot be wired.

In order to solve this problem, generally, FIG.
The method of using the line drawing from each terminal of the SMD shown in FIG. This method draws a line from the terminal of the SMD to a location where the automatic wiring processing becomes easy as shown in FIG. 9 and executes a via (displayed by VIA) at that location before executing the automatic wiring processing. , SMD are used as wiring targets instead of the terminals of SMD.

When SMD is used, a pattern and a via are generated from the component pin as a pre-process of automatic wiring in consideration of connection in another layer, and another component pin of the via is automatically routed. is there. At that time, surface mount parts (SM
The work of generating patterns and vias from component pins in D)
The number of pre-processing work steps is reduced by registering the SMD, the pattern to be connected to the SMD, and the vias collectively in the library instead of performing each design.

FIG. 6 shows an example of patterns registered in the library. In this example, the SMD 63 and each component pin 6
2, 6 and vias 6 corresponding to the component pins 62, 64
The patterns 1, 65 are collectively registered in the library as the component data 60.

However, regarding the via 65 registered in the library together with the parts, regardless of the wiring condition,
Since it is defined as a through via in the library, it becomes difficult to wire other nets, which causes a drop in the wire ratio of automatic wiring.

FIG. 7 is an explanatory diagram of a conventional problem. Figure 7
6 shows an example of performing the automatic wiring process when the component data having the pattern shown in FIG. 6 is registered in the library.

Referring to FIG. When two components shown in FIG. 6 are arranged on the printed board 70 as shown in FIG. 6, the vias 65 and 61 corresponding to the component pins 64 and 62 of the SMD 63 are through vias (of the L1 layer to the L4 layer) according to the definition of the library. It is connected to each layer).

In this case, as shown in FIG. Printed board 7 shown in
At the positions of the vias 65 and 61 of the L3 layer of 0, there is a connection pattern and at the same time a through via exists, so it is determined that another pattern cannot be generated. In addition, C.I. In the case of the L2 layer shown in (1), it is determined that another pattern cannot be generated because the connection pattern exists at the position of the via 61, and there is no wiring pattern at the position of the via 65, but another pattern occurs because it is a through via. It is judged that it cannot be done.

It is an object of the present invention to provide an automatic wiring processing method that can change the type of a via or delete a via depending on a connection state even for a via registered in a library.

[0017]

FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, 1 is a processing device, 2 is a pattern for connecting component information and SMD pins, a library in which vias are registered, and 3 is component information obtained by referring to the library 2 and SMD pins are connected. A pattern file 4 in which information such as patterns and vias and arrangement information of components is stored, and 4 is a pattern file after wiring is completed. Also,
In the processing device 1, 10 is a wiring means between component pins, 11
Is a via pattern layer discrimination means, and 12 is a via correction means.

According to the present invention, regarding the vias registered in the library, the connection of the vias registered in the library is judged when the arrangement between the component pins is performed, and it is not necessary to use the through vias or the vias are unnecessary. For these, the installation and structure of vias are modified to generate efficient wiring patterns.

[0019]

In FIG. 1, the inter-component pin wiring means 10 of the processing apparatus 1 first takes out the connection information between the component pins from the pattern file 3 and carries out the wiring between the component pins from the net having the highest priority. Next, the via pattern layer discrimination means 11
Judges whether the via in the net is a registered via (registered as a through via) by searching the library 2 and, if there is, identifies the connection status wired by the component pin wiring means 10. Then, the layer connected by the via is determined. Whether the via is unnecessary by this determination,
Or, if used, identify which inner layer should be connected to the surface layer. Via correction means 12 is determined based on this determination result.
Deletes or corrects the via information registered as a through via in the library 2 into an internal via.

After the via information is corrected in this way, when the wiring between the component pins is performed again in the component-to-component wiring means 10 using the corrected information, it is changed to the inner layer via in which the through via is deleted. This makes it possible to generate an efficient wiring pattern.

[0021]

FIG. 2 is a system configuration diagram in which the present invention is implemented. In FIG. 2, 20 is a CPU, 21 is a memory, and 2
2 is a file input / output unit (displayed by file I / O), 23
Reference numeral to 25 are libraries or files provided in a secondary storage device (magnetic disk device or the like), and 23 is a library in which component information, SMD pin connection patterns and vias (defined as through vias) are registered. , 24 is a pattern file containing component information and SMD pin connection patterns, as well as via information and component placement information, and 25 is a pattern file 24 after completion of wiring in which automatic wiring has been completed and via information has been added to the contents of the pattern file 24. Pattern file.

In the system of FIG. 2, after the automatic processing program is stored in the memory 21, the wiring processing is executed by the CPU 20. FIG. 3 is a processing flow of the embodiment.

First, the via pattern information connected to the component is taken out from the library 23 (S1 in FIG. 3), and the component arrangement information and the connection information between the component pins are taken out from the pattern file 24 (at the same S2). These pieces of information are loaded into the memory 21 via the file I / O 22 of FIG.
Here, wiring for one net (a signal line that is directly connected via a pin without other components) is performed (at step S3).

Next, it is judged whether or not there is a via registered in the library 23 among the routed wires (at step S4). If not, the wiring for the net is ended. Determines whether to connect only in the same layer as the pattern (the pattern on the front surface or the pattern on the back surface on which the components of the printed board are mounted) (S5). Here, if it is found that the connection is made only on the same layer as the pattern on the front surface or the back surface, the via extending to the inner layer of the printed board is not necessary, so the processing for deleting the via is performed (S6 in the same).

In S5, when it is found that the via to be processed is not connected to the pattern (front surface or back surface) only in the same layer, the processing target via is the same layer in the pattern (front surface or back surface) and the inner layer. It is determined whether or not they are connected (at step S7), and in the case of Yes, the via does not need to be a through via, so that the layer is changed to an interlayer via connecting up to the layer at which it is connected (at step S8). The processes of S5 to S8 are sequentially and repeatedly executed for all existing vias. When it is determined that all the vias for one net are finished (see the same S
9) Then, it is judged whether or not all the nets are completed (S1
0) If not finished, wiring is performed for the next one net (at step S3), and the same process is performed for all nets.

FIG. 4 shows a concrete example of a via changing process according to the present invention. A. of FIG. Is an example of via deletion. As shown in Fig. 3, when there are two through vias to be wired, (a) and (b), the via (a) among them is the same layer as the pattern on the front or back surface in S5 of Fig. 3 above. If it is determined that only the vias are connected, the via (a) is deleted as shown because it is unnecessary. By this deletion, other patterns can be generated at the places where the vias (a) of the layers other than the L4 layer were provided, so that the improvement of the wiring rate of the entire printed circuit board can be expected.

Next, referring to FIG. Is an example of via change. In this case, the via (a) is defined as a through via as shown in, but in S7 of FIG. 3 above, it can be seen that the surface pattern layer and the inner layer (L3) are connected. The through via is changed to an interlayer via (a via connecting the L4 layer and the L3 layer on the surface) like. Also in this case, L
Since it is possible to generate another pattern at the location of the via (a) of the second layer and the L1 layer, the wiring rate of the entire printed board can be improved.

[0028]

According to the present invention, by changing the via of the existing wiring registered in the library, the wiring of other nets can be facilitated, and as a result, the wiring rate of the automatic wiring can be improved. Become. In addition, the wiring work time in the unwired section by manual work is reduced, and the number of design steps can be reduced.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a system configuration diagram in which the present invention is implemented.

FIG. 3 is a processing flow of an embodiment.

FIG. 4 is a specific example of a via changing process according to the present invention.

FIG. 5 is an explanatory diagram of functions of a conventional automatic wiring processing program.

FIG. 6 is an example of a pattern registered in a library.

FIG. 7 is an explanatory diagram of a conventional problem.

FIG. 8 is an explanatory diagram of a case where a terminal of an SMD is directly targeted for automatic wiring.

FIG. 9 is an explanatory diagram of a method of using line drawing from each terminal of the SMD.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Processor 10 Wiring means between component pins 11 Via pattern layer discrimination means 12 Via correction means 2 Library 3 Pattern file 4 Pattern file after wiring is completed

Claims (2)

[Claims] 1. A printed circuit board design support system in which a surface mounting component, a pattern connected to a component pin of the component, and a via defined as a through via of the printed circuit board are collectively registered in a library. A pattern file containing wiring patterns including pins and vias and arrangement information of parts on a printed board is provided, and from each connection information of the part pins of the pattern file, between each part pin including connections between layers of the printed board for each net. The wiring process is performed, the presence or absence of vias collectively registered in the library is searched for the wired nets, and the vias are corrected according to the connection state between layers of the printed board. Automatic wiring processing method for printed circuit board design support system. 2. The modification of a via according to claim 1, wherein the via connecting only with the same layer as the front surface or the back surface of the printed circuit board is deleted, and the via connecting the front surface or the back surface layer with the inner layer is connected with a corresponding connection. An automatic wiring processing method in a printed circuit board design support system, characterized by changing to an interlevel via having