JPH06274425A - Network adaptor device - Google Patents

Abstract

PURPOSE:To realize the network adaptor device for realizing an inter-node communication being low in cost, and low in latency. CONSTITUTION:The device consists of a network adaptor for adding a network function to a computer, and is provided with a transmitting FIFO buffer 103 for transmitting data to a network, a receiving FIFO buffer 104 for receiving the data from the network, dual port buffer memories 201, 202 of at least two faces, and a first control means 204 for executing like a pipeline a data transfer from the receiving FIFO buffer 104 to one face of the dual port buffer memory, and a data transfer from the other face to a main storage, at the time of reception. Also, this device is provided with a second control means 204 for executing like a pipeline a data transfer from the main storage to one face of the dual port buffer memory, and a data transfer from the other face to the transmitting FIFO buffer 103, at the time of transmission.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed DMA data transfer system of a network adapter device on each computer in a computer system connected by a network, and more particularly to a transmission request to a network and a reception request from the network. The present invention relates to a network adapter device suitable for realizing a low-latency communication function between nodes when both occur simultaneously.

[0002]

2. Description of the Related Art The trend of constructing a computer system connected by a network by adding a network adapter device to a conventional stand-alone computer has been described.
Ethernet, Token Ring, ARCNET, FD
It is widely known for the development of network adapter devices such as DI (Fiber Distributed Data Interface). Since these network adapter devices basically have a bus type structure, transmission and reception cannot be performed simultaneously on the network. In the bus type network adapter device, the instantaneous network speed may become higher than the effective throughput of the computer due to problems such as communication protocol and I / O bus overhead. It was common to have a large amount of buffer memory. For example, a normal Ethernet adapter device has a buffer memory of 8 kbytes to 64 kbytes on the board, so that the throughput of the computer is effectively matched with the speed of the network. When a complicated function such as a packet filter is actually added to the network device driver, packets may be dropped in the 8 kbyte buffer memory, but packets may not be dropped in 16 kbytes. For this reason, a conventional low-speed CPU,
It has been considered that as the device driver performs more complicated processing using the I / O bus, the capacity of the buffer memory needs to be increased as the network speed increases.

The bus type network adapter device is a unit called a page for data received from the network and data to be transmitted to the network (a typical value is 2 kbytes for Ethernet, 256 or 512 bytes for ARCNET). And the buffer R on the board
It was stored in AM. Then, the device driver performs data transfer between the buffer RAM and the main memory in the transmission / reception interrupt routine. Therefore, in a situation where the receiving process is frequently performed, almost all pages are occupied by the receiving process, and a situation occurs in which no transmission is performed during that time. However, due to the nature of the network, transmission and reception do not occur at the same time, so the need to separate the buffer RAM into a transmission buffer RAM and a reception buffer RAM was not very high.

In a typical Ethernet control LSI, a transmission / reception page area is switched in units of 2 kbytes by externally attaching a single port RAM. See also ARC
The NET control LSI incorporates a dual port RAM and switches the transmission / reception area in units of 256 or 512 bytes. As for ARCNET, please refer to "ARCNET Techni" issued by Toyo Micro Systems Co., Ltd.
cal Manual ”(Japanese translation title is“ ARCN ”
What is ET "), and a detailed specification of a dedicated chip for ARCNET is also described in" ARCNET Controller COM20020 (Japanese version data sheet) "issued by Toyo Micro Systems Co., Ltd.

Along with the bus type network adapter device, a new type of point-to-point type network adapter device will be developed in consideration of application in the field of parallel / distributed data processing system. Has become. HIPPI (High Performance Parallel Int) is being standardized in ANSI X3T9.3.
erface) channel and SC proposed by IEEE
I (Scalable Coherent Interface) is a standard for such a network adapter device. These point-to-point type network adapter devices can simultaneously perform transmission and reception on the network. Therefore, it is possible to secure a high throughput, low latency (delay time), ultra-high speed communication path for connecting a plurality of data processing devices.

The HIPPI and SCI will be briefly described below.

(1) HIPPI channel As one of the high-speed communication paths for connecting a plurality of data processing devices, HIP is being standardized as an interface of standard specifications in ANSI X3T9.3 adapted for high-speed transfer.
PI (High Performance Parallel)
ll Interface) channel. HIP
The PI channel is a channel that is unidirectionally coupled by 4-byte parallel metal signal lines and performs burst transfer from the source node to the destination node.
Performs high throughput data transfer of MB / s.

[0008] The HIPPI channel is a point-to-point simplex communication and is a connection type communication system. Therefore, a communication is established by establishing a connection from a source to a destination. After this, burst transfer of data is performed. As described above, since the HIPPI channel is basically a connection type interface for the channel, a large amount of collected data can be transferred from the source node (super computer etc.) to the destination node (disk array etc.) at high speed. It is not suitable for high speed transfer while switching a small amount of data to different destinations such as transfer between processors of a parallel processing machine.

(2) SCI As another example of a high-speed communication path for connecting a plurality of data processing devices, SCI (Scala) proposed by IEEE
ble Coherent Interface). For SCI,
The standard is IEEE Draft P1569 / D2.
00 18 Nov 91. The SCI is a memory-to-memory network of distributed memory that connects a unidirectional 2-byte parallel data signal line, a 1-bit flag signal, and a clock signal in a ring shape to perform data communication in short data packets of data sizes 16B and 64B. It is an interface and aims to maintain cache memory coherency.

In addition to the HIPPI channel and SCI, the transposer of Inmos is C
A point-to-point network function is implemented by incorporating four channel mechanisms in the PU.
In particular, the T9000 transponder aims to improve latency by using a technique called a virtual channel. Specifically, a built-in virtual channel processor decomposes a logical packet of an arbitrary length into a virtual packet of a maximum length of 32 bytes and transmits / receives it. Thus, MTU (Maximum) of physical packets on the network
Transfer unit size of 32 bytes, Ethernet, token ring, ARCNE
The latency is improved by making the value much smaller than those of T and FDDI. Such an approach is effective for a system in which a memory and a channel are very closely coupled, such as a transputer, but a normal method in which the channel and the memory are coupled via an I / O bus. In the system, DM via I / O bus
Since the number of transfers of A increases, there is an adverse effect that throughput does not increase. For the T9000 Transputer, please refer to "THE T9000 T" issued by Inmos.
RANSPUTER PRODUCTS OVERVI
EW MANUAL ”has a detailed description.

[0011]

However, the RIS
C (Reduced Instruction Set)
As the development of high-speed processors such as Computer processors and the development of high-throughput I / O buses has spurred, the effective throughput of computers has become equal to the speed of the network, and the following new problems have appeared. . That is, the above conventional techniques have the problems listed below.

1. The problem that increasing the capacity of the buffer memory does not contribute to the effective throughput of the computer In the above-mentioned bus type network adapter device, since the single port transmission / reception memory is mainly used as the buffer memory, the effective throughput of the computer is improved. Has a problem that the capacity of the buffer memory must be increased. However, in ARCNET, since a dual port transmission / reception memory is used as the buffer memory, this problem is somewhat alleviated.

On the other hand, in the point-to-point type network adapter device, the FIFO memory is used as the buffer memory, and the MTU size is set to a value smaller than that of the bus type network in order to suppress the increase in the capacity of the buffer memory. Was. Therefore, as in the bus type network adapter device, when the MTU size is increased, the capacity of the FIFO memory must be increased.

Further, in recent years, due to the progress of optical fiber technology, the speeding up of the network is achieved not only by the copy between the buffer memory and the main memory, but also by the increase of the processing time of the copy between the areas inside the main memory, the effective throughput of the computer. It is suggesting that it will be a factor to decrease. That is, there is a new problem that increasing the capacity of the buffer memory does not contribute to the effective throughput of the computer due to factors such as speeding up of the network and complication of communication protocol processing.

2. Latency problem Bus-type network adapter devices such as Ethernet use single-port transmit / receive memory as buffer memory, so data transfer between network and buffer memory and data transfer between host and buffer memory can be performed in parallel. There is a problem that you cannot do it. In order to solve this problem, in ARCNET, a dual port transmission / reception memory is used as a buffer memory, but it is not possible to switch the transmission / reception operation in fine data units only by switching transmission / reception in page units. A delay occurs when switching the operation from transmission to transmission and switching the operation from transmission to reception. That is, there is a latency problem on the network side.

In a bus type network adapter device, there are many configurations in which a transmission process from the main memory to the buffer memory and a reception process from the buffer memory to the main memory are performed in each interrupt processing routine, and one of the processes is completed. If not, there is a problem that the other process cannot be started. Therefore, if there is a request to send data with a relatively small packet length to another network while receiving data with a relatively large packet length, the conventional configuration sends data until reception is complete. Will cause latency problems on the computer side.

In a point-to-point type network adapter device such as HIPPI channel or SCI,
Low latency is realized by using the IFO memory as a buffer memory. In addition, the above T9000
There is no latency problem because the transmission and reception processes can be executed simultaneously by using the transputer's virtual channel technology.
There is a problem that it is difficult to apply it as it is to a system having an O-bus architecture. That is, since the MTU of the T900 transputer is 32 bytes, the transfer unit between the channel and the main memory is also 32 bytes. Therefore, as in the present invention, the I / O of the existing CPU is
When adding a network adapter device to the bus,
The device driver, which is a program for controlling the network adapter device, needs to notify the network adapter device of a transmission / reception command in units of 32 bytes, and the I / O bus is occupied for purposes other than data transfer, which increases latency. There is a problem.

3. Device driver overhead problem The above-mentioned bus type network adapter device allocates a transmission / reception area to a buffer memory in page units in advance, and a buffer on the network device is included in a reception interrupt processing routine and a transmission interrupt processing routine that occur in a plurality of page units. It was usual to transfer data between memory and main memory. For this reason, there is a problem of device driver overhead that interrupt processing occurs frequently and throughput of the computer decreases.

Further, in a HIPPI channel or a point-to-point type network adapter device such as SCI, low latency is realized by using a FIFO memory as a buffer memory, but in order to suppress the capacity of the buffer memory, the MTU is suppressed. There is a problem that the size cannot be increased. For this reason, the number of transfers between the main memory and the network adapter device increases, which causes a problem that the overhead of the device driver is large.

In addition, a network adapter device based on the command chain system has also appeared in order to speed up the processing of the device driver. In such a device, it is necessary to provide a table for storing commands in the main memory so that the device driver and the network adapter device can access the table. As patents relating to exclusive control of shared memory, as disclosed in Japanese Patent Application Laid-Open Nos. 3-138748 and 3-74757, there are a pointer managing a shared memory and a flag bit indicating a busy state of a shared resource. Had to be introduced.

An object of the present invention is to provide a stand-alone computer having a high-performance CPU such as a RISC processor and a high-performance I / O bus with a low-cost, high-throughput, low-latency communication function, and also to a bus-type point-to-point computer. It is to provide a network adapter device that can be applied to a point-type network.

[0022]

In order to solve the above problems, a network adapter according to the present invention is a network adapter for adding a network function to a computer, which is for transmitting data to the network. A transmission first-in first-out buffer, a reception first-in first-out buffer for receiving data from the network, at least two dual port buffer memories, and a reception first-in first-out buffer for receiving the data. First control means for pipelined data transfer to one side of the dual port buffer memory and data transfer from the other side of the dual port buffer memory to the main memory of the computer; From the main memory to the du Second control means for pipelined data transfer to one side of the port port buffer memory and data transfer from the other side of the dual port buffer memory to the first-in first-out buffer for transmission. It is a thing.

[0023]

In the present invention, on the network adapter device,
At least two dual port small capacity buffer memories are provided between the main memory and the transmission / reception FIFO memory, and the transmission DMA processing from the main storage to the buffer memory, the writing processing from the buffer memory to the transmission FIFO memory, and the reception FI
A write process from the FO memory to the buffer memory and a receive DMA process from the buffer memory to the main memory are pipelined. For example, when a reception request is issued from the network side, after a free buffer surface (for example, surface A) is secured, the data is read from the reception FIFO memory and written in the buffer memory A surface, and at the same time, the buffer memory B
If valid reception data already exists on the side of the buffer memory, the data of the side of the buffer memory B is written to the main memory, and if valid transmission data already exists on the side of the buffer memory B,
The data on the B side of the buffer memory is written to the transmission FIFO memory. In the next bus cycle, when there is no transmission request to the network side, the data of the buffer memory A side written in the previous cycle is written to the main memory, but when there is a transmission request to the network side, the main memory is written. The data is read from and written in the buffer memory B side.

As can be inferred from the above description, arbitration is performed by inputting two requests, a reception request and a transmission request, and a write request from the reception FIFO memory to the buffer memory (A, B) and a buffer memory (A, B).
A state transition machine that outputs a write request from B) to the transmission FIFO memory, a write request from the buffer memory (A, B) to the main memory, and a write request from the main memory to the buffer memory (A, B) is configured. As a result, reception and transmission can be interleaved in units of the capacity of one side of the buffer memory.

Further, instead of the "store and forward" format in which the data is read from the reception FIFO memory and the data is written to the transmission FIFO memory after waiting for the arrival of the entire packet, a part of the packet is arrived. Wait and run in a "wormhole" format.

For the problem of the device driver overhead, the network device fetches a table describing commands for packet transmission processing in a list format and a table describing commands for packet reception processing in a list format. By doing so, the transmission / reception process is activated, and the presence / absence of an interrupt is specified in the table in the list format, so that the transmission / reception interrupt can be generated only when the device driver requires it. Further, the device driver is provided with two pointers (end head pointer and end tail pointer) in order to specify an area of a transmission / reception packet for requesting higher processing to the higher protocol processing unit and higher application.

Note that one command corresponds to one physical packet. Therefore, by increasing the MTU size, the number of times the table is fetched can be suppressed, and the overhead of the device driver can be substantially suppressed.

With the configuration of the present invention, it is possible to realize a low-latency transmission / reception mechanism similar to that used in the virtual channel technology of the T9000 transputer while increasing the MTU size of the packet.

As described above, according to the present invention, the transmission FIFO memory and the reception FIFO are provided on the network adapter device.
By having the O memory separately, the data transfer efficiency between the network adapter device and the main memory is improved. Also,
Since a FIFO memory, which is a type of dual port memory, is used, it is possible to transfer data in a "wormhole" format and improve latency.

In addition to the transmission FIFO memory and the reception FIFO memory on the network adapter device, at least 2
Since it has the buffer memory of the plane, it has the effect of double buffering, and even if the transmission right and the reception right of the I / O bus are switched every bus cycle, the use efficiency of the I / O bus, in other words, the throughput is improved. It never drops. Further, even when data having a large packet length exists in the reception FIFO memory, it is possible to write the transmission data in the main memory to the transmission FIFO memory by time division processing without waiting for the release of the reception FIFO memory for a long time. Therefore, the latency is improved. Furthermore, since interrupt processing can be performed in units of a plurality of packets, the overhead of the device driver due to interrupt processing is reduced.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a network adapter device according to the present invention will be described in detail below with reference to the drawings.

First, the outline will be described with reference to FIG. The computer 100 and the computer 110 are connected to each other via a network. Since the computer 100 and the computer 110 have the same configuration, only the computer 100 will be described in detail below.

The computer 100 includes a high speed processor 106 such as RISC, a main memory (MS) 107, a device driver 120 and the network adapter device 1 according to the present invention.
01 is built in. The main memory 107 and the network adapter device 101 are connected via the I / O bus 105.
The device driver 120 is a block realized by the control program stored in the CPU 106 and the main memory 107.

The network adapter device 101 includes a network control processor 102 and a transmission FIFO (Firs).
It has a t-in first-out) 103 and a reception FIFO 104. The network control processor 102 has a main memory 1
07 via the I / O bus 105 between the transmission FIFO memory 103 and the reception FIFO memory 104
Control sending and receiving. The main memory 107 is provided with a transmission / reception command queue table area 108 secured by a device driver, which is software controlling the network adapter apparatus 101, and a transmission / reception data buffer area 109. The elements 111 to 119 and 130 of the computer 110 are
It is the same as the elements 101 to 109 and 120 of the computer 100.

Since the network communication of this embodiment is carried out in a transmission / reception independent type point-to-point format as shown in the figure, it is possible to independently perform transmission and reception on the network. On the other hand, the transmission / reception DMA processing between the main memory 107 and the network adapter device 101 is
The network control processor 102 switches transmission DMA and reception DMA by time division.

FIG. 2 shows the network control processor 10.
2 shows the internal configuration of No. 2. First, each component will be described.

The network control processor 102 has a dual port data buffer A side 201, a dual port data buffer B side 202, an I / O bus interface 203, a state machine (sequencer) 204,
It comprises a FIFO control unit 205, a DMA control unit 206, and an I / O register 223. The I / O register 223 includes a transmission command control unit 207, a reception command control unit 208, and a command control register 209.

The state machine 204 controls the read / write control of the data buffer A side 201, the B side 202 of the data buffer, the DMA control section 206, and the FIFO control section 205. The state machine 204 includes a transmission request signal 211 from the transmission command control unit 207 and a reception request signal 212 from the reception command control unit 208.
As an input, a control signal 213 to the FIFO control unit 205, a control signal 214 to the DMA control unit 206,
Read / write control signal 2 for data buffer A side 201
15, and signals such as a read / write control signal 216 for the data buffer B side 202 are generated.

The transmission command control unit 207 uses the main memory 10
7, the entry of the transmission command queue fetched from the command queue area 108, the first pointer and the second
Holds the value of the pointer, and generates the control signal 211 for the state machine 204 and the interrupt request signal 220 for the interrupt controller 210 according to the values of the first pointer and the second pointer. Transmission command control unit 207
The detailed operation of will be described later with reference to FIGS.

The received command control unit 208 has a main memory 107.
The received command queue entry fetched from the upper received command queue area 108 and the values of the first pointer and the second pointer are held, and the state machine 204 is supplied to the state machine 204 according to the values of the first pointer and the second pointer. The control signal 212 and the interrupt request signal 221 for the interrupt control unit 210 are generated. Received command controller 20
Details of 8 will be described later with reference to FIGS. 4 and 5.

The FIFO control unit 205 receives the control output signal 213 from the state machine 204 as an input and sends it to the transmission FIFO.
A control signal 218 for controlling the O103 and a control signal 219 for controlling the reception FIFO 104 are generated.

The DMA control unit 206 is also the state machine 2
The control output signal 214 from 04 is input to generate a control signal 217 for controlling the I / O bus 105.

The interrupt control unit 210 receives the interrupt request signal 220 from the transmission command control unit 207 and the interrupt request signal 221 from the reception command control unit 208 and inputs the interrupt signal 2 to the host CPU 106.
22 is generated.

The command control register 209 designates the start / stop of the operation of the send command controller 207 and the start / stop of the operation of the receive command controller 208. Details of the command control register 209 will be described later with reference to FIGS. 4 and 5 because they are closely related to pointer control.

Next, the network control processor 102
The operation of will be described. The main function of the network control processor 102 is to read out the command queue 108 on the main memory 107, and
07, a send command, and a receive command control control unit 208
The received command is read out to the transmission command control unit 207.
According to the command of the reception command control unit 208, the transmission FIFO 103, the reception FIFO 104, and the main memory 1
The DMA transfer with the data buffer 109 on 07 is performed in a pipeline manner.

The outline of the operation will be briefly described with reference to FIG. 9 by using an example. For example, it is assumed that the MTU size is 4 kbytes and the size of one side of the dual port data buffers 201 and 202 is 32 bytes. Also, receive F
It is assumed that 1 Kbyte of data is accumulated in the IFO memory 104. FIG. 9 shows the data buffer (A side 20) from the reception FIFO memory 104 as the reception timing.
1 or the B side 202) and the I / O bus transfer from the data buffer to the I / O bus 105 are shown. In addition, I /
The state of I / O bus transfer from the O bus 105 to the data buffer and network transfer from the data buffer to the transmission FIFO memory 103 is shown. DMA transfer is
It is executed in the following sequence.

If there is no transmission request, the first 32 bytes are read from the reception FIFO memory 104 and written in the dual port data buffer A side 201 (T1).
If there is no request for transmission at this point, the data in the dual port data buffer A side 201 is transferred to the I / O bus 10.
5 and DMA write to the main memory 107 (T2).
At the same time, the next 32 bytes are read from the reception FIFO memory 104 and the dual port data buffer B side 20
Write to 2 (T2). When the transmission request is not generated yet, the reception FIFO memory 104 alternately writes to the A side and the B side in this way, and the reading is continued in the pipeline from the side not written. In this example, 4 kbytes of data is written 128 times into the data buffer and read from the data buffer 128 times. If there is a transmission request during this process, B
Data is read from the surface to the I / O bus (T3),
The other surface (A surface) is used for transmission. That is, I /
Data is written from the O bus 105 to the A side (T
4). At the same time, the reception is continued and the data is written from the reception FIFO memory 104 to the B side (T4). next,
Data is read from the B side to the I / O bus 105, and at the same time, data is read from the A side to the transmission FIFO memory 103 (T5). Then, data is written from the reception FIFO memory 104 to the A side, and at the same time, the I
Data is written from the / O bus 105.

When a transmission request is accepted during the reception process, the reception pipelines up to that point are disturbed, but the use efficiency of the data buffers 201 and 202 does not decrease. That is, the throughput of the entire transmission and reception is the same. And,
The transmission latency is improved.

Although not shown, the case of only transmission is the same as the case of only reception described above except that the transfer direction is reversed.

In this embodiment, the two-sided buffer is used as the transmission / reception buffer, but generally, the N-sided (N is preferably 6 or more) buffer is used as the transmission / reception buffer and the transmission is performed. When the reception and the reception occur simultaneously, it is possible to minimize the disturbance of the pipeline by allocating three planes to the transmission and the reception, respectively.

The above is the description of the operation of the network adapter device.

Next, the processing flow of the device driver 120 when performing the DMA transmission processing and the DMA reception processing between the main memory 107 and the network adapter 101 will be described.

Before requesting the transmission processing to the network adapter device 101, the device driver 120 stores a transmission queue table in which entries storing command information necessary for the transmission processing are linked in a ring shape in the command queue area on the main memory 107. 108, and a buffer for storing transmission data is secured in the data buffer area 109 on the main memory 107. Similarly, the device driver 12
0 requests the network adapter device 101 to perform a receiving process, and secures a receiving queue table in the command queue area 108 in which entries storing command information necessary for the receiving process are connected in a ring shape and stores the received data. The buffer is secured in the data buffer area 109. Hereinafter, since the structures of the transmission queue table and the reception queue table are the same, they will be generically referred to as a queue table and their configurations will be described in detail.

FIG. 3 shows the structure of queue table entries and the data buffers designated by the queue table entries. 301 is the command queue area 1
08 indicates one queue table, and 302 indicates a packet buffer in the data buffer area 109 indicated by the entry of this queue table 301.
The network adapter device 101 activates the transmission / reception operation by fetching the contents of the queue table 301 secured in the main memory 107.

Bit 3 of command queue table 301
Reference numeral 03 is a bit indicating whether or not the entry of the queue table 301 includes information effective for the network adapter device, and will be referred to as a DMAEN bit hereinafter. DM
When the AEN bit is "0", it indicates that it is invalid, and when it is "1", it indicates that it is valid. Bit 3
Reference numeral 04 is a bit indicating whether or not to issue an interrupt to the host CPU 106 when the DMA processing is completed according to the command described in the entry, and will be hereinafter referred to as a DMAiNTEN bit. When the DMAiNTEN bit is "1", it indicates that the interrupt is issued after the processing is completed, and when it is "0", it indicates that the interrupt is not issued.

A field 305 is a status (STATUS) related to a transmission / reception packet when the network adapter device 101 finishes the transmission / reception command processing.
S) A field for returning information. By storing the status information as part of the 301 entry of the queue table, the device driver 120 can always obtain the status information synchronized with the packet.
Post-processing becomes easy.

The field 306 is a field (BUF ADDR) containing the start address of the area where the actual data is stored. The field 307 is a field (BUF COUNT) containing the number of bytes of actually transmitted / received data. Field 308
Is a field (BUF SIZE) containing the maximum size of the buffer 302. Field 309
A group of fields including attribute information of a communication process executing data transmission / reception on a network, which is usually a port number (PortID) and a node number (Node).
ID), a process ID (PID), and the like. Normally, the software header is O
Since it is separated from the data main body by S, when the software header is considered as a part of the packet, it is stored in the same area as the data buffer 302. However, as shown in the figure, part of the entry of the command queue table 301 is stored. By storing as, the device driver 120 does not need to cut out the header from the packet. Therefore, the post-processing of the packet by the device driver 120 can be speeded up.

Each of the transmission / reception command queue tables composed of entries having the above configuration is managed by two pairs (four) of pointers. One pair (start head pointer and start tail pointer) among them is a register on the network adapter device 101, and the remaining pair (end head pointer and end tail pointer) is on the main memory 107 managed by the device driver 120. It is a pointer.

Next, a method of managing the pointer of the transmission / reception command queue table will be described with reference to FIGS. The operation method by the pointer of the reception command queue table (FIG. 4 (B)) at the time of the reception processing is exactly the same as that of the transmission command queue table (FIG. 4 (A)) at the time of the transmission processing, and the description thereof will be omitted. Here, only the operation of the transmission command queue table in the transmission process will be described.

In FIG. 4A, reference numeral 401 denotes a head pointer (hereinafter, referred to as an entry of the transmission command queue table 301a on the main memory in which the command information required by the network adapter device for the current transmission processing is stored. Reference numeral 402 denotes a transmission start head pointer, and reference numeral 402 denotes a tail pointer (hereinafter referred to as a transmission start tail pointer) that points to the end of the entry of the transmission command queue table 301a in which the device driver 120 has written a valid entry. . Reference numeral 403 denotes a head pointer (hereinafter referred to as a transmission end head pointer) that points to the beginning of an area in which the transmission process is completed (written in the main memory) but the device driver 120 has not yet completed the process of passing the data to the program. Call). In other words, it can be interpreted as a pointer that points to the entry next to the entry released by the device driver 120 (the entry at the top (top) in FIG. 4A). Reference numeral 404 is a tail pointer (hereinafter referred to as a transmission end tail pointer) that points to the end of an area where the transmission process has been completed but the device driver 120 has not yet completed the process. The transmission end tail pointer 404 follows the transmission start head pointer 401. In the initial state, the transmission start head pointer 4
01 and the transmission start tail pointer 402 point to the head of the transmission queue table 301a. Similarly, the transmission end head pointer 403 and the transmission end tail pointer 404 also point to the head of the transmission queue table.

As described above, the pointers 411 to 414 of the received command queue table 301b shown in FIG.
Pointer 401 of transmission command queue table 301a
~ Similar to 404.

In the following, among the four queue table pointers for transmission and reception, the device driver 120
A total of three pointers, a start tail pointer, an end head pointer, and an end tail pointer, are managed and updated by referring to the value of the start head pointer, and the network control processor 102 starts by referring to the value of the start tail pointer. It is shown that the DMA transfer function based on the command queue control method can be realized by managing and updating the head pointer.

As shown in FIG. 5, the device driver 12
Reference numeral 0 is a (0) initial processing routine, which is a transmission start head pointer 401, a transmission start tail pointer 402, a transmission end head pointer 403, and a transmission end tail pointer 40.
4 is initialized to '0'.

(1) Commands are sequentially written to the entries from the transmission start head pointer 401. At the same time, the DMAEN bit of that entry is set to "1".

(2) The transmission start tail pointer 402 advances by the number of entries in which the command is written. From the transmission start head pointer 401 to the transmission start tail pointer 4
The entries up to 02 are called the start window.

(3) The start command is written in the command control register 209, and the operation of the transmission command control section 207 is started.

The transmission command control section 207 (4) reads the values of the transmission start head pointer 401 and the transmission start tail pointer 402 when the start command is written in the command control register 209.

(5) The entries from the transmission start head pointer 401 to the transmission start tail pointer 402 (start window) are sequentially read from the command queue table.

(6) DMAEN of the read entry
After confirming that the bit is "1" and executing the DMA transfer according to the command, the STATUS field 3
05, BUF_COUNT field 307 is written to the original entry as a return value and DMAEN bit 3
03 is rewritten from "1" to "0".

(7) The transmission start head pointer 401 is advanced by the number of times the DMA transfer is executed within the range where the transmission start tail pointer 402 is not overtaken.

(8) When the DMAiNTEN bit is set, the DMA end interrupt request line 220 requests an interrupt to the interrupt controller 210 (interrupt register).

(9) This causes an interrupt,
The interrupt processing routine 140 (described later in FIG. 8) is activated.

The device driver 120 executes the transmission end head pointer 403 to the transmission end tail pointer 4 in the interrupt processing routine 140 (DMA end interrupt or OS interval timer interrupt) (10).
The resources of the entries up to 04 are released, and after the resources are released, the end head pointer 403 is updated. If necessary, a new command is written in the entry between the transmission start tail pointer 402 and the transmission end head pointer 403. The transmission end tail pointer 404 is the DMAEN bit 3 of the entry pointed to by the transmission start head pointer 401.
When 03 is “1”, the transmission start head pointer 401
Is set to the value immediately before, and when it is '0', it is set to the same value as the transmission start head pointer 401.

The device driver sets the transmission end tail pointer 404 to the value of the transmission start head pointer 401 at a certain point in time in the past (during DMA end interrupt or OS interval interrupt), and the device driver sets the transmission end head pointer 403. The area between the end pointer 404 and the transmission end tail pointer 404 is transferred to the upper layer protocol processing and upper layer application. At this time, the device driver can know the end of the resource releasable area by referring to the value of the transmission start head pointer 401, but the I / O register (transmission start head pointer) is always sent through the I / O bus. Referencing the value of () causes the DMA to be interrupted, which causes a reduction in the overall throughput. In addition, accessing the I / O bus takes more time than a normal memory access, which is a heavy addition to the device driver. Therefore, the transmission end tail pointer 404 is useful for reducing the overhead of knowing the end of the resource releasable area by the device driver referring to the value of the transmission start head pointer every time.

Next, regarding the operation of the pointer, the critical situation will be divided into three cases.

(A) Transmission end head pointer 403,
When the transmission end tail pointers 404 match, and when the value of the DMAEN bit of the entry next to the entry pointed by both pointers is "1", the transmission end head pointer 403 and the transmission end tail pointer 404 are not updated. To On the other hand, the transmission start tail pointer 402 can be advanced to the same value as both pointers by writing a valid transmission entry. In this case, the three pointers of the transmission start tail pointer 402, the transmission end head pointer 403, and the transmission end tail pointer 401 may coincide with each other. When the value of the DMAEN bit of the entry next to the entry pointed by both pointers is "0", the transmission end head pointer 403 and the transmission end tail pointer 404 can be updated as in the normal operation.

(B) When the transmission end tail pointer 404 and the transmission start head pointer 401 match, in this case, the value of the DMAEN bit of the entry pointed to by both pointers is always "0". In this case, the network adapter device finishes the DMA transfer but does not finish updating the transmission start head pointer 401. However, when the transmission start head pointer 401 is updated over time, the state is exited.

(C) Transmission start head pointer 401,
If the transmission start tail pointers 402 match, in this case, in order to start the DMA transfer, whether the transmission command information of the entries is valid by checking the value of the DMAEN bit of the entries pointed by both pointers. A mechanism for determining is required. As one embodiment of this mechanism, the network adapter device autonomously fetches the value of the DMAEN bit irrespective of whether the pointers match / mismatch, and D is set only when the value of the DMAEN bit is "1".
The MA transfer is started, and when the value of the DMAEN bit is '0', the sleep state is set. In another embodiment, when the network adapter detects a pointer match, it interrupts the host with an interrupt request signal 220 to notify the device driver 120 of the pointer match, and the value of the DMAEN bit 303 is "0". Only in the case of ', the device driver 120 writes the command for starting the network adapter device in the command control register 209. DMAE
While the value of N bit is "1", the network adapter device can suspend the transmission process and switch to the reception process.

Next, FIG. 6 shows the transmission command control unit 207.
FIG. 2 shows an example of the circuit configuration of the circuit portion that generates the interrupt signal signal 220 in FIG. As can be seen from the above description, the reception command control unit 208 also includes a similar control circuit, but since both circuits can have exactly the same configuration, only the configuration of the control circuit for the transmission interrupt will be described. A register 501 stores the DMAEN bit 304 in the command information fetched from the command queue table. Reference numeral 502 denotes a flag register called a ready (RDY) bit register, which is set when the device driver 120 issues a start command to the transmission command control unit 207 to change from “0” to “1”, and the transmission / reception command control unit 207, During the normal operation of 208, the value of "1" is held and the transmission start head boundary 40
When 1 and the transmission start tail pointer 402 match, they are reset to "0". A comparator 503 includes a transmission start head pointer 401 and a transmission end tail pointer 4
02 match, the comparator match output signal line 514
The value of '1' is output to. Reference numeral 504 denotes a flag register called a DMA start register, which changes from “0” to “1” by writing a start command in the command control register 209. Reference numeral 505 is a DMA interrupt permission register that stores the DMAiNTEN bit 304 in the command information fetched from the command queue table. Reference numeral 506 is a register indicating the end of DMA. 5
Reference numeral 07 is a flag register called a display register during DMA operation, which holds a value of "1" during operation of the DMA.
Reference numeral 508 is a DMA count register that counts the number of DMAs (the number of data transfers for one surface of the data buffer). When the value of the DMAEN bit register 501 is “0”, 515 is set to “1” by the function of the AND circuit 509.
Is an illegal DMAEN bit interrupt request signal line. Reference numeral 516 is a pointer match interrupt request signal line that becomes "0" by the action of the AND circuit 510 when the start head pointer 401 and the start tail pointer 402 match. Reference numeral 517 denotes a DMA end interrupt request signal line which becomes "1" by the operation of the AND circuit 512 when the DMA is normally completed and the value of the DMA interrupt permission register 505 is "1". Reference numeral 518 denotes a DMA permission signal line which becomes "1" when the DMA operation is possible and becomes "0" when the DMA operation is not possible due to the function of the OR circuit 513. This value is DMA
It is stored in the operating display register 507. OR circuit 51
By the function of 1, the logical sum signal of the illegal DMAEN bit interrupt request signal line 515, the pointer match interrupt request signal line 516 and the DMA end interrupt request signal line 517 is output as the interrupt request signal (iNT) 220.

Finally, FIGS. 7 and 8 show the processing flow of the device driver 120. 7 shows a main routine, and FIG. 8 shows an interrupt processing routine.

In the main routine of FIG. 7, as described above, the device driver 120 initializes the pointers of a total of eight transmission / reception command queue tables (71),
The send / receive command is set in the send / receive command queue table 108 (118) in the main memory (72). After that, the ready bit of the ready bit register 502 is set by writing a start command in the command control register 209 (73). Thereafter, the send / receive command queue table is sequentially set according to the request of the application program (74), the pointers other than the start head pointer are updated (75), and the process returns to step 74.

In the interrupt processing routine of FIG.
Address the MAEN bit error, pointer match interrupt, and end interrupt. If the illegal DMAEN bit is '1' (81), device driver protocol error processing is performed (82). If the pointers match (83), proceed to the pointer matching interrupt processing routine,
After setting the send / receive command in the send / receive command queue table 108 (118) in the main memory as in the case of the initial setting (8
4) The normal operation is performed by writing the start command again in the command control register (85). If the pointers do not match, a DMA end interrupt process is performed (8
6).

[0083]

As described above, according to the present invention, it is possible to realize a network adapter device which realizes inexpensive and low latency communication between nodes. Specifically, the following effects are obtained by the present invention.

(1) Simplification of hardware Since it is not necessary to have a large-capacity buffer memory on the network adapter device, it is possible to integrate the hardware on a small scale and to supply an inexpensive device.

(2) Low latency inter-node communication By using a small-capacity dual port memory, it is possible to interleave the transmission / reception operations between the network and the main memory in small data units, so that low latency inter-node communication becomes possible. .

(3) Component compatibility of device driver Since the device driver can realize the transmission / reception operation only by accumulating the commands in the command queue table of the ring buffer structure for both transmission and reception, the device driver interface for transmission and reception is provided. It is possible to make the interface compatible with each other. Further, maintenance is easy because only one of the device drivers needs to be created.

(4) High-speed operation of device driver As shown in the embodiment, the device driver refers to the transmission (reception) end head pointer and the transmission (reception) end head pointer, and , Can give commands fast.

(5) Reduction of Interrupt Overhead Since the presence / absence of a transmission / reception end interrupt can be described in the command queue table for each entry, the number of interrupts to the device driver can be easily changed. As a result, a device driver having a response speed matching the speed of the network can be realized without redesigning the device driver.

(6) Realization of automatic header separation mechanism Since the header part of a transmission / reception packet can be stored as a part of the entry of the command queue table, it is originally O
The function performed by S can be replaced.

(7) Realization of status packet synchronization mechanism By having the status of transmission / reception operation in the entry field of the command queue table, it is possible to return the status asynchronously without using a complicated data structure such as a linked list. The status information synchronized with the transmitted / received packet can be returned to the OS.

[Brief description of drawings]

FIG. 1 is a block diagram of a computer system in which computers adopting a network adapter device according to an embodiment of the present invention are network-connected.

FIG. 2 is a block diagram showing an internal configuration of the network control processor shown in FIG.

FIG. 3 is an explanatory diagram of a configuration of a command queue table entry in the embodiment.

FIG. 4 is an explanatory diagram of a command queue table control pointer for transmission processing and reception processing according to the embodiment.

FIG. 5 is another explanatory diagram of a command queue table control pointer for transmission processing and reception processing in the embodiment.

FIG. 6 is a circuit diagram of a critical path control circuit according to an embodiment.

FIG. 7 is a flowchart of a main routine of device driver processing.

FIG. 8 is a flowchart of a device driver interrupt processing routine.

FIG. 9 is a flowchart showing an operation example of the network control processor in the embodiment.

[Explanation of symbols]

 100, 110 ... Computer 101, 111 ... Network adapter device 102, 112 ... Network control processor 103, 113 ... Transmission FIFO memory 104, 114 ... Reception FIFO memory 105, 115 ... I / O bus 106, 116 ... CPU 107, 117 ... Main memory 108, 118 ... Send / receive command queue area 109, 119 ... Send / receive data area 120, 130 ... Device driver 140 ... Interrupt processing routine 201 ... Dual port data buffer A side 201 ... Dual port data buffer B side 203 ... I / O bus interface 204 ... State machine 205 ... FIFO control unit 206 ... DMA control unit 207 ... Send command control unit 208 ... Receive command control unit 209 ... Command control register 210 ... Interrupt control Part 211 ... Transmission request signal 212 ... Reception request signal 213 ... FIFO request signal 214 ... DMA request signal 215 ... Data buffer A side R / W control signal 216 ... Data buffer B side R / W control signal 217 ... DMAR / W control signal 218 ... Transmission FIFOR / W control signal 219 ... Reception FIFOR / W control signal 220 ... Transmission command control unit host interrupt request signal 221 ... Reception command control unit host interrupt request signal 222 ... Host interrupt signal 223 ... I / O Register 301 ... Send / receive command queue table 302 ... Send / receive data area 303 ... DMA start enable bit 304 ... Interrupt enable bit 305 ... Send / receive status 306 ... Send / receive data area start address 307 ... Actual send / receive data count 308 ... Send / receive data area maximum Is 309 ... software header area 401 ... transmission start head pointer 402 ... transmission start tail pointer 403 ... transmission end head pointer 404 ... transmission end tail pointer 411 ... reception start head pointer 412 ... reception start tail pointer 413 ... reception end head pointer 414 ... Reception end tail pointer 501 ... DMAEN bit register 502 ... Ready bit register 503 ... Comparator 504 ... DMA start register 505 ... DMA interrupt enable register 506 ... DMA end register 507 ... DMA operating display register 508 ... DMA count register 509 ... AND circuit 510 ... AND circuit 511 ... OR circuit 512 ... AND circuit 513 ... OR circuit 514 ... Comparator coincidence output signal line 515 ... Illegal DMAEN bit interrupt request Signal line 516 ... Pointer match interrupt request signal line 517 ... DMA end interrupt request signal line 518 ... DMA enable signal line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoichi Murase 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Tetsuhiko Okada 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi Ltd. Central Research Center

Claims (7)

[Claims] 1. A network adapter for adding a network function to a computer, a first-in first-out buffer for transmission for transmitting data to the network, and a receiving for receiving data from the network. A first-in first-out buffer, at least two dual-port buffer memories, a data transfer from the receiving first-in-first-out buffer to one surface of the dual-port buffer memory during reception, and another dual-port buffer memory Control means for pipelined data transfer from the main memory to the main memory of the computer; data transfer from the main memory to one surface of the dual port buffer memory during transmission; Port Buff Network adapter apparatus characterized by comprising: a second control means for performing the other side of the memory data transfer to the transmitter first-in-first-out buffer in a pipeline manner, the. 2. The network adapter device according to claim 1, wherein a device driver that drives the device writes a table describing a reception command for starting transfer from the reception first-in first-out buffer to the main memory. A table is provided on the main memory, a first pointer pointing to the first entry of the table describing the received command, a second pointer pointing to the last entry describing the received command, from the first-in first-out buffer A third pointer that points to the first entry of a table that describes a reception command that has been transferred to the main memory and that has not been processed by the device driver for the main memory, and the reception first Transfer from the in-first-out buffer to the main memory Has a fourth pointer that points to the last entry of the table that describes a received command whose processing by the device driver is incomplete and which has not been completed. While writing the received command from the entry indicated by the pointer, the second pointer is updated, and the first control means reads the entry pointed to by the first pointer and interprets the command to execute the command for reception. After the data transfer from the first-in first-out buffer to the main memory is executed, the value of the first pointer is updated, and the data transfer is continued until the first pointer matches the second pointer. Furthermore, the device driver, after finishing the processing for the main memory, releases the entry and then the third driver A network adapter device characterized by updating the pointer and updating the fourth pointer so as to track the first pointer. 3. The network adapter device according to claim 1, wherein a device driver for driving the device writes a table describing a transmission command for starting transfer from the main memory to the transmission first-in first-out buffer. A table is provided on the main memory, and a first pointer that points to the first entry of the table that describes the send command, and a second pointer that points to the last entry that describes the send command; From the main memory, a third pointer pointing to the first entry of a table describing a transmission command for which transfer to the first-out buffer is completed and processing by the device driver for the main memory is incomplete Transfer to the first-in first-out buffer for transmission Has a fourth pointer that points to the last entry of the table that describes a transmission command that has been completed and has not been processed by the device driver. While writing the transmission command from the entry indicated by the pointer, the second pointer is updated, and the first control means reads the entry pointed to by the first pointer and interprets and executes the command to execute the main memory. From the first-in first-out buffer for transmission to the first pointer, the value of the first pointer is updated, and the data transfer is continued until the first pointer matches the second pointer. Furthermore, the device driver, after finishing the processing for the main memory, releases the entry and then the third driver A network adapter device characterized by updating the pointer and updating the fourth pointer so as to track the first pointer. 4. The network adapter device according to claim 2 or 3, wherein a field describing status information of transmission / reception packets on the network is provided in a part of the table. 5. The network adapter according to claim 2 or 3, wherein the device has a field for designating whether or not to issue an interrupt after the processing is completed, as a part of the table. apparatus. 6. The network adapter according to claim 2, wherein the header part of the packet received from the network is written in a part of a table describing the received command separately from the data body part. apparatus. 7. The network adapter device according to claim 1, wherein the size of one surface of the dual port buffer memory is set to a maximum transfer unit (MT) of the network.
U) A network adapter device characterized by being made sufficiently smaller than the size.