JPH06260765A - Multilayer wiring board and manufacture thereof - Google Patents
Multilayer wiring board and manufacture thereofInfo
- Publication number
- JPH06260765A JPH06260765A JP4114893A JP4114893A JPH06260765A JP H06260765 A JPH06260765 A JP H06260765A JP 4114893 A JP4114893 A JP 4114893A JP 4114893 A JP4114893 A JP 4114893A JP H06260765 A JPH06260765 A JP H06260765A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- multilayer wiring
- resin
- degree
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は電子機器、電気機器、計
算器、通信機器等に用いられる多層配線基板、多層配線
板に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a multilayer wiring board used in electronic equipment, electric equipment, calculators, communication equipment and the like.
【0002】[0002]
【従来の技術】近年、電気、電子機器の高信頼化対策と
して低ハロー性が要求されている。このため電気用積層
板の穴明け工程においては細心の注意が必要とされ、作
業能率を著しく低下させている。この対策として回路の
銅表面に酸化銅を形成させた後、還元する方法があり有
効であるが、処理工程が複雑となり工程管理が難しくコ
ストアップを招く欠点があった。2. Description of the Related Art In recent years, a low halo property is required as a measure for improving reliability of electric and electronic equipment. For this reason, meticulous attention is required in the process of punching the electrical laminate, which significantly reduces the work efficiency. As a countermeasure, there is a method of forming copper oxide on the copper surface of the circuit and then reducing it, but it is effective, but it has a drawback that the process is complicated and the process control is difficult and the cost is increased.
【0003】[0003]
【発明が解決しようとする課題】従来の技術で述べたよ
うに、低ハロー性を良くするための従来方法は何れも困
難で作業能率を著しく低下させている。本発明は従来の
技術における上述の問題点に鑑みてなされたもので、そ
の目的とするところは作業能率を低下させることなく容
易に低ハロー性を実現させる多層配線基板、多層配線板
を提供することにある。As described in the prior art, all the conventional methods for improving the low halo property are difficult and work efficiency is remarkably reduced. The present invention has been made in view of the above problems in the prior art, and an object of the present invention is to provide a multilayer wiring board and a multilayer wiring board that easily realize a low halo property without lowering work efficiency. Especially.
【0004】[0004]
【課題を解決するための手段】本発明は所要枚数の樹脂
硬化度が90%以下の回路形成した内層材の各上面及び
又は各下面に樹脂層を介し、最外層に金属箔を配設後、
樹脂層の樹脂硬化度が90%以下になるように硬化させ
たことを特徴とする多層配線基板及び該多層配線基板に
開穴、回路形成後、完全硬化させてから鍍金以降の工程
を施すことを特徴とする多層配線板の製造方法のため、
ドリル開穴時のクラックを抑制し上記目的を達成するこ
とができたもので、以下本発明を詳細に説明する。According to the present invention, after a resin foil is provided on each upper surface and / or each lower surface of an inner layer material having a circuit formed with a required number of resin curing degrees of 90% or less, a metal foil is provided as an outermost layer. ,
A multilayer wiring board characterized by being cured so that the degree of resin curing of the resin layer is 90% or less, and forming a hole in the multilayer wiring board, forming a circuit, and then completely curing and then performing the plating and subsequent steps. Because of the method for manufacturing a multilayer wiring board characterized by
The present invention will be described in detail below since the above object was achieved by suppressing cracks during drilling.
【0005】本発明に用いる内層材はフェノ−ル樹脂、
エポキシ樹脂、ポリイミド樹脂、不飽和ポリエステル樹
脂、ポリフェニレンオキサイド樹脂、フッ素樹脂等の樹
脂に必要に応じてタルク、クレー、シリカ、炭酸カルシ
ュウム、水酸化アルミニゥム、三酸化アンチモン、五酸
化アンチモン等の無機質粉末充填剤、ガラス繊維、アス
ベスト繊維、パルプ繊維、合成繊維、セラミック繊維等
の繊維質充填剤を添加したものである。基材としてはガ
ラス、アスベスト等の無機質繊維、ポリエステル、ポリ
アミド、ポリアクリル、ポリビニルアルコール、ポリイ
ミド、フッ素樹脂等の有機質繊維、木綿等の天然繊維の
織布、不織布、紙、マット等を用いることができる。基
材に対する含浸は同一の樹脂のみによる含浸でもよい
が、同系樹脂又は異系樹脂による1次含浸、2次含浸と
いうように含浸を複数にし、より含浸が均一になるよう
にすることもできる。かくして基材に樹脂を含浸、乾燥
して得た所要枚数の樹脂含浸基材の上面及び又は下面に
銅、アルミニュウム、真鍮、ニッケル、鉄等の単独、合
金、複合箔からなる金属箔を配設ー体化してなる電気用
積層板に回路形成して内層材を得るものであるが、樹脂
硬化度を90%以下にしておくことが必要である。内層
材の上面及び又は下面に配設される樹脂含浸基材として
は上記のような樹脂含浸基材をそのまま用いることがで
き、上記のような金属箔を最外層に配してから樹脂硬化
度が90%以下になるように硬化させるものである。樹
脂硬化度を90%以下にするには完全硬化に必要な成形
温度の95%以下の温度及び又は完全硬化に必要な成形
時間の45%以下の時間で硬化させることが必要で、か
くして低ハロー性に優れた多層配線基板を得るものであ
る。次に該多層配線基板にスルホール穴等を開穴、回路
形成後、アフターキュアーをおこない完全硬化させる。
完全硬化方法は樹脂硬化度を90%以下で止めた時の不
足分を充足すればよい。以降の作業は通常方法に従って
鍍金以降の工程を施し多層配線板を得るものである。The inner layer material used in the present invention is phenol resin,
Inorganic powder filling such as talc, clay, silica, calcium carbonate, aluminum hydroxide, antimony trioxide, antimony pentoxide, etc. as needed for resins such as epoxy resin, polyimide resin, unsaturated polyester resin, polyphenylene oxide resin, fluororesin, etc. Agent, glass fiber, asbestos fiber, pulp fiber, synthetic fiber, ceramic fiber and other fibrous fillers are added. As the base material, it is possible to use glass, inorganic fibers such as asbestos, organic fibers such as polyester, polyamide, polyacrylic, polyvinyl alcohol, polyimide and fluororesin, woven cloth of natural fibers such as cotton, non-woven fabric, paper and mat. it can. The base material may be impregnated only with the same resin, but a plurality of impregnations such as primary impregnation with the same resin or different type resin and secondary impregnation may be performed to make the impregnation more uniform. Thus, a metal foil consisting of a single, alloy, or composite foil of copper, aluminum, brass, nickel, iron, etc. is provided on the upper and / or lower surface of the required number of resin-impregnated base materials obtained by impregnating the base material with resin and drying. Although the inner layer material is obtained by forming a circuit on a laminated electric laminate, it is necessary to set the degree of resin curing to 90% or less. As the resin-impregnated base material disposed on the upper surface and / or the lower surface of the inner layer material, the resin-impregnated base material as described above can be used as it is. Is 90% or less. In order to reduce the degree of resin curing to 90% or less, it is necessary to cure at a temperature of 95% or less of the molding temperature required for complete curing and / or a time of 45% or less of the molding time required for complete curing, and thus a low halo A multi-layer wiring board having excellent properties is obtained. Next, through holes are formed in the multilayer wiring board, and after forming a circuit, after-curing is performed to completely cure the wiring.
The complete curing method may satisfy the deficiency when the resin curing degree is stopped at 90% or less. Subsequent work is to obtain a multilayer wiring board by performing the steps after plating according to the usual method.
【0006】以下本発明を実施例に基づいて説明する。The present invention will be described below based on examples.
【0007】[0007]
【実施例1】エポキシ当量475のビスフェノ−ルA型
エポキシ樹脂100重量部(以下単に部と記す)に、ジ
シアンジアミド4部、ベンジルジメチルアルコール0.
2部、メチルオキシトール100部を添加したエポキシ
樹脂ワニスを、厚み0.018mmの平織ガラス布に乾
燥後樹脂付着量が45%になるように含浸、乾燥して樹
脂含浸基材を得た。次に該樹脂含浸基材4枚を重ねた上
下面に厚み0.018mmの銅箔を各々配設した積層体
を成形圧力30Kg/cm2 、160℃で30分間加熱
加圧成形して厚み0.9mmの両面銅張積層板を得た。
次に該積層板の上下面に回路形成してから両面に各々上
記と同じ樹脂含浸基材1枚を介してから厚み0.018
mmの銅箔を配設した積層体を成形圧力30Kg/cm
2 、160℃で30分間積層成形して樹脂硬化度が85
%の多層配線基板を得、該多層配線基板2枚を重ね、6
5000rpm、送り25ミクロン/rpmでドリルマ
シンで開穴後、スルホール鍍金をおこない多層配線板を
得た。Example 1 To 100 parts by weight of a bisphenol A type epoxy resin having an epoxy equivalent of 475 (hereinafter simply referred to as "part"), 4 parts of dicyandiamide and 0.
An epoxy resin varnish added with 2 parts and 100 parts of methyl oxytol was impregnated into a plain woven glass cloth having a thickness of 0.018 mm so that the resin adhesion amount was 45% after drying, and dried to obtain a resin-impregnated base material. Next, a laminate having four copper-impregnated base materials and copper foils each having a thickness of 0.018 mm provided on the upper and lower surfaces thereof was heated and pressed at 160 ° C. for 30 minutes under a molding pressure of 30 kg / cm 2 , and the thickness was reduced to 0. A double-sided copper-clad laminate having a size of 0.9 mm was obtained.
Next, a circuit is formed on the upper and lower surfaces of the laminated plate, and the same resin-impregnated base material as described above is interposed on both surfaces, and then a thickness of 0.018
Molding pressure is 30 kg / cm
2 , the resin curing degree is 85 after laminating at 160 ℃ for 30 minutes
% Multi-layered wiring board is obtained, two of the multi-layered wiring boards are stacked, and 6
After drilling with a drill machine at 5000 rpm and a feed rate of 25 microns / rpm, through-hole plating was performed to obtain a multilayer wiring board.
【0008】[0008]
【実施例2】実施例1と同じ多層配線基板を実施例1と
同じ条件で開穴後、170℃で60分間アフターキュア
ーし樹脂硬化度が100%の多層配線基板をスルホール
鍍金して多層配線板を得た。[Embodiment 2] The same multilayer wiring board as in Example 1 is opened under the same conditions as in Example 1, after-cured at 170 ° C. for 60 minutes, and a multilayer wiring board having a resin curing degree of 100% is plated with a through hole to obtain multilayer wiring. I got a plate.
【0009】[0009]
【比施例】2次成形時の成形条件を175℃で120分
間とし、樹脂含浸基材の硬化度を100%にした以外は
実施例1と同様に処理して多層配線基板、多層配線板を
得た。Comparative Example A multilayer wiring board and a multilayer wiring board were processed in the same manner as in Example 1 except that the molding conditions at the time of secondary molding were 175 ° C. for 120 minutes and the curing degree of the resin-impregnated base material was 100%. Got
【0010】実施例1と2及び比較例の多層配線板のT
g、ハローイングサイズ、耐薬品性は表1のようであ
る。硬化度はDSCで評価し、ハローイングは外層プリ
プレグを引剥してハローイングの大きさを光学顕微鏡で
測定した。T of the multilayer wiring boards of Examples 1 and 2 and Comparative Example
Table 1 shows g, halo size, and chemical resistance. The degree of cure was evaluated by DSC, and the halo was measured by peeling the outer layer prepreg and measuring the size of the halo with an optical microscope.
【0011】[0011]
【表1】 [Table 1]
【0012】[0012]
【発明の効果】本発明は上述した如く構成されている。
特許請求の範囲に記載した構成を有する多層配線基板、
多層配線板においては、低ハロー性で、本発明の優れて
いることを確認した。The present invention is constructed as described above.
A multilayer wiring board having the configuration described in the claims,
It was confirmed that the multilayer wiring board had a low halo property and was excellent in the present invention.
Claims (2)
形成した内層材の各上面及び又は各下面に樹脂層を介
し、最外層に金属箔を配設後、樹脂層の樹脂硬化度が9
0%以下になるように硬化させたことを特徴とする多層
配線基板。1. A resin curing degree of a resin layer after arranging a metal foil as an outermost layer through a resin layer on each upper surface and / or each lower surface of an inner layer material having a required number of resin curing degrees of 90% or less. Is 9
A multilayer wiring board, characterized by being hardened so as to be 0% or less.
線基板に開穴、回路形成後、完全硬化させてから鍍金以
降の工程を施すことを特徴とする多層配線板の製造方
法。2. A method for manufacturing a multilayer wiring board, comprising: forming a hole in a multilayer wiring board having a resin layer having a resin curing degree of 90% or less; forming a circuit;
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4114893A JPH06260765A (en) | 1993-03-02 | 1993-03-02 | Multilayer wiring board and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4114893A JPH06260765A (en) | 1993-03-02 | 1993-03-02 | Multilayer wiring board and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06260765A true JPH06260765A (en) | 1994-09-16 |
Family
ID=12600340
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4114893A Pending JPH06260765A (en) | 1993-03-02 | 1993-03-02 | Multilayer wiring board and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06260765A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3740263A1 (en) * | 1987-11-27 | 1989-06-01 | Schlafhorst & Co W | WINDING DEVICE FOR CROSS REELS |
JP2010034142A (en) * | 2008-07-25 | 2010-02-12 | Sumitomo Bakelite Co Ltd | Method of manufacturing multilayer wiring board, multilayer wiring board and semiconductor device |
-
1993
- 1993-03-02 JP JP4114893A patent/JPH06260765A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3740263A1 (en) * | 1987-11-27 | 1989-06-01 | Schlafhorst & Co W | WINDING DEVICE FOR CROSS REELS |
JP2010034142A (en) * | 2008-07-25 | 2010-02-12 | Sumitomo Bakelite Co Ltd | Method of manufacturing multilayer wiring board, multilayer wiring board and semiconductor device |
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