JPH06260495A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To provide a semiconductor device including spacers that sufficiently insulate gate regions and have good adhesion to an inner insulating film. CONSTITUTION:A gate region formed of a gate polysilicon layer 31 is located between a gate oxide film 21 and a nitride film 41 on a main surface of a semiconductor substrate 1. On the sides of the gate region are formed spacer oxide films 101 and 102 having L-shaped sections. Spacer oxide films 111 and 112 are applied to the edges of the spacer oxide films 101 and 102 so that arcuate spacers may be formed. The spacer oxide film 111 and 112 serve to increase the adhesion between the gate region and an insulator that covers the spacers. The gate polysilicon layer 31 is covered with the nitride film, and the spacers provide insulation for a wiring layer formed adjacent to the gate region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a spacer used for self-alignment on a side wall of a gate electrode and a method for manufacturing the same, and more particularly to a semiconductor device suitable for an LDDMOS transistor and a method for manufacturing the same. is there.

[0002]

2. Description of the Related Art In recent years, in MOS transistors, as the miniaturization progresses, the gate length becomes shorter. When this is used as a memory cell, the electric field of the gate at the time of writing becomes extremely high and the carrier passing therethrough is high. It gets energy to collide and ionize. This is called a hot carrier phenomenon and is a factor that causes deterioration of the characteristics of the MOS transistor. In order to improve this, the structure in which the impurity concentration at both ends of the gate is partially lowered and the electric field at this portion is lowered to prevent the occurrence of hot carrier is L
DD (Lightly Doped Drain-source) structure and DDD (Dou
There is a MOS transistor having a ble diffused drain structure or the like.

A method of manufacturing the spacer structure provided on the side wall of the gate electrode will be described below with reference to the LDDMOS transistor. In the LDDMOS transistor, a shallow diffusion layer for preventing the occurrence of hot carrier is formed around the channel region of the gate, and when forming the source / drain diffusion layer, a part of the shallow diffusion layer is covered with a spacer to form an ion. Prevents injection. Figure 5
FIG. 5A is a cross-sectional view showing a part of a manufacturing process of an LDDMOS transistor. In FIG. 5A, a gate oxide film 2 having a thickness of about 100Å is deposited on the surface of a semiconductor substrate 1. A polysilicon layer 3 having a thickness of about 2000Å to be a gate electrode is formed thereon, and a nitride film 4 which is an oxidation resistant film having a thickness of about 2000Å is further formed thereon.

Thereafter, as shown in FIG. 5B, a gate region consisting of the gate oxide film 2 ₁ and the gate polysilicon layer 3 _{1 is} selectively formed, and the gate polysilicon layer 3 ₁ is protected. The shallow diffusion layers 5 ₁ and 5 ₂ are formed through ion implantation of a dopant and a manufacturing process such as lamp annealing. Thereafter, as shown in FIG. 5C, an oxide film 6 is deposited so as to cover the gate polysilicon layer 3 ₁ . Subsequently, as shown in FIG. 5D, spacer silicon oxide films 8 ₁ and 8 ₂ are further formed on the side surface of the silicon oxide film 6 formed so as to cover the gate polysilicon layer 3 ₁ by the CVD method. Form. After that, source / drain diffusion layers 7 ₁ and 7 ₂ are formed by ion implantation. Then, the silicon oxide layer formed on the surface of the semiconductor substrate 1 is removed, and then a contact hole is formed so as to cover the silicon oxide film, and a wiring layer is formed by the conductive thin film. The above-mentioned conventional example is described in Japanese Laid-Open Patent Publication No. 2-113538, and in this LDDMOS transistor, a silicon oxide film is formed so as to cover the gate region, and then a silica coating film is formed by spin coating. Then, an LDDM having a double-layered sidewall structure
OS transistors have been proposed.

[0005]

[Problems to be Solved by the Invention] LDDM as described above
The OS transistor, the spacers formed on the sidewalls of the gate region, a shallow diffusion layer 5 _1, 5 ₂ and the source-drain diffusion layers 7 _1, 7 ₂ is formed, a shallow diffusion layer 5 ₁ by a spacer, 5 ₂ Although the spacers are protected, the spacers silicon oxide films 8 ₁ and 8 ₂ are also ion-implanted with the dopant to impart conductivity to their surfaces.
Therefore, the insulation may be destroyed from the side surface of the gate region. That is, when an interlayer insulating layer is deposited so as to cover the gate region, a contact hole is formed adjacent to the gate region, and a wiring layer made of a conductive thin film is formed thereon,
When the deposition rate of the silicon oxide film on the side wall of the gate polysilicon layer is reduced, or when the contact holes are formed, the spacer silicon oxide films 8 ₁ and 8 ₂ are damaged during the buried contact etching. , A leakage current between the gate electrode and the buried contact, or in the worst case, a short circuit may occur. In addition, the source
When the drain diffusion layers 7 ₁ and 7 ₂ are formed, the dopant is injected into the surfaces of the spacer silicon oxide films 8 ₁ and 8 ₂ to impart conductivity, so that the gate polysilicon layer 3 ₁ is further improved. Spacer Silicon oxide film 8 ₁ , 8 ₂
The insulation may break through the surface of the.

The present invention has been made in view of the above-mentioned problems, and its main purpose is to provide a semiconductor device including a spacer which is suitable for use in self-alignment and has a good gate region insulating property. The manufacturing method is provided. Still another object of the present invention is to provide a semiconductor device having a good adhesion between a spacer formed on a side surface of a gate region and an interlayer insulating layer, and a manufacturing method thereof.

[0007]

In order to achieve the above object, the present invention relates to a semiconductor device having a spacer on a side wall of a gate region and a method of manufacturing the same, as follows. In the first semiconductor device, the gate region is composed of at least a gate oxide film sandwiching a gate polysilicon layer and an oxidation resistant film, and a spacer film of at least two layers is attached to a sidewall of the gate region to form the gate region. At least one of the spacer films in contact with the interlayer insulating layer has the same material composition as the interlayer insulating layer that covers the same material composition surface or two or more material composition surfaces of the spacer film. It is characterized in that it is a spacer film which is an affinity film with the interlayer insulating layer. In the second semiconductor device, the gate region is composed of at least a gate oxide film and a nitride film sandwiching a polysilicon layer, a spacer nitride film having an L-shaped cross section is attached to a sidewall of the gate region, and a step of the spacer nitride film is formed. By filling a space with a spacer oxide film which is a buffer material for the interlayer insulating layer, the spacer has a smooth curved shape.

In a third semiconductor device, a gate region is composed of at least a gate oxide film and a nitride film sandwiching a polysilicon layer, and a sidewall oxide film is formed on a sidewall of the polysilicon layer and the gate oxide film. A spacer nitride film having an L-shaped cross section is provided on the sidewall of the gate region to cover the sidewall oxide film, and the step portion of the spacer nitride film is filled with a spacer oxide film which is a buffer material for the interlayer insulating layer.
The spacer has a smoothly curved shape. Fourth
In the semiconductor device, the gate region is composed of at least a gate oxide film and a nitride film sandwiching a polysilicon layer, an arc-shaped spacer nitride film is attached to a sidewall of the gate region, and the spacer nitride film has an interlayer insulating layer. An arc-shaped spacer oxide film, which is a buffer material, is provided, and the spacer provided on the side wall of the gate region is formed into a smooth curved shape.
In a fifth semiconductor device, a gate region is composed of at least a gate oxide film and a nitride film sandwiching a polysilicon layer, a sidewall oxide film is formed on a sidewall of the polysilicon layer and the gate oxide film, and the gate region of the gate region is formed. An arc-shaped spacer nitride film is attached to the side wall, and an arc-shaped spacer oxide film serving as a buffer material for the interlayer insulating layer is attached to the spacer nitride film.

A first method of manufacturing a semiconductor device comprises a step of forming the gate region composed of at least a gate oxide film sandwiching a polysilicon layer and a first nitride film, and a second nitride film covering the gate region. And then forming an oxide film of substantially the same quality as the interlayer insulating layer on the second nitride film, and etching the oxide film and the second nitride film thereunder in the vertical direction. Forming a curved spacer on the side wall of the gate region by leaving a spacer oxide film on the step portion of the spacer nitride film having an L-shaped cross section attached to the side wall of the gate region. It is what A second method for manufacturing a semiconductor device comprises a step of forming the gate region composed of at least a gate oxide film and a first nitride film sandwiching a polysilicon layer, and a sidewall on a sidewall of the polysilicon layer and the gate oxide film. Forming an oxide film, depositing a second nitride film covering the gate region where the sidewall oxide film is formed, and then depositing an oxide film of substantially the same quality as the interlayer insulating layer. And a step of vertically depositing the oxide film and the second nitride film thereunder to form a step of the spacer nitride film having an L-shaped cross section attached to the sidewall of the gate region. Forming a curved spacer on the side wall of the gate region while leaving a spacer oxide film in the portion.

A third method of manufacturing a semiconductor device comprises a step of forming the gate region composed of at least a gate oxide film sandwiching a polysilicon layer and a first nitride film, and a second nitride film covering the gate region. After the deposition, an etching step of performing vertical etching to form an arc-shaped spacer nitride film on the side wall, and an oxide having substantially the same quality as the interlayer insulating layer covering the gate region where the spacer nitride film is formed are formed. An etching step of forming a film and forming the spacer oxide film covering the spacer nitride film. A fourth method of manufacturing a semiconductor device comprises a step of forming the gate region composed of at least a gate oxide film and a first nitride film sandwiching a polysilicon layer, and a side wall of the polysilicon layer and the gate oxide film. A step of forming a wall oxide film, an etching step of depositing a second nitride film covering the gate region and then performing a vertical etching to form an arc-shaped spacer nitride film on the side wall, and the spacer An etching step of forming an oxide film having substantially the same quality as the interlayer insulating layer covering the gate region where the nitride film is formed, and forming the spacer oxide film covering the spacer nitride film. is there.

[0011]

In the above means, the semiconductor device of the present invention is
A spacer nitride film is provided on the side wall of the gate region to insulate the gate portion, and the spacer oxide film is used as a buffer material with a material having good adhesion or affinity with the interlayer insulating layer,
The spacer has a curved shape to improve the adhesion with the interlayer insulating layer. Further, in the semiconductor device of the present invention, an arc spacer spacer oxide film having good adhesion between the arc spacer nitride film and the interlayer insulating layer is provided as a buffer material on the side wall of the gate region to prevent the insulation and the step difference between the gate regions. This is to alleviate and improve the adhesion between the spacer and the interlayer insulating layer. or,
In the semiconductor device of the present invention, a sidewall oxide film is formed on the side wall of the polysilicon layer in the gate region and the gate oxide film thereunder, a spacer nitride film is provided on the side wall of the gate region, and an interlayer insulating layer is formed. A spacer oxide film having good adhesion is provided as a buffer material to reduce the step difference in the gate region and enhance the adhesion between the spacer and the interlayer insulating layer.

Further, in the method for manufacturing a semiconductor device of the present invention, the above-mentioned shape is etched back or etched in the vertical direction to reduce the insulating property and the step difference in the gate region to improve the adhesion with the interlayer insulating layer. Forming a circular or arc-shaped spacer, the same material as that of the interlayer insulating layer is used on the outer side of the spacer to further enhance the adhesion to the interlayer insulating layer. Further, by forming an oxide film on the polysilicon layer in the gate region in advance, the adhesiveness with the spacer nitride film is enhanced and the insulating property is further enhanced. Further, even if the contact hole is formed adjacent to the polysilicon layer in the gate region, the spacer is formed of two or more layers, so that the spacer is not damaged in the manufacturing process.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. For example, a manufacturing process of forming a gate oxide film based on a spacer structure of an LDDMOS transistor will be described. A gate oxide film having a thickness of about 100Å is formed on the surface of the semiconductor substrate 1 by thermal oxidation. A polysilicon film with a thickness of about 2000 Å is deposited on top of this by doping phosphorus element into the polysilicon film to give conductivity, and further on top of this by a CVD method. A 2000 Å nitride film is formed. Then, a resist is applied, exposed, and developed to form a mask. As shown in FIG. 1A, the gate oxide film 2 ₁ ,
A gate region composed of the gate polysilicon film 3 ₁ and the nitride film 4 ₁ is formed, and further, in order to form an LDD structure using this gate region as a mask, ion implantation is performed to form shallow diffusion layers 5 ₁ and 5 ₂ . To do.

Next, as shown in FIG. 1B, a nitride film 10 is formed by CVD to cover the gate region by about 150.
The oxide film 11 is deposited to a thickness of 0Å, and then the oxide film 11 is similarly deposited to a thickness of about 1500Å by the CVD method. Subsequently, as shown in FIG. 1C, etchback is performed by plasma etching to remove the nitride film 10 _{1 on} both side walls of the gate region.
Thus, a spacer having a two-layer structure of the oxide film 11 _{1 and the} nitride film 10 ₂ and the oxide film 11 ₂ is formed. Of course, the etching may be performed by etching the polysilicon layer 6 in the vertical direction by anisotropic etching by the RIE method. After that, ion implantation is performed using the gate region and the spacer as a mask, and the source / drain diffusion layers 12 ₁ and 1 1 are formed.
2 ₂ is formed. Then, as shown in FIG.
By depositing an oxide film having a thickness of about 1500Å and then patterning it, the interlayer insulating layers 13 ₁ and 13 ₂ and the contact hole 13 ₃ are formed. Subsequently, the wiring layer 14 made of a conductive thin film is formed. Through such a manufacturing process, it is possible to form an LDDMOS transistor which solves the problem of miniaturization of a MOS transistor.

The semiconductor device of this embodiment has a structure in which the nitride film 4 ₁ is formed on the gate region and the side walls of the gate region are covered with the nitride films 10 ₁ and 10 ₂ , and the gate polysilicon layer 3 ₁ Has a structure covered with these nitride films. Further, spacer nitride films 3 ₁ , 3 ₂ having an L-shaped (or inverted L-shaped) cross section are provided on the sidewalls of the gate region, and the spacer oxide films 11 ₁ , 11 ₂ are buried in the step portions. The spacer has a curved shape or an arc shape. With such a smooth curved shape, the adhesion with the interlayer insulating layers 13 ₁ and 13 ₂ becomes good. Further, the spacer oxide films 11 ₁ and 11 ₂ have substantially the same material composition as the interlayer insulating layer or a material having an affinity, so that the adhesion with the interlayer insulating layer is further improved. Therefore, as shown in FIG. 1A, even if the wiring layer 14 is formed in a self-aligned manner so as to cover the gate region, the gate polysilicon layer 3 ₁ is formed by the nitride film 4 ₁ and the spacer nitride film 10 _1. It is protected, insulation between the gate polysilicon layer 3 ₁ and the wiring layer 14 is maintained. Even if plasma etching or the like of the interlayer insulating layer is performed in forming the contact hole 13 ₃ , the nitride film 4 _{1 in} the gate region and the nitride film 10 ₁ on the side wall thereof are not damaged at all, and the gate electrode It is possible to prevent generation of a leak current between the contact hole and the contact hole, a short circuit, or the like.
In this embodiment, the wiring 14 is the contact hole 13.
When connecting to the source / drain diffusion layer 12 ₁ via ₁ , the spacers 10 ₁ and 12 ₁ maintain their insulating properties,
With the interlayer insulating layer 13 ₁ can perform a self-aligned positioning of the wiring 14.

Embodiment 2 FIG. 2 shows another embodiment of the semiconductor device and the method for manufacturing the same according to the present invention. For example, a manufacturing process for forming a gate oxide film based on a spacer structure of an LDDMOS transistor will be described. . A gate oxide film having a thickness of about 100Å is formed on the surface of the semiconductor substrate 1 by thermal oxidation. A polysilicon film having a thickness of about 2000 Å is deposited thereon by a CVD method, and the polysilicon film is doped with a dopant such as phosphorus to impart conductivity, and CV is further formed on the polysilicon film.
A nitride film of about 2000 Å is formed by the D method. afterwards,
A resist is applied, exposed, and developed to form a mask. As shown in FIG. 2A, the gate oxide film 2 is formed.
₁ , a gate region composed of the gate polysilicon film 3 ₁ and the nitride film 4 ₁ is formed.

Then, as shown in FIG. 2B, the sidewall of the gate polysilicon layer 3 ₁ is annealed to about 100 Å by heat treatment.
Thin sidewall oxide films 15 ₁ and 15 ₂ are formed. Then, in order to form an LDD structure using this gate region or the like as a mask, a dopant such as a phosphorus element is ion-implanted, and a shallow anneal step 5 ₁ ,
5 ₂ is formed. Of course, after the shallow diffusion layers 5 ₁ and 5 ₂ are formed, the sidewall oxide film 15 is subjected to a heat treatment process.
₁ , 15 ₂ may be formed. Subsequently, as shown in FIG. 2C, a nitride film 10 is formed as a first layer film of the spacer film by a CVD method so as to cover the gate region by about 1500.
Then, the oxide film 11 is deposited to a thickness of about 1500Å as a second layer film of the spacer film.

After that, as shown in FIG. 2D, etchback is performed by plasma etching to form the nitride film 10 ₁ , the oxide film 11 ₁ and the nitride film ₁ on both side walls of the gate region.
A spacer having a two-layer structure of O ₂ and oxide film 11 ₂ is formed. Of course, this etching is performed by the RIE method.
The polysilicon layer 6 may be formed by etching in the vertical direction by anisotropic etching. Then, a dopant such as phosphorus is ion-implanted using the gate region and the spacer as a mask, and an annealing process is performed to form the source / drain diffusion layers 12 ₁ and 12 ₂ . Thereafter, as shown in FIG. 2E, an oxide film having a thickness of about 1500 Å is deposited and then patterned to form the interlayer insulating layer 13
₁ , 13 ₂ and contact hole 13 ₃ are formed.
Subsequently, the wiring layer 14 made of a conductive thin film is formed. An LDDMOS transistor can be formed through such manufacturing steps.

In the semiconductor device of this embodiment, the nitride film 4 ₁ is formed on the gate region, and the sidewall oxide film 1 is formed on the side wall of the gate polysilicon layer 3 _{1 in} the gate region.
The side wall of the gate region in which 5 ₁ and 15 ₂ are formed has a shape such that spacer nitride films 10 ₁ and 10 ₂ having an L-shaped (or inverted L-shaped) cross section are formed and the gate polysilicon layer 3 ₁ is embedded therein. it has, furthermore, arcuate spacers made a step portion of the spacer nitride film 10 _1, 10 ₂ from the spacer oxide film 11 _1, 11 ₂ fills smooth curve shape is formed.
By forming the side wall oxide films 15 _1, 15 _2, adhesion between the spacer nitride film 10 _1, 10 ₂ is good, the spacer nitride film 10 _1, 10 ₂ of the deposition rate is improved. Therefore, even if the contact hole 13 ₃ is formed in the vicinity of the gate polysilicon layer 3 ₁ and the wiring layer 14 is formed as in the above embodiment, the gate polysilicon layer 3 ₁
The insulation between the wiring layer 14 and the wiring layer 14 is maintained. Further, in forming the contact hole 13 _3, even when subjected to plasma etching, without any damage to the nitride film 4 ₁ and spacer nitride film 10 ₁ of the gate region. Therefore, it is possible to prevent the occurrence of leak current, short circuit, etc. between the gate electrode and the contact hole.

Embodiment 3 FIG. 3 is another embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. For example, a manufacturing process for forming a gate oxide film based on a spacer structure of an LDDMOS transistor will be described. . In FIG. 3, a gate oxide film having a thickness of about 100Å is formed on the surface of the semiconductor substrate 1 by thermal oxidation. A polysilicon film having a thickness of about 2000 Å is deposited thereon by CVD, and the polysilicon film is doped with a dopant such as a phosphorus element to impart conductivity, and further, a CVD film is formed to have a thickness of about 2000 Å. Form a nitride film. After that, a mask is formed by applying a resist, exposing it, and developing it to form a gate region, which is composed of a gate oxide film 2 ₁ , a gate polysilicon film 3 ₁ and a nitride film 4 ₁ as shown in FIG. 3A. Is formed, and in order to form an LDD structure using this gate region as a mask,
The shallow diffusion layers 5 ₁ and 5 ₂ are formed by ion-implanting a dopant such as phosphorus element.

Next, as shown in FIG. 3 (b), a nitride film is deposited to about 1500 Å by a CVD method so as to cover the gate region.
And is etched back by plasma etching to form first-layer spacer nitride films 16 ₁ and 16 ₂ in an arc shape on the side wall of the gate region. Then, FIG.
As shown in (c), an oxide film is formed by CVD to about 150
The spacer nitride film 1 of the first layer is deposited by depositing it to a thickness of 0Å and performing the same etch back by plasma etching.
The second layer spacer oxide film 1 so as to cover 6 ₁ and 16 _2.
7 ₁ and 17 ₂ are formed. In this way, the double-layered spacer is formed. The spacer nitride films 16 ₁ and 16
₂ and the spacer oxide films 17 ₁ and 17 ₂ may be formed by etching the nitride film in the vertical direction by anisotropic etching by the RIE method. Thereafter, as shown in FIG. 3D, the source / drain diffusion layers 12 ₁ and 12 ₂ are formed by ion-implanting a dopant such as a phosphorus element using the gate region and the spacer as a mask. Then, FIG.
As shown in (e), an interlayer insulating layer 1 is formed by depositing an oxide film having a thickness of about 1500Å by a CVD method or the like and patterning it.
3 ₁ , 13 ₂ and contact hole 13 ₃ are formed.
Subsequently, the wiring layer 14 made of a conductive thin film is formed. An LDDMOS transistor can be formed through such manufacturing steps.

In the semiconductor device of this embodiment, the gate region
Nitride film 4 on top of₁And a spacer that covers the sidewall of the gate region
Nitride film 16₁, 16₂And spacer oxide film that covers them
17 ₁, 17₂And the gate polysilicon layer 3₁Covered
It is a structured structure. Therefore, as in the above embodiment, the gate
Polysilicon layer 3₁Close to the contact hole 13 ₃
Wiring layer 1 so as to cover the gate region and the spacer.
4 is formed, the gate polysilicon layer 3₁And distribution
Good insulation with the wire layer 14 and no leak current
I can't see it. Also, the contact hole 13₃To form
Even if plasma etching is performed,
Nitride film 4 on top of₁And the spacer nitride film 16 on the side wall thereof₁
It is a manufacturing method that does not give any damage.

Embodiment 4 FIG. 4 shows another embodiment of a semiconductor device and a method of manufacturing the same according to the present invention. For example, a manufacturing process for forming a gate oxide film based on a spacer structure of an LDDMOS transistor will be described. . A gate oxide film having a thickness of about 100Å is formed on the surface of the semiconductor substrate 1 by thermal oxidation. A polysilicon film having a thickness of about 2000 Å is deposited thereon by CVD, and the polysilicon film is doped with a phosphorus element dopant to impart conductivity, and further CVD is performed thereon.
A nitride film of about 2000 Å is formed by the method. After that, a mask is formed by applying a resist, exposing it, and developing it to form a gate region, which is formed of a gate oxide film 2 ₁ , a gate polysilicon film 3 ₁ and a nitride film 4 ₁ as shown in FIG. 4A. Is formed.

Then, as shown in FIG. 4B, the sidewall oxide film 15 having a thickness of about 100 Å is formed by thermal oxidation.
₁ , 15 ₂ are formed. Further, by using this gate region as a mask, the shallow diffusion layers 5 ₁ , 5 are formed by the above method.
₂ to form an LDD structure. Subsequently, as shown in FIG. 4C, a nitride film 10 is deposited to a thickness of about 1500 Å by a CVD method so as to cover the gate region, and etch back is performed by plasma etching to form side walls of the gate region. Smooth curved arc-shaped spacer nitride film 16
₁ and 16 ₂ are formed, and subsequently, an oxide film is similarly deposited to a thickness of about 1500 Å by the CVD method and etched back by plasma etching to form the spacer oxide film 1.
7 ₁ and 17 ₂ are formed. The spacer nitride films 16 ₁ and 16 ₂ and the spacer oxide films 17 ₁ and 1 are formed on both side walls of the gate region.
A spacer having a two-layer structure of 7 ₂ is formed.

Of course, the etching in this case may also be formed by etching the spacer nitride film and the spacer oxide film in the vertical direction by anisotropic etching by the RIE method. After that, a dopant such as a phosphorus element is ion-implanted using the gate region and the spacer nitride film as a mask to form the source / drain diffusion layers 12 ₁ and 12 ₂ . Then, Fig. 1
As shown in (d), an oxide film having a thickness of about 1500 Å is deposited and then patterned to form the interlayer insulating layers 13 ₁ and 13 ₂ and the contact hole 13 _3, and a wiring layer made of a conductive thin film. 14 is formed. An LDDMOS transistor can be formed through such manufacturing steps.

In the semiconductor device of this embodiment, the nitride film 4 ₁ is formed on the upper portion of the gate region, and the arc-shaped spacer nitride films 16 ₁ , 16 ₂ are formed on the side wall of the gate region in a smooth curved shape.
And the gate polysilicon layer 3 ₁ is covered with the spacer nitride films 16 ₁ and 16 ₂ and the spacer oxide films 17 ₁ and 1 2.
It is covered with 7 ₂ . Therefore, the gate polysilicon layer 3
_Even if the contact hole 13 ₃ is formed in the vicinity of ₁ to form the wiring layer 14 in a self-aligned manner, the insulation between the gate polysilicon layer 3 ₁ and the wiring layer 14 is maintained as in the above embodiment. Be done. Even if plasma etching is performed in forming the contact hole 13 ₃ , the nitride film 4 _{1 in} the gate region and the spacer nitride film 16 ₁ on the side wall thereof are not damaged at all. In this embodiment, when the wiring 14 is connected to the source / drain diffusion layer 12 ₁ via the contact hole 13 ₁ , the spacers 16 ₁ and 17 ₁ are
While maintaining an insulating property, together with the interlayer insulating layer 13 ₁ can perform a self-aligned positioning of the wiring 14.

Although the gate region has the sandwich structure of the gate oxide film 2 ₁ , the gate polysilicon film 3 ₁ and the nitride film 4 _{1 in} the _{first to} third embodiments, the present invention is not limited to this embodiment. may be one of the gate polysilicon film 3 ₁ of the surface was oxidized, or by providing a buffer layer in accordance with the nature of the interlayer insulating layer heather, it is clear that not limited to examples is there. Further, if the gate polysilicon film 3 ₁ and the nitride film 4 ₁ are made of other materials, the spacer is made of a material having a good adhesiveness accordingly. By forming the sidewall oxide films 15 ₁ and 15 ₂ , the adhesion with the spacer nitride films 16 ₁ and 16 ₂ is good.

The gate region of the above-mentioned embodiment is formed by the gate polysilicon layer sandwiched between the gate oxide film and the nitride film. The polysilicon film is formed on the surface of this gate polysilicon layer and It is obvious that a nitride film may be formed on it. Further, when the gate polysilicon layer is another conductive film, a material having adhesiveness or affinity corresponding to it may be used. Further, the nitride film is not limited to the material of the embodiment as long as it is an oxidation resistant film. Of course, the spacer of the embodiment is LDDMOS.
Although it is used for positioning the LDD structure of the transistor and the source / drain diffusion layer, it is obvious that the present invention can be widely applied to semiconductor devices as a miniaturization technique without being limited to the semiconductor device and the manufacturing method thereof according to this embodiment. For example, it is apparent that the present invention can be applied to a semiconductor device having a structure in which a source / drain is formed by vapor-depositing a semiconductor layer on both sides of the spacer after forming the spacer. Further, although the spacer of the embodiment is described with reference to the LDDMOS transistor, it may be used simply for the purpose of eliminating the insulating property in the gate region or the step difference in the gate region to improve the adhesion with the interlayer insulating layer. That is clear.

[0029]

As described above, according to the present invention, the spacer nitride film and the spacer oxide film are formed on the sidewall of the gate region, and the spacer diffusion film and the source / drain diffusion layer are formed by the spacer. Is self-aligned to form an LDD structure, the spacer maintains insulation between the gate region and a wiring layer formed in the vicinity thereof, and further, an interlayer insulating layer covering the gate region is formed. A spacer oxide film having good adhesion is provided as a buffer material. That is, the gate polysilicon layer has a structure that is covered and protected by the nitride film and can prevent the generation of leak current, and therefore has an extremely high insulation property with the wiring layer formed so as to cover the gate region. It has a characteristic of being high, and has an advantage that the yield and reliability of a semiconductor device in which an LDDMOS transistor or the like is integrated can be improved. Further, the shape of these spacers can be made into an arc shape having a smooth curve by etching back or anisotropic etching as described above, the step difference in the gate region is eliminated, and the adhesiveness between the spacer and the interlayer insulating layer is eliminated. And the adhesion between the gate region and the spacer is also good by forming the sidewall oxide film. Further, the yield and reliability of the semiconductor device can be improved by using a material having good adhesion between the spacer and the interlayer insulating layer. Further, by forming the side wall oxide film on the side wall of the polysilicon layer in the gate region, the degree of adhesion with the spacer nitride film is improved, and the yield and reliability of the semiconductor device can be improved. As a matter of course, even if a contact hole is formed adjacent to the polysilicon layer in the gate region, it is possible to prevent the generation of leak current, so that it is possible to prevent the insulation from being broken.

[Brief description of drawings]

1A to 1D are cross-sectional views showing an embodiment of a semiconductor device and a method of manufacturing the same according to the present invention.

2A to 2E are cross-sectional views showing another embodiment of the semiconductor device and the manufacturing method thereof according to the present invention.

3A to 3E are cross-sectional views showing another embodiment of the semiconductor device and the method for manufacturing the same according to the present invention.

4A to 4D are cross-sectional views showing another embodiment of the semiconductor device and the manufacturing method thereof according to the present invention.

5A to 5D are cross-sectional views showing another example of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols] 1 semiconductor substrate 2 ₁ gate oxide film 3 ₁ gate polysilicon layer 4 ₁ nitride film 5 ₁ , 5 ₂ shallow diffusion layer 10 nitride film 11 oxide film 10 ₁ , 10 ₂ spacer nitride film 11 ₁ , 11 ₂ Spacer oxide film 12 ₁ , 12 ₂ Source / drain diffusion layer 13 ₁ , 13 ₂ Interlayer insulating layer 13 ₃ Contact hole 14 Wiring layer 15 ₁ , 15 ₂ Sidewall oxide film 16 ₁ , 16 ₂ Spacer nitride film 17 ₁ , 17 ₂ Spacer oxide film

Front page continuation (72) Inventor Masahiko Omatsu 1-2-1, Marunouchi, Chiyoda-ku, Tokyo Nihon Steel Pipe Co., Ltd.

Claims (9)

[Claims] 1. A semiconductor device having a spacer on a sidewall of a gate region, wherein the gate region comprises at least a gate oxide film sandwiching a gate polysilicon layer and an oxidation resistant film, and at least two sidewalls of the gate region are provided. Attach a spacer film of more than one layer,
An interlayer insulating layer covering the gate region contacts the same material composition surface or two or more material composition surfaces of the spacer film, and at least one of the spacer films contacting the interlayer insulating layer is the same as the interlayer insulating layer. 2. The semiconductor device, which is a spacer film of a material composition of the above or an affinity film with the interlayer insulating layer. 2. A semiconductor device having a spacer on a sidewall of a gate region, wherein the gate region comprises at least a gate oxide film and a nitride film sandwiching a gate polysilicon layer, and the sidewall of the gate region has an L-shaped cross section. A spacer nitride film is attached, and a spacer oxide film which is a buffer material for the interlayer insulating layer is filled in the step portion of the spacer nitride film, whereby the spacer has a smooth curved shape. 3. A semiconductor device having a spacer on a side wall of a gate region, wherein the gate region comprises at least a gate oxide film and a nitride film sandwiching a gate polysilicon layer, and a sidewall oxide is formed on a side wall of the polysilicon layer. A film is formed, a spacer nitride film having an L-shaped cross section is provided on the side wall of the gate region so as to cover the sidewall oxide film, and a spacer oxide film which is a buffer material for the interlayer insulating layer is provided in the step portion of the spacer nitride film. The semiconductor device is characterized in that the spacer is formed into a smooth curved shape by filling the space. 4. A semiconductor device having a spacer on a sidewall of a gate region, wherein the gate region comprises at least a gate oxide film and a nitride film sandwiching a gate polysilicon layer, and an arc-shaped spacer on a sidewall of the gate region. A nitride film is provided, and an arc-shaped spacer oxide film that is a buffer material for the interlayer insulating layer is provided on the spacer nitride film, and the spacer provided on the side wall of the gate region has a smooth curved shape. A semiconductor device characterized by: 5. A semiconductor device having a spacer on a sidewall of a gate region, wherein the gate region comprises at least a gate oxide film and a nitride film sandwiching a gate polysilicon layer, and a sidewall oxide is formed on a sidewall of the polysilicon layer. A semiconductor, wherein a film is formed, an arc-shaped spacer nitride film is provided on a side wall of the gate region, and an arc-shaped spacer oxide film serving as a buffer material for an interlayer insulating layer is provided on the spacer nitride film. apparatus. 6. A method of manufacturing a semiconductor device having a spacer on a side wall of a gate region, wherein the gate region including at least a gate oxide film sandwiching a gate polysilicon layer and a first nitride film is formed, Forming a second nitride film covering the gate region, and subsequently forming an oxide film having substantially the same quality as that of the interlayer insulating layer on the second nitride film; and the oxide film and a second underlying film. By etching the nitride film in the vertical direction, a spacer nitride film having an L-shaped cross section attached to the side wall of the gate region and a spacer oxide film on the step portion thereof are left, and the side wall of the gate region is curved. A method of manufacturing a semiconductor device, comprising the step of forming a spacer. 7. A method of manufacturing a semiconductor device having a spacer on a sidewall of a gate region, wherein the step of forming the gate region including at least a gate oxide film sandwiching a gate polysilicon layer and a first nitride film, Forming a sidewall oxide film on the sidewalls of the polysilicon layer and the gate oxide film; depositing a second nitride film covering the gate region where the sidewall oxide film is formed, and subsequently depositing an interlayer insulating layer; A step of depositing an oxide film having substantially the same quality as that on the second nitride film, and etching the oxide film and the second nitride film below the oxide film in the vertical direction to form a sidewall of the gate region. A semiconductor device comprising: a spacer nitride film having an L-shaped cross section attached thereto; and a step of forming a curved spacer on a sidewall of the gate region while leaving a spacer oxide film on a step portion thereof. Manufacturing method. 8. A method of manufacturing a semiconductor device having a spacer on a sidewall of a gate region, wherein the gate region is formed of at least a gate oxide film sandwiching a gate polysilicon layer and a first nitride film, An etching step of depositing a second nitride film covering the gate region and then performing vertical etching to form an arc-shaped spacer nitride film on the sidewall, and the gate region having the spacer nitride film formed thereon. A step of forming an oxide film having substantially the same quality as the interlayer insulating layer covering the spacer and forming the spacer oxide film covering the spacer nitride film. 9. A method of manufacturing a semiconductor device having a spacer on a side wall of a gate region, wherein the gate region including at least a gate oxide film sandwiching a gate polysilicon layer and a first nitride film is formed, Forming a sidewall oxide film on the sidewalls of the polysilicon layer and the gate oxide film; and, after depositing a second nitride film covering the gate region, etching in the vertical direction to form an arc shape on the sidewall. Etching step of forming the spacer nitride film, and forming an oxide film having substantially the same quality as the interlayer insulating layer covering the gate region where the spacer nitride film is formed, and forming the spacer oxide film covering the spacer nitride film. A method of manufacturing a semiconductor device, comprising: