JPH06268522A - Capacitor array type d/a converter circuit - Google Patents

Abstract

PURPOSE:To provide a D/A converter circuit employing a capacitor array whose capacitance total sumis small. CONSTITUTION:The D/A converter consists of capacitor arrays (11, 12) in which lots of capacitors (Ci) are connected in common at their respective one-side terminals, an integration means (10) connected to the common connecting point of the capacitor arrays, integrating the charge of each capacitor and resetting the integrated charge with a reset signal, reference potential application means (Vrefn, Vrefn + 1) applying respectively plural kinds of different reference potential sets with a predetermined relation, a reset means (13) connected between the other terminals of the capacitor arrays and the reference potential application means to reset the capacitor of the capacitor array with the reset signal, and a reference potential selection means (140 connected to the other terminals of the capacitor array via the reset means and selecting an optimum reference potential among plural kinds of reference potential sets with a received digital signal in plural bits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitance series DA conversion circuit, and more particularly to a capacitance series having a small total capacitance (hereinafter, if necessary,
It is called a capacitor array. The present invention relates to a DA conversion circuit having.

In an image display device which reproduces a still image at least instantaneously by a large number of scanning lines, input image data is digital-analog (hereinafter D) for each scanning line.
-A) Capacitive array type DA for conversion
A conversion circuit is used.

[0003]

2. Description of the Related Art FIG. 21 shows a typical example of a conventional capacitor array DA conversion circuit. This DA converter circuit includes a capacitor array in which a large number of capacitors whose capacitance values gradually change by powers of 2 are arranged in a row, reset means 3 for resetting the charge held in each capacitor by a reset signal, and each bit b1. , * B1, ... Bm and * bm and a reference potential Vref for applying the selected reference potential to the other end of each capacitor Ci of the capacitor array, and each of the capacitor arrays. The integrating means 10 is provided with an operational amplifier circuit OP having a sum of the capacitances Ci as one input and a ground potential as the other input, and supplying the drive voltage to a capacitive load. The digital signal * b1 represents an inverted signal of the digital signal b1.

In the DA conversion circuit shown in FIG. 21, the capacity for the most significant bit (MSB) is 2 for the least significant bit (LSB).
There is a problem that the total capacity becomes large because it becomes ^m-1 times. In order to deal with this problem, it has been conventionally proposed to configure the capacitor array in two stages.

FIG. 22 shows a DA conversion circuit using two stages of this capacitor array. 22, the DA conversion circuit has substantially the same configuration as the DA conversion circuit of FIG. 21 except that it has two-stage capacitor arrays 1 and 2. This D
The A conversion circuit is based on the IEEE Journal of So by YSYee and others.
lid-State Circuits, vol.sc-14, Aug. 1979 “A Two-State Weighted Capacitor Network for D / AA
/ D Conversion ". The capacitance of a capacitor array is given by Ci = 2 ^i-1 C1 for i≤m, and Ci = 2 ^im-1 for i≥m + 1. C
It is given at 1. Further, it is given by Cc = C1.

The operation will be briefly described below. First, the reset signal causes the switches SWRG, SWRC, SWR1, ...
With SWRm + n closed, all capacitors are equivalently GN
It is connected to D and the held charge is reset. During the reset period, each bit bi, / bi of the digital signal (/ indicates a negative (inverted) logic. The same applies hereinafter.) Is set to zero by an AND circuit as shown in FIG. ,……, SWRm + n, SWB1,
………, SWBm + n is open. When the reset period ends, the switches SWRG, SWRC, SWR1, ...
SWRm + n becomes open, and each capacitance C of the capacitor array is set by each bit bi, / bi of the input digital signal.
As the potential at one end of i (i = 1 to m + n), the reference potential Vre
f or ground potential GND is applied. At this time, the voltage Vc applied to the capacitance Cc is Is required. Therefore, the integrating means 10 is connected to the operational amplifier circuit O.
The charge Q stored in the capacitance CG configured with P is And the output Vout is

[0007] And DA-converted output is obtained. The maximum amplitude of this output is determined by the reference potential Vref and the capacitance ratio C1 / CG.

In the conventional example of FIG. 22, the total capacitance of the capacitor array is (2 ^m +2 ⁿ -1) C including Cc.
1 and, for example, assuming that C1 is 0.5 pF and m = n = 4 and 8-bit DA is assumed, it becomes 15.5 pF. For this reason, in applications that require a plurality of DA conversion circuits, a large total capacity is required, which is extremely disadvantageous in that the chip area is large for IC integration.

In the method using only one stage of the capacitor array as shown in FIG. 21, the capacity for MSB is 2 ^m-1 times the capacity for LSB with respect to the digital signal of m bits as described above. Therefore, if the number of bits is the same, the total capacitance is much larger than that of the configuration using two stages of capacitor arrays as shown in FIG.

[0010]

As described above, in the conventional DA conversion circuit using the capacitor array, the total sum of required capacities becomes large, and in particular, a plurality of DA conversion circuits are integrated into one chip. Had a problem that the chip area was increased, the cost was increased, and the reliability was lowered.

The present invention has been made in view of the above points, and provides a DA conversion circuit using a capacitor array having a small total sum of capacitances by operating with multistage reference voltages while keeping the capacitance ratio constant. It is in.

[0012]

A capacitor array DA converter circuit according to the present invention resets an electric charge to an integral by a reference potential supply means for supplying a plurality of types of reference potentials having a predetermined relationship with each other. Integrating means, a capacitor array having a plurality of capacitors, one end of which is commonly connected to the input of the integrating means, and a capacitor array of the capacitor array for resetting the capacitance of the capacitor array by the reset signal. An optimum one is selected from the plurality of kinds of reference potentials by a reset means connected to the other end and a digital signal of a plurality of bits connected to the other end of the capacitor array via the reset means and input. And a reference potential selection means.

[0013]

In the DA conversion circuit configured as described above, the absolute value of the difference voltage between the i-th (n ≧ i ≧ 3) reference potential and the first reference potential in the n types of reference potentials is the second reference potential. Of the absolute value of the difference voltage between the potential and the first reference potential, 2 ^j (n−2 ≧ j ≧
1) n (n ≧ 3) kinds of reference potentials having a double relationship, an integrating means capable of resetting charges integrated by a reset signal, and one end commonly connected to the input of the integrating means k A first capacitor array having (k ≧ 2) capacitors, reset means for resetting the capacitance of the first capacitor array by a reset signal, and the other end of each capacitor of the first capacitor array are input. By the k-bit digital signal, the a-th reference potential and the b-th (b ≠
It may be configured by a reference potential selecting means that is selectively connected to either of the reference potentials in a).

In the DA conversion circuit according to the present invention, since the reference potential selectively applied to one end of each capacitance of the capacitor array by the digital signal inputted is weighted, each capacitance value of the capacitor array is weighted. There is no need to attach it. Therefore, it is possible to keep the total capacitance of the capacitor array small. For example, when DA-processing a 6-bit digital signal, the capacity using the conventional two-stage capacitor array is 15 times the minimum capacity of the capacitor array, and the capacity using the single-stage capacitor array is the minimum capacity of the capacitor array. The capacitance of the capacitor array is required to be 63 times that of the capacitor array.
Double capacity is enough. Therefore, when the DA conversion circuit is integrated into an IC, it can be realized in a smaller area.
Even if the conversion circuit is built in one chip, it can be realized with a small chip area, and the cost can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a first embodiment of a capacitance column type DA conversion circuit according to the present invention. Integrating means 1
Reference numeral 0 is composed of an operational amplifier circuit OP and a capacitor CG, and the reset signal Reset resets the electric charge of the capacitor CG by the switch SWRG. Capacitor array 11
Is composed of k capacitors C1 to Ck each having the same capacitance value, and the common connection end of the capacitor array 11 is connected to the integrating means 10. The first reference potential Vref1 is applied as the AC GND of the integrating means 10. Therefore,
The common connection end of the capacitor array 11 is equivalently the reference potential Vref1. In addition, the switches SWR1 to SWRk constituting the reset means 13 are the capacitor array 11
Are provided between the other end of each capacitor and the reference potential Vref1, and the capacitor array 11 is provided by the reset signal Reset.
The electric charges accumulated in the capacitors C1 to Ck are reset. Switches SWB1 to constituting the reference potential selection means 14
SWBk is the other end of each capacitor of the capacitor array and the reference potential V
The connection is controlled by each bit signal bi (i = 1 to k) of the k-bit digital signal which is connected to ref1 and is given zero during the reset period by the reset signal Reset. In this case, the reference potential is given by Vrefi-Vref1 = 2 ^i-2 (Vref2-Vref1).

The DA of the first embodiment of the present invention shown in FIG.
The operation of the conversion circuit will be described. First, reset signal Reset
Thus, the reset means 13 resets the charges of the capacitor array 11 and the capacitance CG of the integrating means 10. Next, the reference potential selection means 14 applies the selected reference potential to the other end of each capacitance Ci of the capacitor array 11 by each bit bi, / bi (i = 1 to k) of the digital signal. At this time, the sum of the charges accumulated in each capacitance Ci of the capacitor array 11 is the charge Q accumulated in the capacitance CG of the integrating means 10.
Equal to Can be expressed as Therefore, the output Vout is And becomes DA converted output. The maximum amplitude of the output is determined by the difference between the reference potentials Vref2-Vref1 and the capacitance ratio C1 / CG.

The total sum of the capacitances of the capacitor array 11 required here is k times C1 for a k-bit digital signal. In the conventional method using one stage of the capacitor array, it is 2 ^k -1 times of C1, and the capacitor array has two stages.
In the system using the stages, when k is an even number, it is 2 ^{(k + 2) / 2} -1 times, and when k is an odd number, it is 2 ^{(k-1) / 2} -1 times. Therefore, for example, when k = 8, in the DA conversion circuit of the present invention, the total capacitance of the capacitor arrays is 8 times C1, which is 255 times C1 in the system using one conventional capacitor array, or two capacitor arrays. Compared to 31 times that of the method used, the total capacitance of the capacitor array can be made smaller, so that the area required for making into an IC can be made smaller and the cost can be reduced.

FIG. 2 is a diagram showing a circuit configuration of a DA converter circuit according to a second embodiment of the present invention. This is the first of FIG.
This is a DA conversion circuit in which the second capacitor array 12, the charge transfer capacitance Cc, and the charge distribution capacitance Cv are added to the embodiment.

The operation will be described below. First, the reset signal Reset causes the reset means 13 to perform the capacitor array 1
1, 12 and charge transfer capacitance Cc, charge distribution capacitance Cv
, The charge of the capacitance CG of the integrating means 10 is reset. Next, each bit bi, / b of the k + m bit digital signal
With i (i = 1 to k + m), the reference potential selecting means 14 applies the selected reference potential to the other end of each capacitance Ci of the capacitor arrays 11 and 12. In FIG. 2, m = k, and the capacitances Ci of the capacitor arrays 11 and 12 are equal. Also,
Cc = C1 and Cv = (2k- ^k -1) C1. Further, the reference potential Vrefi (where i = 2 to n, n = k +
1) is given by Vrefi-Vref1 = 2 ^i-2 (Vref2-Vref1). At this time, the total sum Q1 of the charges accumulated in each capacitance Ci of the capacitor array 11 is In addition, the charge Q2 accumulated in the charge transfer capacitance Cc is Can be expressed as The charge Q accumulated in the capacitance CG of the integrating means 10
Is the sum of charge Q1 and charge Q2, Becomes Therefore, the output Vout is And becomes DA converted output. The maximum output amplitude is Vre
It is determined by f2-Vref1 and C1 / CG.

In this way, the number of reference potentials can be reduced. At this time, the total capacitance of the capacitor arrays 11 and 12 is 2 ^{k / 2} + k / 2 times C1 and can be made smaller than the total capacitance of the capacitor arrays required for the DA conversion circuit using the conventional capacitor array. .

FIG. 3 is a diagram showing a circuit of a third embodiment which is a modification of the circuit configuration of the second embodiment of the DA converter circuit of the present invention. The input digital signal has k + m bits, and the case where k = m + 1 and n = k + 1 is shown. Here, as in FIG. 2, Ci (i = 1 to k + m) = C1, Cc
= C1 and Vrefi (i = 3 to n) -Vref1 = 2 ^i-2 (Vref2-Vref1), and Cv = (2 ^k-1 -k-1) C
Set to 1.

At this time, the upper m bits bk + j (j = 1 to 1)
m) the capacitance Ck + j of the first capacitor array controlled by
By setting the reference potential applied to Vrefj + 1 to
An effect similar to that of the second circuit configuration shown in FIG.

FIG. 4 is a diagram showing a circuit of a fourth embodiment which is another modification of the circuit configuration of the second embodiment of the DA converter circuit of the present invention.

The input digital signal has k + m bits, and the case where k = m−1 and n = m + 1 is shown. Here, as in FIG. 2, Ci (i = 1 to k + m) = C
1, Cc = C1, and Vrefi (i = 2 to n) -Vref1 = 2
^i-2 (Vref2-Vref1), and Cv
By setting = (2k- ^k -1) C1, the same effect as the second circuit configuration shown in FIG. 2 can be obtained.

FIG. 5 is a diagram showing a circuit configuration of a DA converter circuit according to a fifth embodiment of the present invention. In the second embodiment shown in FIG. 2, the first capacitor array 11 is also used as the second capacitor array in a time division manner, and the switching means 15 for switching the upper k bits and the lower k bits of the digital input signal 15 is used. In addition, a switch SWBP for switching a path for bypassing the charge transfer capacitance Cc and a path for the charge distribution capacitance Cv by the switching signal ML between the upper bit and the lower bit, and a switch SWRV for resetting the charge distribution capacitance Cv are added. , Resetting the integrating means is performed by the first reset signal Reset.
At 1, the capacitance Ci, the charge transfer capacitance Cc, and the charge distribution capacitance Cv of the capacitor array are set to the second reset signal Reset.
2 is performed. Each capacitance Ci of the capacitor array 11
Are equal, and Cc = C1 and Cv = (2 ^k -k-1)
It is set as C1. Furthermore, the reference potential Vrefi (i = 2 to
n = n + 1) is given by Vrefi-Vref1 = 2i ^-2 (Vref2-Vref1).

The operation of the fifth embodiment will be described below. First, the charge of the capacitance CG of the integrating means 10 is reset by the first reset signal Reset1 and the second reset signal Reset2
Thus, the reset means 13 resets the capacitor array 11, the charge transfer capacitance Cc, and the charge distribution capacitance Cv. Next, the reference potential selection means 14 controls the reference potential to be connected by the capacitor array by the lower k bits selected by the switching means 15 for the upper k bits and the lower k bits of the digital input signal. At this time, by the switching signal ML between the high-order bit and the low-order bit, the charge sharing capacitance C is set by SWBP.
A route to v is selected. As a result, the charge Q2 accumulated in the capacitance CG of the integrating means 10 via the charge transfer capacitance Cc is Becomes Next, the capacitor array 11 is reset again by the second reset signal Reset2. Then, the reference potential selecting means 14 controls the reference potential to be connected to the capacitor array by the upper k bits selected by the upper k bits and the lower k bits switching means 15 of the digital input signal. At this time, the switching signal ML between the upper bit and the lower bit
Thus, the path that bypasses the charge transfer capacitance Cc is selected by SWBP. The charge Q1 further accumulated in the capacitance CG of the integrating means 10 by the capacitor array 11 is Therefore, the total sum Q of the charges accumulated in the capacitance CG of the integrating means 10 is

[0028] Becomes Therefore, the output Vout is And becomes DA converted output. The maximum output amplitude is Vre
It is determined by f2-Vref1 and C1 / CG.

By thus sharing the capacitor array by the time division operation, the capacitance can be further reduced as compared with the second embodiment of FIG.

As shown in the sixth embodiment of FIG. 6, the capacitance Ck of the capacitor array 11 controlled by the most significant bit in FIG. 1 is set to Ck = 2C1 and the other capacitor array 1
By setting the capacitance Ci of 1 as Ci = C1 and setting the reference potential applied to the capacitance Ck of the capacitor array 11 through the reference potential selecting means 14 to Vref1 and Vrefn-1, the total capacitance of the capacitor array is shown in FIG. Although it is increased by C1 as compared with the first embodiment, the reference potential can be reduced by one type. Similarly applied to FIG. 2, as in the seventh embodiment shown in FIG. 7, Ck and C2k whose reference potentials are controlled by the most significant bit of each of the capacitor arrays 11 and 12 are Ck = C2k = 2C1. It is also possible to set the capacitance Ci of the other capacitor array to Ci = C1. At this time, the charge distribution capacitance Cv is Cv = (2 ^k -k-
2) C1 should be set. Although not shown, FIG.
The same can be applied to the capacitor array of the fifth embodiment. Furthermore, the capacitor array 11 of the fourth embodiment of FIG.
In the same manner as in the eighth embodiment shown in FIG. 8, the capacitance Ck + m whose reference potential is controlled by the most significant bit of the capacitor array 11 is Ck + m = 2C1 and the reference potential selecting means 14 is used. The reference potential applied via Vref1 and Vrefn
It can also be -1.

Further, by applying it to FIG. 3, the capacitance C1 controlled by the least significant bit of the capacitor array 12 is connected in series with two capacitances C2 as in the ninth embodiment shown in FIG. = C2 / 2, the capacitance of another capacitor array Ci (i> 1) = C2, and Cv = (2 ^k-1 -k-
1/2) C1 is set so that the reference potential Vref2 applied to the capacitance C1 of the capacitor array 12 through the reference potential selection means 14 is set to the capacitance C2.
It may be shared as a reference potential applied via the.

In the above embodiment, the reset means 13 and the reference potential means 14 are provided separately. For example, FIG.
As in the tenth embodiment shown as a modification of the above embodiment, by controlling the input digital signal with the reset signal Reset by the transfer control means composed of, for example, OR and NOR, the reference potential means 14 and the reset means 13 are controlled. It can also have the function of.

Further, in the above description, the input digital signal is in the straight binary format, and at this time Vou
If the output range of t is Vref2-Vref1> 0, Vref1
On the other hand, if Vref2-Vref1 <0 on the minus side only, only the plus side on Vref1 will result. On the other hand, for example, a first modification shown in FIG. 11 as a modification of FIG.
As in the first embodiment, with respect to the reference potential Vref1 given as the AC GND of the integrating means 10, the reference potential Vre
If fi (i ≧ 3) is Vrefi-Vref1, V is when i is an odd number
Ref2-Vref1 is set to -2 ^{(i-3) / 2} times, and when i is an even number, it is set to 2 ^{(i-2) / 2} times Vref2-Vref1. Control the connection of the potential Vref2i, and use the digital signal bi bit to set the reference potential V
By controlling the connection of ref (2i + 1), it may be modified to obtain an output on both the plus and minus sides with respect to Vref1.

Further, when the input digital signal is a two's complement representation, for example, the reference potential Vrefn + 1-Vref1 is as shown in the twelfth embodiment shown in FIG.
If Vrefn-Vref1 is set to -1 times and used as a reference potential whose connection is controlled by the most significant bit b2k of the digital signal, outputs on both the positive and negative sides of Vref1 are obtained. Although not shown, the same applies to FIG. In the case of FIG. 1, the reference potential Vrefn is Vrefn−Vref1 = − (V
refn-1−Vref1). The same applies to the case of the fourth embodiment of FIG. Further, in the fifth embodiment of FIG. 5, the reference potential Vrefn + 1 is set to Vrefn + 1-Vref1 =-(Vrefn-1-Vre as in the thirteenth embodiment shown in FIG.
f1) so that Vrefn is selected by the switch SWS when the lower bit side is selected by the switching signal ML between the lower bit and the upper bit, and Vrefn + is selected by the switch SWS when the upper bit side is selected by the switching signal ML. You should choose 1.

It is also easy to add the function of controlling the polarity of the output by the polarity inversion signal INV, which is a digital signal whose input is represented by 2's complement. The polarity inversion of the two's complement digital signal is performed by inverting each bit bi of the digital signal and adding 1 to the least significant bit thereof. For example, in the case of the first embodiment of FIG. 1, first, as described above, the reference potential Vrefn is set to Vrefn−Vref1 = − (Vrefn−1−
Vref1) is set, but as in the fourteenth embodiment shown in FIG. 14A, the polarity inversion signal INV causes bi,
/ Bi, and a capacitance having a capacitance value equal to the capacitance C1 of the capacitor array whose connection to the reference potential is controlled by the least significant bit and whose connection to the reference potential Vref1 is controlled by the polarity inversion signal INV. Ca is added, and this capacitance Ca is added to each capacitance C of the capacitor array.
A reference potential similar to that of the first embodiment can be realized by adding a switch SWRINV for resetting at the same time as i to the reset means 14. The polarity reversing means 17 is shown in FIG.
It can also be realized by using an XOR and an inverter circuit as in the fifteenth embodiment shown in FIG. FIG. 16 shows a 16th embodiment applied to the 13th embodiment of FIG. In FIG. 16, the polarity reversing means 17 can reduce the circuit scale of the polarity reversing means 17 by half, for example, by placing the polarity reversing means 17 after the changeover switch means 15 for the upper bit and the lower bit. The addition of 1 to the least significant bit at the time of polarity inversion by the polarity inversion signal INV inputs the polarity inversion signal INV and the switching signal ML between the upper bit and the lower bit, selects the lower bit and adds at the time of polarity inversion. It may be controlled by the addition signal generating means 18 for generating a signal.

The capacitor column type DA converter circuit of the present invention described above has a smaller total sum of required capacitor array capacities than a conventional DA converter circuit using a capacitor array, and can be realized in a small chip area when integrated into an IC. Therefore, it is useful for an IC of a liquid crystal display drive circuit which requires a large number of DA conversion circuits. FIG. 17 shows the configuration of the liquid crystal display device. The liquid crystal display device drives a liquid crystal display 5, a scanning line selection circuit 8, and a liquid crystal cell 6 on a scanning line selected by the scanning line selection circuit 8 to transfer the accumulated image data for one scanning line, respectively. It is composed of a circuit 7. FIG. 18 shows the configuration of the liquid crystal display drive circuit, and FIG. 19 shows the timing of control signals. The operation will be briefly described. First, the shift register means 20 transfers a pulse STH representing the start of the effective image data period to give the latch timing of the image signals R, G, B in each latch of the latch means 21. In the horizontal blanking period, the reset signal R
By resetting each DA conversion circuit of the DA conversion means 23 by eset, the image data of one horizontal period is transferred from the latch means 21 to the latch means 22 by the data transfer pulse H, and after the reset period of the DA conversion means 23 is completed, the latch means is operated. The DA conversion means 23 converts the held image data from digital to analog and outputs it. D
When the drive capability of the A conversion means is low, it may be output via the latch means 24. Further, as shown in FIG. 20, the DA converter 23 may be output after the output is stabilized by the enable signal EN via the switch 25.

[0037]

As described above, since the capacitance column type DA conversion circuit according to the present invention can reduce the total capacitance of the capacitor array as compared with the conventional DA conversion circuit using the capacitor array, the IC It can be realized with a smaller chip area. This allows
For example, it is most suitable for the purpose of incorporating a plurality of DA conversion circuits in one-chip IC such as a liquid crystal display driving IC.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit of a DA converter circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a circuit of a second embodiment of a DA converter circuit of the present invention.

FIG. 3 is a diagram showing a modified example of the circuit of the third embodiment of the DA converter circuit of the present invention.

FIG. 4 is a diagram showing another modification of the circuit of the fourth embodiment of the DA converter circuit of the present invention.

FIG. 5 is a diagram showing a circuit of a DA converter circuit according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a circuit of a sixth embodiment as a modified example of the circuit of the embodiment of FIG.

7 is a diagram showing a circuit of a seventh embodiment as a modified example of the circuit of the embodiment of FIG.

FIG. 8 is a diagram showing a circuit of an eighth embodiment as a modification of the circuit of the embodiment of FIG.

9 is a diagram showing a circuit of a ninth embodiment as a modification of the circuit of the embodiment of FIG.

10 is a diagram showing a circuit of a tenth embodiment which doubles as a reset means and a reference potential selecting means in the embodiment of FIG.

11 is a diagram showing a circuit of an eleventh embodiment as a modified example in which the output potential range is expanded in the embodiment of FIG.

FIG. 12 is a diagram showing a circuit of a twelfth embodiment as a modified example of the embodiment of FIG. 2 when an input digital signal is a two's complement representation.

FIG. 13 is a diagram showing a circuit of a thirteenth embodiment as a modified example of the embodiment of FIG. 5 when the input digital signal is a two's complement representation.

FIG. 14 is a diagram showing a circuit of a fourteenth embodiment in which a polarity inversion function is added to the first embodiment when an input digital signal is a two's complement representation.

FIG. 15 is a diagram showing a circuit of a fifteenth embodiment as a specific example of the polarity inverting means.

FIG. 16 is a diagram showing a circuit of a sixteenth embodiment in which a polarity inversion function is added to the thirteenth embodiment when an input digital signal is a two's complement representation.

FIG. 17 is a diagram showing a configuration of a liquid crystal display device.

FIG. 18 is a circuit diagram showing an example in which the DA conversion circuit of the present invention is applied to a drive circuit of a liquid crystal display device.

19 is a diagram showing timings of signals and control signals in the embodiment of FIG.

FIG. 20 is a circuit diagram showing another example in which the DA conversion circuit of the present invention is applied to a drive circuit of a liquid crystal display device.

FIG. 21 is a diagram showing a conventional DA conversion circuit using one stage of a capacitor array.

FIG. 22 is a diagram showing a conventional DA conversion circuit using two stages of capacitor arrays.

FIG. 23 is a diagram showing an example of a control circuit for an input digital signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 integrating means 11 1st capacitor array 12 2nd capacitor array 13 resetting means 14 reference potential selecting means 15 changeover switch means for high-order bit and low-order bit of digital signal 16 transmission control means 17 polarity reversing means 18 addition signal generating means 20 Shift register means 21 Latch means 22 Latch means 23 DA conversion circuit

Claims (4)

[Claims] 1. A capacitor array having a plurality of capacitors commonly connected at one end thereof, and a capacitor connected to a common connection side of the capacitor array to integrate charges from the respective capacitors and reset the integrated charges by a reset signal. A capacitor array DA conversion circuit including at least an integrating unit for supplying a plurality of types of reference potentials having a predetermined relationship and different values to the individual capacitors of the capacitor array, and the capacitor array. A reset means connected between the other end of the capacitor array and the reference potential supply means and resetting each capacitance of the capacitor array by the reset signal, and connected to the other end of the capacitor array via the reset means. Optimum among multiple types of reference potentials by inputting multiple bit digital signals Capacity column type DA converter circuit comprising: the reference voltage selection means for selecting an object, the. 2. The capacitor array type DA according to claim 1, wherein a large number of capacitors of the capacitor array, each of which has one end commonly connected, have substantially equal capacitance values. Conversion circuit. 3. The i-th (n ≧ i ≧) at n kinds of reference potentials.
The absolute value of the difference voltage between the reference potential and the first reference potential in 3) is 2 ^j of the absolute value of the difference voltage between the second reference potential and the first reference potential.
N (n ≧ 3) types of reference potentials having a relationship of (n−2 ≧ j ≧ 1) times, a charge transfer capacitance that transfers the input charge, and an output of the charge transfer capacitance are input. An integrating means capable of resetting an electric charge integrated by a reset signal of 1, and a first capacitor array having k (k ≧ 2) capacitors, one end of which is commonly connected to the input of the integrating means. , M (m ≧ m), one end of which is commonly connected is connected to the input of the charge transfer capacitance and the charge distribution capacitance.
2) a second capacitor array consisting of two capacitors and a first capacitor array
And reset means for resetting the capacitance of the second capacitor array and the charge transfer capacitance and charge distribution capacitance by the first reset signal, and the other end of each capacitance of the first capacitor array is input k + m The upper k bits of the bit digital signal are selectively connected to either the a-th reference potential or the b-th (b ≠ a) reference potential, and the other end of each capacitance of the second capacitor array is Lower m of input k + m bit digital signal
2. The capacitor according to claim 1, further comprising a reference potential selection unit that is selectively connected to either the c-th reference potential or the d-th (c ≠ d) reference potential by a bit. Column type DA conversion circuit. 4. The i-th (n ≧ i ≧ n) of n kinds of reference potentials.
The absolute value of the difference voltage between the reference potential and the first reference potential in 3) is 2 ^j of the absolute value of the difference voltage between the second reference potential and the first reference potential.
Bits are provided for n (n ≧ 3) types of reference potentials having a relationship of (n−2 ≧ j ≧ 1) times, a charge transfer capacitance that transfers an input charge, and a path that bypasses the charge transfer capacitance. By-pass means formed by a selection signal, integrating means capable of resetting the charges integrated by the first reset signal when the output of the charge transfer capacitance is input, and one end commonly connected to the charge transfer capacitance A capacitor array composed of k (k ≧ 2) capacitors connected to an input and a charge distribution capacitor, and the capacitance of the capacitor array and the charge transfer capacitance and the charge distribution capacitance are reset by a second reset signal. Reset means, switch means for selecting upper k bits and lower k bits of the 2 kbit digital signal input by the bit selection signal, and the capacity. The other end of each capacitor of the array is composed of a reference potential selecting means selectively connected to either of two different reference potentials depending on the k-bit digital signal selected by the switch means. The capacitor array DA conversion circuit according to claim 1, which is characterized in that.