JPH06252376A - Wiring structure of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To provide the wiring structure of solid-state image pickup element which enables the higher-speed operation of a device by lowering the resistance value of a bus line without changing the shape of a bus line itself. CONSTITUTION:In wiring structure, which has shunt wiring 13 for applying four phases of transfer clocks phi1-phi4 to each transfer electrode of a plurality of vertical transfer parts and four pieces of bus lines 141-144 for supplying transfer clocks phi1-phi4 separately for each phase to the shunt wiring 13, being arranged, in the condition of crossing the end, at the end of this shunt wiring 13, the shunt wiring 13 crosses the bus line 141 on the side of a vertical transfer part alternately within one group, with four pieces as a group, out of four pieces of bus lines 141-144. The points where the shunt wiring 13 crosses the bus line 141 are reduced to half the number of vertical transfer rows.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device wiring structure, and more particularly to a shunt wiring structure for applying a transfer clock to each transfer electrode of a plurality of vertical transfer portions.

[0002]

2. Description of the Related Art As a charge transfer method, FIT (Frame Int
A CCD solid-state image pickup device adopting an erline transfer) method is known. As is clear from FIG. 3 showing the basic structure of the FIT CCD solid-state image pickup device, a plurality of photosensors 11 that are two-dimensionally arranged in a matrix and accumulate signal charges according to the amount of incident light, and vertical columns thereof. In addition to the image pickup unit 1 having the vertical shift register 12 which is arranged for each of the photosensors 11 and vertically transfers the signal charges read from the photosensors 11, each of the vertical shift registers 12 of the image pickup unit 1 has a vertical shift register 12. A vertical shift register 21 that is continuous for each column is provided, and a storage unit 2 that reduces smear components by high-speed charge transfer is provided. The storage part 2 is entirely covered with a light shielding layer (not shown) made of an aluminum layer.

In the image pickup section 1, the signal charges photoelectrically converted and accumulated by the photosensor 11 are read out to the vertical shift register 12 and transferred at high speed to the accumulation section 2 by the register 12. The signal charges transferred to the storage unit 2 are transferred at high speed to the horizontal shift register 3 by the vertical shift register 21 in units corresponding to one scanning line. 1
The signal charges for the scanning lines are sequentially transferred in the horizontal direction by the horizontal shift register 3. An output circuit unit 4 including an FDA (Floating Diffusion Amplifier) or the like is provided at the output end of the horizontal shift register 3, and the signal charge obtained by photoelectric conversion in the image pickup unit 1 is converted into a signal voltage to generate a pixel signal. Take it out.

A 2 million pixel FIT CCD solid-state image pickup device is known as a solid-state image pickup device capable of increasing the number of pixels in a television system such as an HD (High Definition) TV. Since this FIT type CCD solid-state image pickup device for HDTV needs to operate at high speed, a shunt wiring structure is adopted in order to suppress the propagation delay of each transfer electrode of the vertical shift registers 12 and 21. In addition, since the chip area is large, the vertical shift register 1
Since the load capacities of 2 and 21 are large, as shown in FIG.
By separating the shunt wirings 13 and 22 for applying a transfer clock to each transfer electrode of these vertical shift registers in the image pickup section 1 and the storage section 2, each shunt wiring 1
The load capacities for 3, 22 are halved to prevent propagation delay of the transfer clock.

That is, in FIG. 4, the transfer electrodes of the vertical shift register in the image pickup unit 1 are supplied with four-phase transfer clocks φ1 to φ4 via the shunt wiring 13 and the loop-shaped bus line 14 extending in the vertical direction. Is applied. The bus line 14 is for supplying the transfer clocks φ1 to φ4 in common to each of the plurality of shunt wirings 13, and is composed of four pattern wirings 14 _{1 to} 14 ₄ corresponding to four phases. There is. A bonding pad 15 is formed on each of the pattern wirings 14 _{1 to} 14 _4.
Four-phase transfer clocks φ1 to φ4 are applied from external terminals (not shown) of the chip via ₁ to 15 ₄ .

On the other hand, the transfer electrode of the vertical shift register in the storage section 2 has a shunt wiring 2 extending in the horizontal direction.
The four-phase transfer clocks [phi] 1 to [phi] 4 are applied via the two and the loop-shaped bus line 23. The bus line 23 is for supplying the transfer clocks φ1 to φ4 commonly to each of the plurality of shunt wirings 22, and four pattern wirings 23 ₁ to 23 ₄ corresponding to four phases are provided.
It consists of Four-phase transfer clocks φ1 to φ4 are applied to each of these pattern wirings 23 ₁ to 23 _{4 from} an external terminal (not shown) of the chip via bonding pads 24 _{1 to} 24 ₄ .

FIG. 5 shows an outline of the shunt wiring in the image pickup section 1, and FIG. 6 shows its planar structure. As the shunt wiring 13, one formed by finely processing the first aluminum layer forming the light shielding layer is used. The shunt wiring 13 made of the first aluminum layer (1st-Al) extends in the vertical direction on the vertical shift register between pixels in the horizontal direction (between the left and right photosensors 11, 11), and each transfer electrode Are connected to the polysilicon (1Poly, 2Poly) electrodes 16 and 17 of the two-layer structure, which are formed at a plurality of positions, via contacts 18 and 19. Here, focusing on a certain phase (for example, φ2), as is apparent from FIG. 7, one shunt wiring covers four transfer electrodes.

[0008]

However, in the conventional wiring structure having the above structure, the cross-sectional structure diagram of FIG. 8 (A of FIG. 5) is used.
-A 'line sectional view), the bus line part is formed on the shunt wiring (1st-Al) 13 via the interlayer insulating film 2
Bus line 1 consisting of the second aluminum layer (2nd-Al)
4 has a cross-sectional structure that crosses, and the resistance value of the bus line 14 is high due to the influence of the step of the shunt wiring (1st-Al) 13, so the operating frequency of the device is regulated by this portion. In order to reduce this resistance value, the wiring width of the bus line (2nd-Al) 14 may be widened or the film thickness thereof may be thickened. There was a problem such as the difficulty of processing.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the resistance value of the bus line without changing the shape of the bus line itself, thereby enabling higher speed operation of the device. It is to provide a wiring structure of the solid-state imaging device.

[0010]

A wiring structure of a solid-state image pickup device according to the present invention has a structure in which each transfer electrode of a plurality of vertical transfer parts has n electrodes.
A shunt wiring for applying a phase transfer clock, and a shunt wiring arranged at an end of the shunt wiring in a state intersecting with the end so as to supply the transfer clock for each phase to the shunt wiring.
In the wiring structure of the solid-state imaging device having two bus lines, the point where the shunt wiring intersects the bus line on the vertical transfer unit side among the n bus lines is more than the number of vertical transfer columns. It is configured to be set less.

[0011]

With respect to the bus line on the vertical transfer unit side among the n bus lines, the n shunt wirings are made to intersect with each other, for example, in every one group or every other group. As a result, the number of points where the shunt wiring intersects the bus line is half the number of vertical transfer columns,
The number of steps on the bus line can be reduced to half that of the conventional structure. Since the resistance of the bus line is almost determined by the number of steps, the number of steps can be reduced to 1/2 of the conventional structure, and the resistance of the bus line can be reduced to about 1/2 of that of the conventional structure. It is possible to realize higher speed operation.

[0012]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a configuration diagram showing a first embodiment of the present invention, and shows a case where it is applied to an image pickup section 1 of the FIT type CCD solid-state image pickup device shown in FIG. Note that FIG. 1A shows an outline of wiring and FIG. 1B shows a partial cross-sectional structure taken along the line BB ′ of FIG. In FIG. 1, each transfer electrode of the vertical shift register (vertical transfer unit) in the imaging unit is
For example, via a wiring structure including a shunt wiring 13 extending in the vertical direction and a loop-shaped bus line 14 arranged at the end of the shunt wiring 13 in a state of intersecting the end and electrically connected, for example, 4 Phase transfer clocks φ1 to φ4
Is applied.

The bus line 14 is for supplying the transfer clocks φ1 to φ4 commonly to each of the plurality of shunt wirings 13, and four pattern wirings 14 _{1 to} 14 ₄ corresponding to four phases. It consists of The bonding pad 15 ₁ is attached to each of the pattern wirings 14 _{1 to} 14 _4.
15 ₄ through 4 from outside the chip terminals (not shown)
Phase transfer clocks φ1 to φ4 are applied. On the other hand, the shunt wirings 13 are provided by the number corresponding to the vertical transfer column, and the four pattern wirings 14 _{1 to} 14 of the bus line 14 are provided.
Of the _four , the pattern wiring on the vertical transfer unit side, in other words, the outermost pattern wiring in the loop (in this example, the pattern wiring 14 ₁ of the first phase) is grouped into four groups within one group. It is wired so that every other wire intersects.

That is, in FIG. 1A, the shunt wiring 13 ₁ in the leftmost group has the first phase (φ1).
And two shunt wirings of the third phase (φ3), and in the next shunt wiring 13 ₂ , _two shunt wirings of the second phase (φ2) and the fourth phase (φ4) are the first phase of the bus line 14. intersection pattern wiring 14 _1, respectively, are connected to the pattern wiring 14 _{1-14 4} four bus lines 14 phase (.phi.1 to .phi.4) in correspondence. In this way, among the _four pattern wirings 14 _{1 to} 14 ₄ of the bus line 14, four shunt wirings 13 are grouped with respect to the outermost pattern wiring 14 ₁ in the loop, one in one group. By intersecting every other, the shunt wiring 13 becomes the pattern wiring 14
The number of points that intersect ₁ is half the number of vertical transfer columns.

As a result, as is apparent from FIG. 1B, the second layer of aluminum is formed on the shunt wiring 13 formed of the first layer of aluminum (1st-Al) through the interlayer insulating film 20. In the cross-sectional structure traversed by the bus line 14 composed of the layer (2nd-Al), the number of steps of the pattern wiring 14 ₁ can be reduced to half that of the conventional structure. Therefore, since the resistance of the bus line 14 is determined almost by the number of steps, the resistance of the pattern wiring 14 ₁ can be reduced to about 1/2 of that of the conventional structure, and a higher speed operation of the device can be realized.
On the other hand, since the capacity is almost unchanged, the bus line 14
The drive limit frequency due to the propagation delay at is almost doubled. Further, in the second (second phase) pattern wiring 14 ₂ from the outside of the loop of the bus line 14, the number of steps is reduced to 1/3 of the conventional structure.

In the conventional structure, one shunt wiring covers four transfer electrodes, whereas in the present structure,
One shunt wiring covers eight transfer electrodes, and the capacitance doubles as compared with the conventional structure. However, since there is a sufficient margin with respect to the driving frequency, there is no problem in propagation delay even if the capacitance doubles. It is a level. Also, the pattern wiring 14 ₁
The shunt wiring 13 that does not intersect with is not removed completely, but is left on the vertical shift register as in the conventional structure, and only the portion that intersects with the pattern wiring 14 ₁ is thinned out. By doing so, the shunt wiring 13 always exists on any line on the transfer electrode, and the upper structure of the light receiving portion becomes uniform, so that a phenomenon such as sensitivity unevenness caused by the nonuniformity of this portion is caused. It does not cause the occurrence of.

FIG. 2 is a schematic wiring diagram showing a second embodiment of the present invention. In this embodiment, the shunt wiring 13
Of the bus line 14 are arranged so that every four groups are wired so as to intersect the pattern wiring 14 ₁ of the bus line 14. That is, in the shunt wiring 13 ₁ of the leftmost group, all the shunt wirings intersect the pattern wirings 14 ₁ of the first phase of the bus line 14, and the four pattern wirings 14 _{1 to} 14 ₄ of the bus line 14 are connected to the phase ( φ1
~ Φ4), all the shunt wirings are connected to the pattern wiring 1 in the shunt wiring 13 ₂ of the second group from the left.
4 ₁ is cut at the front so as not to intersect with.
After that, the above configuration is repeated.

As described above, the shunt wiring 1 is provided for the outermost pattern wiring 14 ₁ in the loop of the bus line 14.
By crossing every 3 groups with 4 groups of 3s, the point where the shunt wiring 13 intersects with the pattern wiring 14 ₁ becomes 1/2 of the number of vertical transfer columns. As a result, similarly to the case of the first embodiment, the resistance of the pattern wiring 14 ₁ can be reduced to about 1/2 of that of the conventional structure, so that the device can be operated at higher speed and the upper structure of the light receiving portion can be prevented. The occurrence of a phenomenon such as uneven sensitivity caused by the uniformity does not occur.

In each of the above embodiments, the FI shown in FIG.
The case where the invention is applied to the shunt wiring structure in the image pickup unit 1 of the T-type CCD solid-state image pickup device has been described. Not only the device but also the IT type CCD solid-state imaging device can be applied. In addition, in each of the above embodiments, one shunt wiring
The number of shunt wirings 13 intersecting the pattern wiring 14 ₁ of the bus line 14 is determined so as to cover one transfer electrode, but the number of transfer electrodes covered by one shunt wiring is not limited to eight. , Can be set freely within the range where propagation delay does not matter.

Further, it is not always necessary to regularly thin out the shunt wiring, and the pattern wiring 14 _{1 of the} bus line 14
On the other hand, if the number of intersections of the shunt wirings 13 is at least one less than the number of vertical transfer columns, the resistance of the pattern wirings 14 ₁ of the bus lines 14 can be reduced as compared with the conventional structure. It will be possible to realize higher speed operation. Furthermore, in each of the above embodiments, the vertical transfer drive is applied to the case of four-phase drive, but the present invention is not limited to four-phase drive.

[0021]

As described above, according to the present invention,
Of the n bus lines, the shunt wiring is connected to the bus line on the vertical transfer unit side, and n lines are grouped, for example, 1
By arranging every other line in the group or every other group, the point where the shunt wiring intersects with the bus line becomes ½ of the number of vertical transfer columns, and the number of steps of the bus line is reduced to the conventional structure. Since the resistance of the bus line can be reduced to about 1/2 of that of the conventional structure, higher speed operation of the device can be realized.

[Brief description of drawings]

1A and 1B are configuration diagrams showing a first embodiment of the present invention, in which FIG. 1A shows an outline of wiring and FIG. 1B shows B in FIG. 1A.
The partial cross-sectional structures of the -B 'line are shown respectively.

FIG. 2 is a wiring schematic diagram showing a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a FIT type CCD solid-state imaging device.

FIG. 4 is a wiring diagram showing a conventional wiring structure.

FIG. 5 is a schematic wiring diagram of the imaging unit in FIG.

FIG. 6 is a plan view showing the shunt wiring of the image pickup section.

FIG. 7 is a schematic plan view showing the relationship between a single shunt wire and a transfer electrode.

8 is a cross-sectional structural view of a part of line AA ′ in FIG.

[Explanation of symbols]

 1 Imaging Unit 2 Storage Unit 3 Horizontal Shift Register 11 Photo Sensor 12 Vertical Shift Register 13,22 Shunt Wiring 14,23 Bus Line

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI technical display 7210-4M H01L 27/14 D

Claims (3)

[Claims] 1. A shunt wire for applying an n-phase transfer clock to each transfer electrode of a plurality of vertical transfer parts, and an end part of the shunt wire which is arranged in a state of intersecting the end part to the shunt wire. On the other hand, a wiring structure of a solid-state imaging device having n bus lines for supplying the transfer clock for each phase, wherein the bus line on the vertical transfer unit side of the n bus lines is A wiring structure of a solid-state imaging device, wherein the number of intersections of the shunt wirings is set to be smaller than the number of vertical transfer columns. 2. The shunt wiring intersects with the bus line on the vertical transfer unit side every other group in a group of n lines.
The wiring structure of the solid-state imaging device described. 3. The wiring structure of a solid-state image pickup device according to claim 1, wherein the shunt wiring intersects the bus line on the vertical transfer unit side in groups of n pieces every other group. .