JPH06252076A - Method of manufacturing semiconductor device and its manufacturing device - Google Patents

Abstract

PURPOSE:To reduce charge-up damages to an element on a wafer by a method wherein, after a wafer is processed in a step that it is apprehended that the charge-up damages are generated, ultraviolet rays are emitted to the processed wafer. CONSTITUTION:Etching gas is introduced into within a reaction chamber 1 to regulate pressure within the reaction chamber 1, thereafter high frequency is applied from a high frequency power source 8 to a lower electrode 7. At the time when etching of a conductive film advances and each wire is isolated, such a condition is generated that the charge-up is the easiest to occur. After the etching is completed, a wafer W is transferred to an unload chamber 5 and ultraviolet rays are emitted from a mercurry lamp 15 to the wafer W. Thus, the charge-up of the wafer W is eliminated. Thus, it is possible to reduce charge-up damages of the wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a manufacturing apparatus therefor, and more particularly, to a semiconductor device manufacturing process in which a wafer is charged up immediately by a plasma process, ion implantation, electron beam irradiation, etc. By removing it, the effect on the element is reduced, and the yield and reliability of the product are improved.

[0002]

2. Description of the Related Art During a semiconductor device manufacturing process, a plasma process such as plasma etching or plasma CVD, ion implantation or electron beam irradiation causes charge-up on a wafer being processed, resulting in damage such as element destruction or deterioration. It includes processes that are easy to receive. In 1983, Toshiba Corp.'s Yoshida and Watanabe reported a charge-up damage phenomenon related to dry etching (1983 Dry P
Rocess Symposium, I-2, proceedings p4), and since then, many studies have been conducted to investigate damage to plasma processes and devices. Among those series of studies, 1987
Announced by Arikado et al. Of Toshiba Corporation (8th
International Symposium on Plasma Chemistry, C-II
I), a mode in which nonuniformity of plasma (variation of Vdc) is very deeply related to charge-up damage is particularly important and widely known.

Since this announcement, in order to reduce the damage to the element due to the plasma process, a device has been devised to make the plasma more uniform and the Vdc smaller. For example, ECR (Electron Cyclotron R
esonance) Etching, MERIE (Magnetron Enhanc
In processing using a magnetic field such as ement Reactive Ion Etching), it is devised so that the magnetic field orientation is as uniform as possible in the vicinity of the wafer to be processed. Further, in the former ECR etching, many devises have been made on the frequency of the bias to be applied.

In the case of ion implantation that handles charged particles, charge-up damage similarly poses a problem. In ion implantation, since only positive ions are implanted into the wafer, the charge imbalance is large. Therefore, the device is devised to keep the charge balance by irradiating electrons at the same time as ion implantation (so-called electron shower).

As a method of preventing charge-up at the time of ion implantation, in JP-A-3-25929, the surface of a wafer is covered with an amorphous recon and the amorphous recon is made conductive by irradiating ultraviolet rays during the ion implantation. Proposals to do so have also been made. On the other hand, with respect to electron beam irradiation, it has been conventionally used as a length measurement SEM (scanning electron microscope) for inspection in the semiconductor manufacturing process, but recently, electron beam exposure in the PEP (Photo Engravement Process) process (hereinafter , EB exposure). This EB exposure is also a process in which charge-up easily occurs, and a conductive resist has been developed to prevent the charge-up.

[0006]

The problems of the prior art relating to the prevention of charge-up when a wafer is subjected to processing such as plasma process, ion implantation and electron beam irradiation are as follows. In the conventional plasma process of semiconductor manufacturing process,
A method for making the plasma uniform is an approach for basically preventing the wafer from being charged up. However, in the 39th Joint Lecture on Applied Physics 28p-NC-10, Otsubo showed that if the secondary electron emission rate between the surface to be processed of the wafer and the inner wall of the etching chamber was different, the bulk plasma was uniform. Also showed the research result that an imbalance of positive and negative incident charges may occur on the wafer.

On the other hand, in the case of plasma etching, the surface of the wafer to be etched is a conductor and the base is an insulating film, and vice versa. The same applies to the case of plasma CVD, and in some cases the insulating film may be deposited on the surface where the conductor wiring is formed in the initial state. That is,
In the case of these plasma processes, in view of the above research results, even if the bulk plasma is made uniform, charge imbalance occurs on the wafer, which means that a complete charge-up free state cannot be obtained.

Therefore, a complete charge-up free is not required, and even if the charge-up is good to some extent as long as it does not affect the element, the conventional plasma etching apparatus or plasma CVD apparatus can provide uniform plasma. There was no particular countermeasure against charge-up damage other than the device to try. Therefore, there is a problem on the device user side that once a certain device is adopted, it is only possible to rely on the performance peculiar to the device for preventing charge-up damage.

Further, with respect to the electron shower performed to maintain the balance of charges in the ion implantation, it is difficult to quantitatively and precisely control the electron shower, and the implantation result may be delicate depending on the conditions of the electron shower. There was a problem that there was a difference. As a method for preventing charge-up during ion implantation, Japanese Patent Laid-Open No. Hei 3
No. 25929 is effective in the case of implanting the entire surface of the wafer, but cannot prevent charge-up of the photoresist when the photoresist is used (photoresist is a conductive film). Since it is above, charge-up is more likely to occur). Further, the formation and peeling of the amorphous silicon film used in this method cause a large increase in cost, and there are various technical problems in peeling.

In the case of electron beam irradiation used for EB exposure,
Since the development profile has the highest priority, there is a limit to making it conductive, and since it is a negative resist, there is a problem that charge-up damage is likely to remain on the element as it is. Therefore, the present invention has been made by paying attention to the above-mentioned conventional problems, and by rapidly removing charges accumulated on a wafer by a plasma process, ion implantation, electron beam irradiation, etc. in a semiconductor manufacturing process, An object of the present invention is to provide a method and an apparatus for manufacturing a semiconductor device capable of reducing charge-up damage to the upper element, and to solve the above conventional problems.

[0011]

In order to achieve the above object, the semiconductor manufacturing method of the present invention processes a wafer in a process that may cause charge-up damage such as plasma process, ion implantation, and electron beam irradiation. After that, the wafer to be processed is irradiated with ultraviolet light. Further, in the semiconductor device manufacturing apparatus of the present invention, the load lock chamber is provided with means for irradiating the wafer to be processed with ultraviolet light immediately after performing a process that may cause charge-up damage such as plasma process, ion implantation, or electron beam irradiation. It is characterized in that it is provided on the unload side of.

[0012]

According to the present invention, when the wafer is subjected to processing such as plasma process, ion implantation, and electron beam irradiation, it does not prevent charge-up from occurring on the wafer to be processed. This is to reduce the influence on the element. In the past, many discussions have been made about damage that occurs during plasma irradiation,
There was no problem after the plasma irradiation. The present inventor has diligently studied from this point of view, and the 53th Annual Meeting of the Japan Society of Applied Physics 17p-S
As indicated by K-13, the present invention has been completed based on the knowledge that once the charge-up occurs, the effect of the charge-up will remain unless a process for discharging the charge is performed.

Generally, as processes for releasing charges in the manufacture of semiconductor devices, there are heat treatment of wafers, plasma treatment, cleaning treatment with a liquid having a low specific resistance, and the like. Further, as a more reliable and effective treatment, a method of irradiating with ultraviolet rays has been conventionally known. However, irradiation of ultraviolet rays has not been used as a semiconductor manufacturing process.

According to the present invention, a wafer is subjected to plasma processing,
By performing a process such as ion implantation process and electron beam irradiation process in which charge-up is likely to occur and then irradiating this wafer with this ultraviolet ray rapidly, damage in the case of charge-up is reduced. It is a thing. Incidentally, JP-A-63-128722 and JP-A-63-128722
No. 117424 discloses a technique of utilizing ultraviolet energy in a plasma process such as etching and CVD. These techniques use the ultraviolet irradiation to release the charge of the wafer and reduce the charge-up damage. Is essentially different from the technical idea. While the present invention is intended to obtain a charge-up damage reduction effect with a minimum amount of post-treatment in the extension of the conventional process of semiconductor manufacturing, the conventional ultraviolet energy utilization technique described above is the reaction itself of the process. Is a completely different field.

Thus, according to the present invention, the charge-up damage in the manufacturing process of the semiconductor device is reduced by the simple means of irradiating with ultraviolet rays, thereby enhancing the reliability of the semiconductor device and improving the yield in the manufacturing process. It is possible to improve the product quality and productivity.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. This is an example of the plasma etching process, especially in the case of wiring processing in which sufficient heat treatment cannot be applied after etching and therefore damage that cannot be removed by annealing out is likely to remain.

FIG. 1 is a schematic sectional view of an etcher for wiring processing of a semiconductor device according to an embodiment of the present invention. A load lock chamber 3 is provided on the left side of the central reaction chamber 1 via a gate valve 2, and an unload lock chamber 5 is provided on the right side via the other gate valve 4 of the same. Of the pair of parallel plate electrodes arranged in the reaction chamber 1, the upper electrode 6 is grounded,
The lower electrode 7 on which the wafer W to be processed is placed is connected to a high frequency power supply 8. A supply port 10 for etching gas (Cl ₂ and BCl ₃ ) supplied from a cylinder (not shown) through the mass flow controllers 9a and 9b is provided in the upper part of the reaction chamber 1, and a conductance valve 1 is provided in the lower part of the reaction chamber 1.
An exhaust port 12 is provided through 1 to an exhaust pump (not shown). Further, exhaust ports 13 and 14 leading to exhaust pumps (not shown) are provided in the lower portions of the load lock chamber 3 and the unload lock chamber 5, respectively. Further, a mercury lamp 15 is installed above the interior of the unload lock chamber 5 as a means for irradiating ultraviolet light.

Using this etcher for wiring processing, the wafer on which the resist pattern is formed is etched as follows. The wafer W to be processed is first introduced into the load lock chamber 3. The air in the load lock chamber 3 is exhausted from the exhaust port 13, and the wafer W is placed in vacuum. Next, the wafer W is guided to the reaction chamber 1 separated by the gate valve 2 and placed on the lower electrode 7. The conductance valve 11 of the reaction chamber 1 is opened, and the chamber is once evacuated to, for example, 1/100 of the etching pressure. After that, the etching gas flows into the reaction chamber 1 at a predetermined flow rate (for example, C
L ₂ is introduced at 70 sccm and BCl ₃ is introduced at 30 sccm). The pressure in the reaction chamber 1 is controlled by the conductance valve 1
After adjusting to 100 Pa by adjusting the opening of 1, for example, 13.56 Hz, 2 W from the high frequency power source 8
A high frequency (RF wave) of / cm ² is applied to the lower electrode 7.
As a result, the etching gas in the reaction chamber 1 becomes a plasma state, the active ions are vertically incident on the upper surface of the wafer, and the wafer W is anisotropically etched.

2 to 4 schematically show the mechanism of charge-up occurring on the wafer W during etching. A gate electrode 24 made of polysilicon is formed on a silicon substrate 21 via a LOCOS 22 for element isolation and a gate oxide film 23. A conductor film 26 made of an aluminum compound such as Al-0.5% Cu is vapor-deposited on the interlayer insulating film 25 covering it.
The conductor film 26 is being plasma-etched using the photoresist 27 formed thereon as a mask. As shown in FIG. 2, the photoresist 27 existing in a floating state on the conductor film 26 is in a state where electrons 30 in the plasma are accumulated and are very easily charged up. At this time, the gate oxide film 23 has a small potential difference between the gate electrode 24 and the silicon substrate 21 and is hardly stressed. As the etching of the conductor film 26 progresses,
As described above, a state in which charge-up is most likely to occur occurs when the individual wirings are isolated, and the stress due to this charge-up continues to be applied while the interlayer insulating film 25 is over-etched.

When the etching is completed, as shown in FIG. 4, the charge moves to a portion having a large capacity, but the charge accumulated in the photoresist 27 or the like is completely lost and the influence thereof disappears. Not up to.
When the wiring patterning by etching is completed in this way, the inside of the reaction chamber 1 is evacuated to a predetermined pressure again, and then the wafer W is transferred to the unload lock chamber 5 separated via the gate valve.

In the unload lock chamber 5, the wafer W
On the other hand, with the mercury lamp 15, for example, 3 W at 1 W / cm ² .
UV irradiation for a minute is performed. 30 mercury lamps
It has a function of emitting ultraviolet rays of 0 nm or less to release the charge accumulated in the wafer W. This ultraviolet irradiation eliminates the charge-up of the wafer W. When the etching is completed early, the power of the mercury lamp 15 may be increased to shorten the processing time of ultraviolet irradiation. In this way, this etching process is not rate-controlled in the step of ultraviolet irradiation, and it is possible to prevent the throughput of the manufacturing process of the semiconductor device from decreasing.

After the above etching, the photoresist 27 was removed by ashing and washing with an organic solvent, and a silicon gate MOSFET having wiring formed was obtained. FIG. 5 shows some of the process flows in the case where the ultraviolet irradiation, which is the process of the present invention, is performed during the semiconductor device manufacturing process, particularly during the process from etching to ashing. Process I is wafer "etching"
After that, "ultraviolet ray irradiation" is performed, followed by "ashing" treatment, and then ultraviolet ray irradiation again to wash the organic solvent. On the other hand, Process II is a process in which "etching" and "ashing" are continuously performed, and ultraviolet rays are irradiated only immediately after the ashing, and it is preferable to apply when the time between "etching" and "ashing" is short. . In addition, when using an asher with extremely small damage as in the downflow method, UV irradiation is performed only immediately after "etching" as in process III, and then UV light is used after "ashing" performed thereafter. You may make it wash | clean an organic solvent as it is, without irradiating.

In the above embodiment, the load lock chamber 3 and the unload lock chamber 5 of the etching apparatus are provided separately on both sides of the reaction chamber 1, but the present invention is not limited to this, and the load lock chamber 3 is not limited thereto. The unload lock chamber 5 and the unload lock chamber 5 may be combined into one chamber. Further, an asher may be attached in series to the reaction chamber 1 to be subjected to etching so that the ultraviolet irradiation after the ashing can be easily performed.

A heating stage may be attached to the load lock chamber 3, the wafer W may be exposed to an oxygen or ozone atmosphere at the stage, and resist ashing may be performed in the unload lock chamber 5. In short, it is important to irradiate ultraviolet rays as soon as possible after performing a process in which charge-up may occur, and do not leave the charge-up state for a long time and leave no damage until the next step.

Further, in the above-mentioned embodiment, the case of dry etching is taken as an example, but it goes without saying that these can be suitably applied to the steps of plasma CVD, ion implantation, EB irradiation and the like. Also, the present invention does not necessarily have to be performed immediately after every plasma process. This is because, as is well known, various damages of the process are largely mitigated by the high temperature heat treatment in the process before the wiring is provided on the wafer. INDUSTRIAL APPLICABILITY The present invention is particularly effective in the steps after the wiring formation, which cannot be subjected to the high temperature heat treatment.

[0026]

As described above, according to the present invention,
Plasma processing, ion implantation, electron beam irradiation, etc. are performed because the wafer to be processed is irradiated with ultraviolet light after processing the wafer in a process that may cause charge-up damage such as plasma process, ion implantation, or electron beam irradiation. Even if a charge-up occurs due to the process of, the charge can be easily and quickly removed from the wafer to reduce the charge-up damage of the wafer,
This has the effect of improving the reliability of the semiconductor device and improving the yield in the manufacturing process.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing one embodiment of a semiconductor device manufacturing apparatus according to the present invention.

FIG. 2 is a schematic diagram illustrating a mechanism in which charge-up occurs when wiring processing is performed on a wafer by the apparatus of FIG.

FIG. 3 is a schematic diagram illustrating a mechanism in which charge-up occurs when performing wiring processing on a wafer by the apparatus of FIG.

FIG. 4 is a schematic diagram illustrating a mechanism in which charge-up occurs when wiring processing is performed on a wafer by the apparatus of FIG.

FIG. 5 is a diagram showing a process flow after a wiring etching process according to the present invention.

[Explanation of symbols]

 1 Reaction chamber 3 Load lock chamber 5 Unload lock chamber 15 Ultraviolet irradiation means (mercury lamp)

Claims (2)

[Claims] 1. A semiconductor device manufacturing method, wherein a wafer to be processed is irradiated with ultraviolet light after the wafer is processed in a process such as plasma process, ion implantation, electron beam irradiation, or the like that may cause charge-up damage. Method. 2. A means for irradiating ultraviolet rays to a wafer to be processed immediately after performing a process that may cause charge-up damage such as plasma process, ion implantation, electron beam irradiation, etc. is provided on the unload side of the load lock chamber. A semiconductor device manufacturing apparatus characterized by the above.